TRF3761-EIRHARG4

TRF3761_07 TI | Alldatasheet

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FEATURES

APPLICATIONS

(TOP VIEW) GND AVDD_BIAS RBIAS1 GND VCTRL_IN AVDD_VCO AVDD_BUF AVDD_CAPARRAY GND AVDD (See□Note A) PD_OUTBUF CHIP_EN CLOCK DATA STROBE DGND DGND DVDD1 AVDD_PRES GND DVDD2MUX_OUTREF_INGNDAVDD_REFAVDD_CPCPOUTGNDAVDDGND GNDGND VCO_OUTPVCO_OUTM AVDD_OUTBUF GND AVDD_VCOBUF EXT_VCO_IN RBIAS2 GND 383940 37 36 35 34 33 32 31 131211 14 15 16 17 18 19 20 To□Microcontroller To□Microcontroller REF 1000□pF 2.37□kΩ 10□pF 10□pF 120 Ω 120 Ω VDDVDD LOAD 1000□pF 4.75□kΩ

DESCRIPTION

Noise: 137dBc/Hz (at 600kHz, f VCO of 1.9GHz Low Noise Floor: 158dBc/Hz at 10MHz Offset Integer-N PLL Input Reference Frequency range: 10MHz to 104MHz VCO Frequency Divided by 2-4 Output Output Buffer Enable Pin Programmable Charge Pump Current Hardware and Software Power Down 3-Wire Serial Interface Single Supply: 4.5V to 5.25V Operation Wireless Infrastructure WCDMA, CDMA, GSM Wideband Transceivers Wireless Local Loop RFID Transceivers See the Application Information section for Clock generation Loop Filter Design procedures. IF LO generation AVAILABLE DEVICE OPTIONS Div by Div by Div by PART NUMBER Fstart Fstop Fstart Fstop Fstart Fstop TRF3761-A 1493 1608 746.5 804 373.25 402 TRF3761-B 1595 1711 797.5 855.5 398.75 427.75 TRF3761-C 1660 1790 830 895 415 447.5 TRF3761-D 1740 1866 870 933 435 466.5 TRF3761-E 1805 1936 902.5 968 451.25 484 TRF3761-F 1850 1984 925 992 462.5 496 TRF3761-G 1920 2059 960 1029.5 480 514.75 TRF3761-H 2028 2175 1014 1087.5 507 543.75 TRF3761-J 2140 2295 1070 1147.5 535 573.75 TRF3761-K 2225 2386 1112.5 1193 556.25 596.5 TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for high performance applications. The TRF3761 includes a low-noise, voltage-controlled oscillator (VCO) and an integer-N PLL. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2005 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TRF3761 integrates divide-by or options for a more flexible output frequency range. It is controlled through a 3-wire serial-programming-interface (SPI) interface. For power sensitive chip_en pin PACKAGE/ORDERING INFORMATION (1) SPECIFIED PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT MEDIA, PRODUCT TEMPERATURE LEAD DESIGNATOR (2) MARKINGS NUMBER QUANTITY RANGE TRF3761-AIRHAR Tape and Reel, 2500 TRF3761-A QFN-40 RHA C to C TRF3761-A TRF3761-AIRHAT Tape and Reel, 250 TRF3761-BIRHAR Tape and Reel, 2500 TRF3761-B QFN-40 RHA C to C TRF3761-B TRF3761-BIRHAT Tape and Reel, 250 TRF3761-CIRHAR Tape and Reel, 2500 TRF3761-C QFN-40 RHA C to C TRF3761-C TRF3761-CIRHAT Tape and Reel, 250 TRF3761-DIRHAR Tape and Reel, 2500 TRF3761-D QFN-40 RHA -40 C to C TRF3761-D TRF3761-DIRHAT Tape and Reel, 250 TRF3761-EIRHAR Tape and Reel, 2500 TRF3761-E QFN-40 RHA C to C TRF3761-E TRF3761-EIRHAT Tape and Reel, 250 TRF3761-FIRHAR Tape and Reel, 2500 TRF3761-F QFN-40 RHA C to C TRF3761-F TRF3761-FIRHAT Tape and Reel, 250 TRF3761-GIRHAR Tape and Reel, 2500 TRF3761-G QFN-40 RHA C to C TRF3761-G TRF3761-GIRHAT Tape and Reel, 250 TRF3761-HIRHAR Tape and Reel, 2500 TRF3761-H QFN-40 RHA C to C TRF3761-H TRF3761-HIRHAT Tape and Reel, 250 TRF3761-JIRHAR Tape and Reel, 2500 TRF3761-J QFN-40 RHA C to C TRF3761-J TRF3761-JIRHAT Tape and Reel, 250 TRF3761-KIRHAR Tape and Reel, 2500 TRF3761-K QFN-40 RHA C to C TRF3761-K TRF3761-KIRHAT Tape and Reel, 250 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (2) Thermal pad size: 177 177 mils. Submit Documentation Feedback

www.ti.com MUX_OUT CLOCKDATASTROBE REF_IN CHIP_EN PD_OUTBUFEXT_VCO_IN CPOUT34 VCTRL_IN VCO_OUTM VCO_OUTP Lock Det Serial Interface R□Div PFD Charge Pump N−Divider counter counter Prescaler div□p/p+1 FromSPI FromSPI FromSPI Power Down Div1/2/4 39 3 4 TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Functional Block Diagram Submit Documentation Feedback

www.ti.com GND A VDD_BIAS RBIAS1 GND VCTRL_IN A VDD_VCO A VDD_BUF A VDD_CAP ARRA Y GND A VDD PD_OUTBUF CHIP_EN CLOCK DA T A STROBE DGND DGND DVDD1 A VDD_PRES GND DVDD2 MUX_OUT REF_IN GND A VDD_REF A VDD_CP CPOUT GND A VDD GND GND GND VCO_OUTPVCO_OUTM A VDD_OUTBUF GND A VDD_VCOBUF EXT_VCO_IN RBIAS2 GND 383940 37 36 35 34 33 32 31 13121 1 14 15 16 17 18 19 20 TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 RHA PACKAGE (TOP VIEW) TERMINAL FUNCTIONS TERMINAL (1) I/O NO. Once configured in register this pin will control the output buffer. Logic level PD_OUTBUF I turns on the buffer and logic level turns off the buffer. This pin requires 4.5 to 5.25v applied for normal operation. Grounding this pin will CHIP_EN I disable the chip. CLOCK I Serial-programming-interface clock Serial-programming-interface data, used for programming the frequency and other DATA I/O features. STROBE I Serial-programming-interface strobe required to write the data to the chip DGND Digital ground Digital power supply, requires 4.5 to 5.25 Suggested decoupling, 0.1uF and DVDD1 10pF capacitors in parallel. Power supply for prescaler circuit, requires 4.5 to 5.25 Suggested decoupling, AVDD_PRES 0.1uF and 10pF capacitors in parallel. VCO output, can be used single ended matched to ohms or in conjuction with VCO_OUTP O VCO_OUTM (pin 14) with a balun. VCO output, can be used single ended matched to ohms or in conjunction with VCO_OUTM O VCO_OUTP (pin 13) with a balun. Power supply for output buffers, requires 4.5 to 5.25 Suggested decoupling, AVDD_OUTBUF 0.1uF and 10pF capacitors in parallel. Power supply for VCO buffers, requires 4.5 to 5.25 Suggested decoupling, AVDD_VCOBUF 0.1uF and 10pF capacitors in parallel. External VCO input to prescaler, If using an external VCO instead of the internal EXT_VCO_IN I VCO. External bias resistor for setting the internal reference current requires a 4.75K RBIAS2 I/O ohm resister to ground. (1) Power Supply=Vcc=(DVDD1, AVDD1, AVDD_PRES, AVDD_VCOBUF, AVDD, AVDD_CAPARRAY, AVDD_BUF, AVDD_VCO, AVDD_BIAS, AVDD_CP, AVDD_REF, DVDD2) Submit Documentation Feedback

www.ti.com THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TERMINAL FUNCTIONS (continued) TERMINAL (1) I/O NO. Analog power supply, requires 4.5 to 5.25 Suggested decoupling, 0.1uF and AVDD 10pF capacitors in parallel. Power supply for VCO core and buffer, requires 4.5 to 5.25 Suggested AVDD_CAPARRAY decoupling, 0.1uF and 10pF capacitors in parallel. Power supply for VCO core and buffer, requires 4.5 to 5.25 Suggested AVDD_BUF decoupling, 0.1uF and 10pF capacitors in parallel. Power supply for VCO core and buffer, requires 4.5 to 5.25 Suggested AVDD_VCO decoupling, 0.1uF and 10pF capacitors in parallel. VCTRL_IN I VCO control voltage, the output of the loop filter is applied to this pin. External bias resistor for setting charge pump reference current, requires 2.37K RBIAS1 I/O ohm resistor to ground. Power supply for band gap current bias, requires 4.5 to 5.25 Suggested AVDD_BIAS decoupling, 0.1uF and 10pF capacitors in parallel. 10, 11, 12, 16, 20, 22, GND Analog ground 27, 30, 31, 33, Power supply for FUSE cell, requires 4.5 to 5.25V. Suggested decoupling, 0.1uF, AVDD 1nF and 1pF capacitors in parallel. CPOUT O Charge pump output, connected to the input of loop filter. Analog power supply for charge pump, requires 4.5 to 5.25 Suggested AVDD_CP decoupling, 0.1uF and 10pF capacitors in parallel Power supply for REF_IN circuitry, requires 4.5 to 5.25 Suggested decoupling, AVDD_REF 0.1uF and 10pF capacitors in parallel. REF_IN I Reference signal input, reference oscillator input of 10MHz to 104MHz. Generally used for digital lock detect, can be used to verify locked condition by MUX_OUT O microcontroller, high locked, low unlocked. Power supply for the digital regulator, requires 4.5 to 5.25 Suggested DVDD2 decoupling, 0.1uF and 10pF capacitors in parallel. over operating free-air temperature range (unless otherwise noted) PARAMETER (1) TEST CONDITIONS MIN TYP MAX UNIT Soldered slug, no airflow C/W θ JA Thermal derating, junction-to-ambient Soldered slug, 200-LFM airflow 20.1 C/W Soldered slug, 400-LFM airflow 17.4 C/W (1) Determined using JEDEC standard JESD-51 with High K board Over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT Supply voltage range (2) 0.3 to 5.5 V Digital I/O voltage range 0.3 to V CC +0.3 V T J Operating virtual junction temperature range to 150 C T stg Storage temperature range to 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Submit Documentation Feedback

www.ti.com RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V CC Power supply voltage 4.5 5.25 V Power supply voltage ripple 940 µ V pp T A Operating free air temperature range C T J Operating virtual junction temperature range 150 C Supply voltage V CC 4.5V to 5.25V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Parameters Divide by output 130 mA I CC Total supply current T A C Divide by output 140 mA Divide by output 150 mA Reference Oscillator Parameters f ref Reference frequency 104 MHz Reference input sensitivity (REF_IN) 0.2 2.5 Vpp Parallel capacitance 6.52 pF Reference input impedance (REF_IN) Parallel resistance 3913 Ω PFD Charge Pump PFD frequency MHz Charge pump current CP_OUT SPI programmable 5.6 mA Digital Interface (PD_OUTBUF, CHIP_EN, CLOCK, DATA, STROBE) V IH High-level input voltage 2.5 V CC V V IL Low-level input voltage 0.8 V V OH High-level output voltage 0.8V CC V V OL Low-level output voltage 0.2V CC V Output Power Single ended dBm Differential dBm Supply voltage V CC 4.5V to 5.25V, T A to C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t (CLK) Clock period ns t su1 Setup time, data ns t h Hold time, data ns t w Pulse width, STROBE ns t su2 Setup time, STROBE ns Submit Documentation Feedback

www.ti.com tsu1 th t(CLK) tsu2 tw 1” Clock□Pike CLOCK DATA STROBE DB0□(LSB) Address□bit□1 DB1 Address□bit□2 DB2 Address□bit□3 DB29 Cmd□bit□30 DB30 Cmd□bit□31 DB31□(MSB) Cmd□bit□32 TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 The first bits, DB(3-0), of data are Address bits. The remaining bits, DB(31-4), are part of the command. The command is little endian or lower bits first. Figure Serial Programming Timing Diagram Submit Documentation Feedback

www.ti.com TRF3761-B ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 119.34 600kHz offset 139 VCO phase noise, f VCO 1651MHz, 1MHz offset -142.1 dBc/Hz Free running VCO direct output f O 1651MHz 6MHz offset 156.6 10MHz offset -158.6 100kHz offset -127.8 600kHz offset 146.5 VCO phase noise, f VCO 1651MHz, 1MHz offset 149 dBc/Hz Free running VCO divide-by-2 output f O 825.5 MHz 6MHz offset 156.2 10MHz offset 158.4 100kHz offset 127.3 600kHz offset -151.4 VCO phase noise, f VCO 1651MHz, 1MHz offset -153 dBc/Hz Free running VCO divide-by-4 output f O 412.75 MHz 6MHz offset 155.5 10MHz offset 155.9 1kHz offset 83.5 600kHz offset 138 VCO phase noise, f VCO 1651MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 1651MHz 1MHz offset 141.8 10MHz offset 158.2 RMS phase error 100Hz to 10MHz 0.85 Closed loop phase noise direct output (3) 1kHz offset 90.2 600kHz offset 146 VCO phase noise, f VCO 1651MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 825.5 MHz 1MHz offset 147.39 10MHz offset 158.25 RMS phase error 100Hz to 10MHz 0.53 Closed loop phase noise divide-by-2 output (3) 1kHz offset -95.7 600kHz offset 151 VCO phase noise, f VCO 1651MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 412.75 MHz 1MHz offset 154 10MHz offset 156 RMS phase error 100Hz to 10MHz 0.33 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-C ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 119.5 600kHz offset 138.8 VCO phase noise, f VCO 1723MHz, 1MHz offset -143.9 dBc/Hz Free running VCO direct output f O 1700MHz 6MHz offset 155.3 10MHz offset 157.5 100kHz offset 126 600kHz offset 145.2 VCO phase noise, f VCO 1723MHz, 1MHz offset 149.5 dBc/Hz Free running VCO divide-by-2 output f O 861.5 MHz 6MHz offset 157.2 10MHz offset 158 100kHz offset 133 600kHz offset -151 VCO phase noise, f VCO 1723MHz, 1MHz offset -153.8 dBc/Hz Free running VCO divide-by-4 output f O 430.75 MHz 6MHz offset 156 10MHz offset 156.5 1kHz offset 600kHz offset 138.3 VCO phase noise, f VCO 1723MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 1723MHz, 1MHz offset 142.6 10MHz offset 157.3 RMS phase error 100Hz to 10MHz 0.87 Closed loop phase noise direct output (3) 1kHz offset 90.1 600kHz offset 145 VCO phase noise, f VCO 1723MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 861.5 MHz 1MHz offset 148.6 10MHz offset 158 RMS phase error 100Hz to 10MHz 0.53 Closed loop phase noise divide-by-2 output (3) 1kHz offset 96.2 600kHz offset 151 VCO phase noise, f VCO 1723MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 430.75 MHz 1MHz offset 153 10MHz offset 156 RMS phase error 100Hz to 10MHz 0.33 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-D ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 118 600kHz offset 138.5 VCO phase noise, f VCO 1817MHz, 1MHz offset -144 dBc/Hz Free running VCO direct output f O 1817MHz 6MHz offset 156 10MHz offset 158 100kHz offset 124.8 600kHz offset 145.2 VCO phase noise, f VCO 1817MHz, 1MHz offset 148 dBc/Hz Free running VCO divide-by-2 output f O 908.5MHz 6MHz offset 157.8 10MHz offset 158.2 100kHz offset 132 600kHz offset -151 VCO phase noise, f VCO 1817MHz, 1MHz offset -154 dBc/Hz Free running VCO divide-by-4 output f O 454.25MHz 6MHz offset 157 10MHz offset 157.5 1kHz offset 600kHz offset 139 VCO phase noise, f VCO 1817MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (1) f O 1817MHz 1MHz offset 144 10MHz offset 159 RMS phase error 100Hz to 10MHz 0.85 Closed loop phase noise direct output (3) 1kHz offset VCO phase noise, 600kHz offset 146 f VCO 1817MHz, Closed loop phase noise divide-by-2 dBc/Hz f O 908.5MHz 1MHz offset 149 output (1) (2) (3) 10MHz offset 159 RMS phase error 100Hz to 10MHz 0.47 Closed loop phase noise divide-by-2 output (3) 1kHz offset VCO phase noise, 600kHz offset 151 f VCO 1817MHz, Closed loop phase noise divide-by-4 dBc/Hz f O 454.25MHz 1MHz offset 154 output (1) (2) (3) 10MHz offset 157 RMS phase error 100Hz to 10MHz 0.34 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-E ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 118 600kHz offset 138 VCO phase noise, f VCO 1869MHz, 1MHz offset 142 dBc/Hz Free running VCO direct output f O 1869MHz 6MHz offset 155 10MHz offset 157.3 100kHz offset 126 600kHz offset 144 VCO phase noise, f VCO 1869MHz, 1MHz offset 149 dBc/Hz Free running VCO divide-by-2 output f O 934.5MHz 6MHz offset 158 10MHz offset 158.2 100kHz offset 132 600kHz offset 150 VCO phase noise, f VCO 1869MHz, 1MHz offset 154 dBc/Hz Free running VCO divide-by-4 output f O 467.25MHz 6MHz offset -157 10MHz offset 157.3 1kHz offset 84.5 600kHz offset 140 VCO phase noise, f VCO 1869MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 1869MHz 1MHz offset 143.6 10MHz offset 157 RMS phase error 100Hz to 10MHz 0.9 Closed loop phase noise direct output (3) 1kHz offset 90.7 600kHz offset 144 VCO phase noise, f VCO 1869MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 934.5MHz 1MHz offset 148.5 10MHz offset 158 RMS phase error 100Hz to 10MHz 0.53 Closed loop phase noise divide-by-2 output (3) 1kHz offset 600kHz offset 150 VCO phase noise, f VCO 1869MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 467.25MHz 1MHz offset 154 10MHz offset 157 RMS phase error 100Hz to 10MHz 0.35 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-F ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset -116 600kHz offset -137 VCO phase noise, f VCO 1916MHz, 1MHz offset -141 dBc/Hz Free running VCO direct output f O 1916MHz 6MHz offset -155 10MHz offset -157 100kHz offset -113 600kHz offset -136 VCO phase noise, f VCO 1916MHz, 1MHz offset -147.5 dBc/Hz Free running VCO divide-by-2 output f O 958MHz 6MHz offset -155 10MHz offset -157.5 100kHz offset -128 600kHz offset -148 VCO phase noise, f VCO 1916MHz, 1MHz offset -150 dBc/Hz Free running VCO divide-by-4 output f O 479MHz 6MHz offset -155 10MHz offset -156 1kHz offset -82.5 600kHz offset -136.7 VCO phase noise, f VCO 1916MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 1916MHz 1MHz offset -142 10MHz offset -157 RMS phase error 100Hz to 10MHz 0.947 Closed loop phase noise direct output (3) 1kHz offset -88.6 600kHz offset -142.6 VCO phase noise, f VCO 1916MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 958MHz 1MHz offset -148.2 10MHz offset -158 RMS phase error 100Hz to 10MHz 0.477 Closed loop phase noise divide-by-2 output (3) 1kHz offset -95 600kHz offset -148 VCO phase noise, f VCO 1916MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 479MHz 1MHz offset -152 10MHz offset -156 RMS phase error 100Hz to 10MHz 0.231 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-G ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset -115 600kHz offset -136 VCO phase noise, f VCO 1989MHz, 1MHz offset -141.2 dBc/Hz Free running VCO direct output f O 1989MHz 6MHz offset -155.6 10MHz offset -159 100kHz offset -121.3 600kHz offset -142.4 VCO phase noise, f VCO 1989MHz, 1MHz offset -141.5 dBc/Hz Free running VCO divide-by-2 output f O 994.5MHz 6MHz offset -157.2 10MHz offset -158 100kHz offset -128 600kHz offset -148 VCO phase noise, f VCO 1989MHz, 1MHz offset -151 dBc/Hz Free running VCO divide-by-4 output f O 497.25MHz 6MHz offset -156.8 10MHz offset -157 1kHz offset -83 600kHz offset -136 VCO phase noise, f VCO 1989MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 1989MHz 1MHz offset -141 10MHz offset -159 RMS phase error 100Hz to 10MHz Closed loop phase noise direct output (3) 1kHz offset -88.7 600kHz offset -141.9 VCO phase noise, f VCO 1989MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 994.5MHz 1MHz offset -147.5 10MHz offset -158 RMS phase error 100Hz to 10MHz 0.509 Closed loop phase noise divide-by-2 output (3) 1kHz offset -95 600kHz offset -147.9 VCO phase noise, f VCO 1989MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 497.25MHz 1MHz offset -151.3 10MHz offset -156 RMS phase error 100Hz to 10MHz 0.252 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-H ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 116 600kHz offset 136 VCO phase noise, f VCO 2116MHz, 1MHz offset -142 dBc/Hz Free running VCO direct output f O 2116MHz 6MHz offset 154.2 10MHz offset 156 100kHz offset 123.3 600kHz offset 143 VCO phase noise, f VCO 2116MHz, 1MHz offset 147.6 dBc/Hz Free running VCO divide-by-2 output f O 1058 6MHz offset 157 10MHz offset 158.3 100kHz offset 129.4 600kHz offset -149.8 VCO phase noise, f VCO 2116MHz, 1MHz offset -152.7 dBc/Hz Free running VCO divide-by-4 output f O 529MHz 6MHz offset 157.7 10MHz offset 158 1kHz offset 600kHz offset 136 VCO phase noise, f VCO 2116MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 2116MHz 1MHz offset 141 10MHz offset 157 RMS phase error 100Hz to 10MHz 0.99 Closed loop phase noise direct output (3) 1kHz offset -89 600kHz offset 143 VCO phase noise, f VCO 2116MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 1058MHz 1MHz offset 148 10MHz offset 159 RMS phase error 100Hz to 10MHz 0.54 Closed loop phase noise divide-by-2 output (3) 1kHz offset 600kHz offset 149.5 VCO phase noise, f VCO 2116MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 529MHz 1MHz offset 153 10MHz offset 158 RMS phase error 100Hz to 10MHz 0.35 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRF3761-J ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Supply voltage V CC 5V, T A to C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset 116.7 600kHz offset 135.4 VCO phase noise, f VCO 2289MHz, 1MHz offset -141 dBc/Hz Free running VCO direct output f O 2289MHz 6MHz offset 153.8 10MHz offset 156.4 100kHz offset 123 600kHz offset 142 VCO phase noise, f VCO 2289MHz, 1MHz offset 147 dBc/Hz Free running VCO divide-by-2 output f O 1144.5 6MHz offset 156.2 10MHz offset 157.5 100kHz offset 129 600kHz offset -149 VCO phase noise, f VCO 2289MHz, 1MHz offset -153 dBc/Hz Free running VCO divide-by-4 output f O 572.25MHz 6MHz offset 157.5 10MHz offset 158 1kHz offset 600kHz offset 135 VCO phase noise, f VCO 2289MHz, dBc/Hz Closed loop phase noise direct output (1) (2) (3) f O 2289MHz 1MHz offset 140 10MHz offset 156 RMS phase error 100Hz to 10MHz 1.1 Closed loop phase noise direct output (3) 1kHz offset 600kHz offset -141 VCO phase noise, f VCO 2289MHz, dBc/Hz Closed loop phase noise divide-by-2 output (1) (2) (3) f O 1144.5MHz 1MHz offset 145.7 10MHz offset 158 RMS phase error 100Hz to 10MHz 0.59 Closed loop phase noise divide-by-2 output (3) 1kHz offset 600kHz offset 148 VCO phase noise, f VCO 2289MHz, dBc/Hz Closed loop phase noise divide-by-4 output (1) (2) (3) f O 572.25MHz 1MHz offset 152 10MHz offset 158.1 RMS phase error 100Hz to 10MHz 0.37 Closed loop phase noise divide-by-4 output (3) VCO gain, Kv VCO free running MHz/V Reference spur (2) dBc (1) See Application Circuit Figure (2) PFD 200kHz, Loop Filter BW 15kHz, Output frequency step 200kHz. (3) Reference oscillator RMS phase error 0.008250 RMS jitter 881.764 fs. Submit Documentation Feedback

www.ti.com TRP3761-B TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1651 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1651 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 825.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 825.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 412.75 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 412.75 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure Figure Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-B TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure Divide-By-2 Output: PFD Frequency Spurs Figure Divide-By-4 Output: PFD Frequency Spurs Figure 10. Submit Documentation Feedback

www.ti.com TRP3761-C TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1723 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1723 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 861.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 861.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 430.75 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 430.75 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 11. Figure 12. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 13. Figure 14. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 15. Figure 16. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-C TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 17. Divide-By-2 Output: PFD Frequency Spurs Figure 18. Divide-By-4 Output: PFD Frequency Spurs Figure 19. Submit Documentation Feedback

www.ti.com TRF3761-D TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1801 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1801 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 900.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 900.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 450.25 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 450.25 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 20. Figure 21. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 22. Figure 23. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 24. Figure 25. Submit Documentation Feedback

www.ti.com TRF3761-D TYPICAL CHARACTERISTICS (Continued) TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Direct Output: PFD Frequency Spurs Figure 26. Divide-By-2 Output: PFD Frequency Spur Figure 27. Divide-By-4 Output: PFD Frequency Spurs Figure 28. Submit Documentation Feedback

www.ti.com TRP3761-E TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1869 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1869 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 934.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 934.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 467.25 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 467.25 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 29. Figure 30. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 31. Figure 32. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 33. Figure 34. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-E TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 35. Divide-By-2 Output: PFD Frequency Spurs Figure 36. Divide-By-4 Output: PFD Frequency Spurs Figure 37. Submit Documentation Feedback

www.ti.com TRP3761-F TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1916 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1916 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 958 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 958 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 479 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 479 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 38. Figure 39. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 40. Figure 41. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 42. Figure 43. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-F TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 44. Divide-By-2 Output: PFD Frequency Spurs Figure 45. Divide-By-4 Output: PFD Frequency Spurs Figure 46. Submit Documentation Feedback

www.ti.com TRP3761-G TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1989 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1989 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 994.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 994.5 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 497.25 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 497.25 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 47. Figure 48. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 49. Figure 50. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 51. Figure 52. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-G TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 53. Divide-By-2 Output: PFD Frequency Spurs Figure 54. Divide-By-4 Output: PFD Frequency Spurs Figure 55. Submit Documentation Feedback

www.ti.com TRP3761-H TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 2100 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 2100 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1050 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1050 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 525 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 525 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 56. Figure 57. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 58. Figure 59. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 60. Figure 61. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-H TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 62. Divide-By-2 Output: PFD Frequency Spurs Figure 63. Divide-By-2 Output: PFD Frequency Spurs Divide-By-4 Output: PFD Frequency Spurs Figure 64. Submit Documentation Feedback

www.ti.com TRP3761-J TYPICAL CHARACTERISTICS f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 2216 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 2216 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 1108 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 1108 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 Phase Noise − dBc/Hz 1k 10k 100k 10M CL = 554 MHz f − Frequency − Hz −160 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 Phase Noise − dBc/Hz 1k 10k 100k 10M OL = 554 MHz TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 (See Figure Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 65. Figure 66. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 67. Figure 68. Closed Loop VCO Phase Noise Open Loop VCO Phase Noise Figure 69. Figure 70. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 TRP3761-J TYPICAL CHARACTERISTICS (See Figure (continued) Direct Output: PFD Frequency Spurs Figure 71. Divide-By-2 Output: PFD Frequency Spurs Figure 72. Divide-By-4 Output: PFD Frequency Spurs Figure 73. Submit Documentation Feedback

www.ti.com SERIAL INTERFACE PROGRAMMING REGISTERS DEFINITION tsu1 th t(CLK) tsu2 tw 1” Clock□Pike CLOCK DATA STROBE DB0□(LSB) Address□bit□1 DB1 Address□bit□2 DB2 Address□bit□3 DB29 Cmd□bit□30 DB30 Cmd□bit□31 DB31□(MSB) Cmd□bit□32 TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 The TRF3761 a 3-wire serial programming interface that controls an internal, 32-bit shift register. There are a total of signals that need to be applied: the CLOCK (pin 3), the serial DATA (pin and the STROBE (pin 5). The DATA (DB0-DB31) is loaded LSB first and is read on the rising edge of the CLOCK. The STROBE is asynchronous to the CLOCK and at its rising edge the data in the shift register gets loaded onto the selected internal register. The first four bits (DB0-DB3) is the address to select the available internal registers. The first bits, DB(3-0), of data are Address bits. The remaining bits, DB(31-4), are part of the command. The command is little endian or lower bits first. Figure 74. Serial Programming Timing Diagram Register Address REST Charge Pump Current Output Mode OUTBUF PD Reference Clock Divider (RDiv) Select EN_SEL BUFOUT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 Reference Clock Divider (RDiv) Anti Backlash PFD_P TRIS_C CP_TE Full Cal OL P ST Req DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 Figure 75. Register Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Table Register Device Setup REGISTER MAPPING Data Field DB31 FULL_CAL_REQ This is a read only bit, that indicates if a power-up cal is not required power-up cal is required power-up cal is required DB30 CP_TEST TI internal use only test enabled DB29 TRIS_CP High-impedance state charge pump CP high-impedance state output for normal operation DB28 PFD_POL Selects Polarity of PFD, should match negative polarity of VCO gain. If using external positive VCO with Negative gain then set to and vise versa. The internal VCO has positive gain so set to positve(1) DB27 ABPW1 ABPW <1,0 anti-backlash pulse width 1.5ns delay 0.9ns delay 3.8ns delay 2.7ns delay DB26 ABPW0 DB25 RDIV_13 14-bit reference clock divider RDIV <13,0 >:00...01: divide by RDIV <13,0 >:00...10: divide by DB24 RDIV_12 RDIV <13,0 >:00...11: divide by DB23 RDIV_11 DB22 RDIV_10 DB21 RDIV_9 DB20 RDIV_8 DB19 RDIV_7 DB18 RDIV_6 DB17 RDIV_5 DB16 RDIV_4 DB15 RDIV_3 DB14 RDIV_2 DB13 RDIV_1 DB12 RDIV_0 DB11 PD_BUFOUT If DB10 then it controls power down <DB10:11 of output buffer default; output buffer on output buffer off output buffer on/off controlled by OUTBUF_EN pin DB10 OUTBUF_EN_SEL Select Output Buffer enable control: internal through OUTBUF_EN pin DB9 OUT_MODE_1 OUTBUFMODE <1,0 Selection of RF divide by output buffer division ratio divide by DB8 OUT_MODE_0 divide by4 DB7 ICP2 ICP <2,0 select charge pump current mA step). From 1.4mA to 11.2mA DB6 ICP1 with Rbias set to 2.37Kohms. DB5 ICP0 DB4 RESET Registers reset high low for normal operation Address DB3 Address Bits <3,0 >=0000 for register Bits DB2 DB1 DB0 Submit Documentation Feedback

www.ti.com 1.2 V 22.168I = × (N + 1) ×CP R 8bias1 (1) /c40 /c413.3252 × N + 1I =CP Rbias1 (2) TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 OUT_MODE <1,0 TRF3761 has an optional divide by or output, which is selectable by programming bits <OUT_MODE_1, OUT_MODE_0 of register (see Table CP_TEST: By setting bit DB30 to it is possible to test the PFD up or down pulses. Internal TI use only. TRIS_CP: If bit DB29 is set to the charge pump output goes in tri-state. For normal operation, DB29 must be set to ABPW: Bits <DB27, DB26 are used to program the width of the anti-backlash pulses of the PFD. The user selects one of the following values: 0.9ns, 1.5ns, 2.7ns and 3.8ns. Backlash can occur when Fpfd becomes phase aligned with Fout of the VCO. This will cause a high impedance state on the phase detector and allow the output frequency to drift until the phase difference is enough to cause the phase detector to start sending signals to the charge pump to correct the difference. This slight variation will show up as a sub harmonic of the pfd signal in the passband of the loop filter which would result in a significant spur in the output of the VCO. It is recommended that the anti-backlash pulse be set to the 1.5ns which gives the best spur reduction for the TRF3761. PFD_POL: Bit DB28 of register sets the polarity of the PFD. A Low (0) selects a negative polarity, and a High (1) selects a positive polarity. By choosing the correct polarity, the TRF3761 will works with an external VCO having both positive and negative gain (Kv). For example if an external VCO has a Kv -23MHz/V then the PFD polarity would need to be negative, so DB28 would be set to a Low (0). When using the internal VCO with a Kv of 23MHz/V, the PDF_POL should be set to RDiv: A 14-bit word programs the RDiv for the reference signal, DB25 is the MSB and DB12 is the LSB. RDiv value is determined by dividing the reference frequency by the channel step size. For example if the reference frequency is 10MHz and the channel step size is 200KHz then RDiv would be 50. This sets up the Fpfd for the phase detector, in other words the reference frequency will be divided down by a factor of RDiv which in this example is 50. ICP: Bits <DB7, DB5 set the charge pump current. which reduces to: where N decimal value of [Reg1 DB <7:5 >]. The range is set by N and Rbias2. It is recommended that Icp be set to 7mA or <DB7, DB5 >=101. OUTBUF_EN_SEL: Output buffer on/off state is controlled through serial interface or an external pin. If bit DB10 is a (default state) the output buffers state is elected through bit DB11. If DB10 is a the buffers on/off are directly controlled by the OUTBU_EN pin. RESET: Setting bit DB4 to all registers are reset to default values. Refer to Register under the Application Information section. Register Address Reference Frequency (Integer Part) Refernece Frequency (Fractional Part) DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 Reference VCO Frequency in MHz START Frequency _CAL Continued DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 Figure 76. Register Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Table Register VCO Calibration REGISTER MAPPING Data Field DB31 START_CAL start calibration DB30 FOUT12 VCO frequency in MHz start calibration DB29 FOUT11 DB28 FOUT10 DB27 FOUT9 DB26 FOUT8 DB25 FOUT7 DB24 FOUT6 DB23 FOUT5 DB22 FOUT4 DB21 FOUT3 DB20 FOUT2 DB19 FOUT1 DB18 FOUT0 DB17 REF_FRAC6 Reference frequency in MHz (fractional 0000000 0.00MHz part) 0000001 0.01MHz DB16 REF_FRAC5 0000010 0.02MHz DB15 REF_FRAC4 1100011 0.99MHz DB14 REF_FRAC3 DB13 REF_FRAC2 DB12 REF_FRAC1 DB11 REF_FRAC0 DB10 REF6 Reference frequency in MHz (integer 0001010 =10MHz part) 0001011 =11MHz DB9 REF5 DB8 REF4 1101000 104MHz DB7 REF3 DB6 REF2 DB5 REF1 DB4 REF0 Address DB3 Address Bits <3,0 >=0001 for register Bits DB2 DB1 DB0 Reference Frequency: The bits <DB17, DB4 are used to specify the input reference frequency as multiples of 10kHz. Bits <DB10,DB4 specify the integer part of the reference frequency expressed in MHz. Bits <DB17,DB11 set the fraction part. Those values are then used during the calibration of the internal VCO. For example if using a 20MHz reference oscillator then bits <DB10,DB4 would be 0010100 and bits <DB17,DB11 would be 0000000. If the reference oscillator is 13.1MHz then bits <DB10,DB4 would be 0001101 and bits <DB17,DB11 would be 0001010. Start Calibration: A in DB31 starts the internal VCO calibration. When the calibration is complete, DB31 bit is internally reset to FOUT <12,0 This 13-bit word <DB30,DB18 specifies the VCO output frequency in MHz. If output frequency is not a integer multiple of MHz, this value must be approximated to the closest integer in MHz. Refer to Register under the Application Information section. Submit Documentation Feedback

www.ti.com TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Register Address Dual-Modulus A-Counter B-Counter Prescalar Mode DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 B-Counter Test MUX Lock RSRV RSRV PLL DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 Figure 77. Register Table Register A and B Counters REGISTER MAPPING Data Field DB31 Rsrv Reserved DB30 Rsrv Reserved DB29 START_LK Lock PLL to frequency active DB28 TEST_MUX_3 See Table for descriptions and 0001 LOCK_DETECT enabled settings. DB27 TEST_MUX_2 DB26 TEST_MUX_1 DB25 TEST_MUX_0 DB24 B_12 13-bit B counter DB23 B_11 DB22 B_10 DB21 B_9 DB20 B_8 DB19 B_7 DB18 B_6 DB17 B_5 DB16 B_4 DB15 B_3 DB14 B_2 DB13 B_1 DB12 B_0 DB11 A_5 6-bit A counter DB10 A_4 DB9 A_3 DB8 A_2 DB7 A_1 DB6 A_0 DB5 PRESC_MOD1 Dual-modulus prescaler mode <B5,B4 >:00 for <B5,B4 >:01 for DB4 PRESC_MOD0 <B5,B4 >:10 for <B5,B4 >:11 for Address DB3 Address Bits <3,0 >=0010 for register Bits DB2 DB1 DB0 Submit Documentation Feedback

www.ti.com FUNCTIONAL /c163 (3) /c40 /c41OUT PFD COUNTER COUNTER FN = = A + Prescalar × B numF (4) integer decimal num COUNTER integer COUNTER num decimal N = x y ,Prescalar B = x and A = Prescalar × y /c180 /c222 (5) TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 B <12,0 This 13-bit word <DB24,DB12 controls the value of the B counter of the N divider. The valid range is from to 8191. A <5,0 These bits <DB11,DB6 control the value of the A counter. The valid range is from to 63. PRESC_MOD <1,0 These bits <DB5,DB4 define the mode of the dual-modulus prescaler according to Table START_LK: TRF3761 does not load the serial interface registers values into the dividers registers until bit DB29 of register is set to After TRF3761 is locked to the new frequency, bit DB29 is internally reset to Refer to Register under the Application Information section. The TRF3761 integrates a high-performance, LC tank, voltage-controlled oscillator (VCO). For each of the devices of the TRF3761 family, the inductance and capacitance of the tank are optimized to yield the best phase-noise performance. The VCO output is fed externally and to the prescaler through a series of very low noise buffers, that greatly reduce the effect of load pulling onto the VCO. To extend the frequency coverage, the TRF3761 integrates a divide by and by with very low noise floor. The VCO signal is fed externally through a final open-collector differential-output buffer. This buffer is able to provide up to 3dBm (typical) of power into a 200 Ω differential resistive load. The open-collector structure gives the flexibility to choose different load configurations to meet different requirements. Prescaler Stage This stage divides down the VCO frequency before the A and B counters. This is a dual-modulus prescaler and the user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65. Prescaling is used due to the fact that the internal devices are limited in frequency operations of 200MHz. To determine the proper prescaler value, Fout which is the frequency out of the VCO is divided by the numerator of the prescaler if the answer is less than 200MHz then that is the prescalar to use, see Equation If the value is higher than 200MHz then repeat this procedure with the next prescalar numerator until a value of 200MHz or less is achieved. Refer to Synthesizing a Selected Frequency in the Section Register A and B Counter Stage The TRF3761 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A counter can take values from to 63, while the B counter can take values from to 8191. Also, the value for the B counter must be greater than or equal to the value for the A counter. The A and B counter with the prescaler stage create the VCO N-divider, see Equation and Equation Refer to Synthesizing a Selected Frequency in the Section Register Submit Documentation Feedback

www.ti.com Reference Divider REF_IN DIV PFD F R = F (6) /c40 /c41 REF_IN OUT DIV PFD COUNTER denom COUNTER F F = F × N = × A + Prescalar × BR (7) Phase Frequency Detector (PFD) and Charge Pump Stage Mux Out Div 1/2/4 Serial interface CHIP ENABLE Buffer Power Down External VCO IN TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 FUNCTIONAL (continued) TRF3761 includes a 14-bit RDiv, also known as RDiv, that allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD) this clock is also known as F PFD which is also the channel step size. Division ratios from to 16,383 are allowed. To determine RDiv use Equation The output frequency (Fout) is determined using Equation The outputs of the RDiv and the N counter are fed into the PFD stage, where the two signals are compared in frequency and phase. The TRF3761 pulse, whose width is controllable by the user through the serial programming interface. The PFD feeds the charge pump, whose output current pulses are fed into an external loop filter, which eventually produces the tuning voltage needed to control the integrated VCO to the desired frequency. MUX_OUT pin (39) provides a communication port to the microcontroller circuit. See Table in the Application Information section. Div 1/2/4 is the frequency divider for the TRF3761. This circuit can be programmed thru the serial programming interface (SPI) to divide the output frequency of the VCO by or This feature allows for the same loop filter design to be used for any of the divide by modes, and For example, if the VCO is running at 1499MHz to 1608MHz band then with the same exact circuit, run the output in the divide by mode 749.5MHz to 804MHz band or in the divide by mode 374.75MHz to 402MHz. The programming interface pins (3, to the chip are the serial programming interface (SPI). The interface requires a Clock, Data, and Strobe signal to operate. See timing diagram Figure This feature provides a way to shut down the chip when not needed in order to conserve power. CHIP_EN Pin (2) needs to be High for normal operation. PD_OUTBUFF pin (1), when enabled in software can provide a -40dB reduction in the output power while the VCO is locked and running. This feature is to help with isolation between RX and TX. EXT_VCO_IN pin (18) allows for the use of an external VCO to use the phase lock loop circuit in the TRF3761. This feature enables higher frequencies to be synthesized. Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION Initial Calibration and Frequency Setup at Power Up TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 The integrated high performance VCO requires an internal frequency calibration at power up. To perform such calibration the following procedure is recommended: Apply power supply to IC. Apply an input reference frequency to pin (38) and ensure the signal is stable. Turn on the TRF3761 using the chip enable pin (CHIP_EN, pin 2), by applying 5V. Register Setup the device through Register referencing Table The first bits of the 32-bit code sent to the chip are set DB <3:0 to 0000; which is the address of register Bit DB4, sets the soft reset for the chip. Soft reset allows for the registers to be reset without powering down the chip. If a soft reset is used then write to register twice: once with DB4 set high and once with DB4 set low. Typically, this bit is only used when the chip has been powered up and registers and have already been written to, so on power-up reset is not required, so DB4 is, by default, set low. DB <7: sets the charge pump current based on the resistor value on pin of the TRF3761 and the decimal value of Register DB <7:5 used in Equation This equation reduces to Equation where N decimal value of [Reg1 DB <7:5 >]. DB <9: sets the mode of the chip. The mode is how the device will or will not divide down the VCO s frequency. There are choices for the mode setting, divide by or per Table For example if 525MHz is required from the TRF3761 which has a main frequency of 1575MHz then the divide-by-4 mode is chosen by setting DB <9: to 10. DB <11:10 controls the output buffer. Both of these are set to by default, so the buffer is controlled internally. See Table for more information. DB <25:12 sets the RDiv value. Once the calculations under the Synthesizing a Selected Frequency section have been completed the value is known, based on the external reference oscillator. The value for R is entered into the DB <25:12 For example, if the reference oscillator is at a frequency REF_IN of 61.44MHz and a channel step size of 120kHz is required, which is also the frequency PFD the phase frequency detector will use to compare against the VCO's output frequency OUT then F REF_IN PFD 512, which is entered as follows: MSB: LSB 0001000000000. By default, DB <27:26 are set to for a 1.5ns delay on the anti-backlash pulse width. See Table for more information. DB is set to for positive by default. See Table for more information. DB is set to for normal operation. See Table for more information. DB is set to by default. See Table for more information. DB is set to by default. See Table for more information. Register Initiate calibration procedure by programming register as follows: Reference Table The first bits of the 32-bit code sent to the chip are set DB <3:0 to 0001; which is the address of register Use bits DB <17, of register to specify the input reference frequency in MHz. The value is split into an integer and a fraction part. For example: to insert a f REF of 30.72MHz, set: DB <10, (integer part) equal to 0011110 (30) and DB <17, (fraction part) equal to 1001000 (72). Submit Documentation Feedback

www.ti.com Re-Calibration After Power Up TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 APPLICATION INFORMATION (continued) Set DB <30:18 of register to the desired frequency. For example: 2200MHz would be 0100010011000 (2200). Set DB31of register to to start the calibration. The VCO calibration runs for 5ms. During the cal procedure it will not be possible to program register and At the end of the calibration, bit DB31 of register resets to Subsequent frequency programming requires DB31 to be set to Register Completion of the frequency set up, on initial calibration, cannot proceed until 5ms has elapsed, due to full calibration, then it will require that the A and B values, the prescalar ratio, be known. See Synthesizing a Selected Frequency section below for calculation. Reference Table The first bits of the 32-bit code sent to the chip are set DB <3:0 to 0010; which is the address of register DB <5:4 sets the prescalar ratio, 8/9, 16/17, 32/33, 64/65. For example: if are required, set the register bits DB <5:4 to 01. DB <11:6 sets the A value for the N counter. For example: if A is set DB <11:6 as follows: 000100 (4). DB <24:12 sets the B value for the N counter. For example: if B is 1156, set DB <24:12 as follows: 0010010000100 (4). DB <28:25 sets the TEST_MUX. This allows the user to check via the microcontroller the state of the TRF3761 by programming it to one of states. The most common state to use is the Digital lock Detect which places the pin in a logic high state with indicates the VCO is locked. Table MUX-Out Settings STATE DB <28:25 STATE DB <28:25 3-state o/p High impedance state on Pin 39) 0000 RDiv o/p (Shows R-value on Pin 39) 0100 Digital lock Detect (High when locked on Pin 39) 0001 Analog lock detect (High when locked on Pin 39) 0101 N-Divider o/p (Shows N-value on Pin 39) 0010 Read back read back register settings) 0110 DVDD (internal TI use) 0011 DGND (internal TI use) 0111 DB29 sets the START LOCK, which is set to on the initial frequency setup and then set to on additional frequency changes. Once all registers are written, the TRF3761 will lock to the desired frequency. In order to change the frequency once the initial calibration is complete, only registers and need to be reprogrammed. No calibration is required. Assuming the TRF3761 is powered up and operational, a VCO calibration is also possible without powering down the IC. To perform such calibration the following procedure is recommended: Set bit DB4 (RESET) of register to This performs a software reset and clears all registers of VCO calibration data. Once the reset command is issued then DB4 of register will need to be set to Repeat the Initial Calibration and Frequency setup at Power up section, skipping the power up section and performing the register programming sequence. Submit Documentation Feedback

www.ti.com Synthesizing a Selected Frequency Application Schematic TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 The TRF3761 is an integer-N PLL synthesizer, and because of its flexibility (14-bit RDiv, 6-bit A counter, 13-bit B counter, and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. If synthesizing a 900MHz local oscillator, with spacing capability (minimum frequency increment) of 200kHz, as in a typical GSM application, the choice of the external reference oscillator is beyond the scope of this section. However, if a 10MHz reference is selected, the settings are calculated to yield the desired output frequency and channel spacing. There is more than one solution to a specific set of conditions, so below is one way of achieving the desired result. First, select the appropriate RDiv counter value. Since a channel spacing of 200kHz is desired, the F PFD is set to 200kHz. Calculate the RDiv value through: RDiv F REFIN PFD 10MHz/ 200kHz 50. Assume a prescaler value of is selected. This is a valid choice, since the prescaler output is well within the 200MHz limit (900MHz 112.5MHz). Select the appropriate A and B counter values. RFOUT F PFD N REFIN RDiv) counter Prescalar numerator B counter). Therefore, the following equation must be solved: 900MHz 200kHz x B). There are many solutions to this single equation with two unknowns; there are some basic constraints on the solution, since B 8191, and also B So, if A solving the equation yields B 562. One complete solution would be to choose: RDiv 50, A counter Bcounter 562 and Prescalar resulting in the desired N counter value 4500. This is how the A counter, B counter and prescalar make up the N counter. When this procedure is complete the values for the N counter and the prescalar ratio should be known. Registers and need to be set up for operation of the chip. See Table and Table for this procedure. Register bits <DB30:DB18 12:0 set the output frequency of the device along with register See the N-Divider section under the Functional a typical application schematic for the TRF3761. In this example, the output signal is taken differential using the resistive pull-up resistors of the final output buffer. A single-ended and tuned load configuration is also available. The loop filter components: 303pF, 8.87k Ω 1650pF, 3.4k Ω 330pF are typical ones used for the plots shown above. Those values can be optimized differently according to the requirements of the different applications. Submit Documentation Feedback

www.ti.com TRF3761 (TOP VIEW) GND AVDD_BIAS RBIAS1 GND VCTRL_IN AVDD_VCO AVDD_BUF AVDD_CAPARRAY GND AVDD (See□Note A) PD_OUTBUF CHIP_EN CLOCK DATA STROBE DGND DGND DVDD1 AVDD_PRES GND DVDD2MUX_OUTREF_INGNDAVDD_REFAVDD_CPCPOUTGNDAVDDGND GNDGND VCO_OUTPVCO_OUTM AVDD_OUTBUF GND AVDD_VCOBUF EXT_VCO_IN RBIAS2 GND 383940 37 36 35 34 33 32 31 131211 14 15 16 17 18 19 20 To□Microcontroller To□Microcontroller REF 1000□pF 2.37□kΩ 10□pF 10□pF 120 Ω 120 Ω VDDVDD LOAD 1000□pF 4.75□kΩ Loop Filter Design TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Refer to the Application Information section Loop Filter Design. Figure 78. TRF3761 Application Schematic Numerous methodologies and design techniques exist for designing optimized loop filters for particular applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can be implemented, including both passive and active. In this section, a third-order passive filter is used. For this example, assume these several design parameters. The internal VCO has a value of 23MHz/V, meaning that in the linear region, changing the tuning voltage of the VCO by induces a change of the output frequency of Submit Documentation Feedback

www.ti.com OUTF = F F min max (8) OUTFN = F com (9) = 2πFc c/c118 (10) 1 - tancosT1 T31 +c T1 /c230 /c246 /c102/c231 /c247/c102/c232 /c248/c61 /c230 /c246/c118 /c231 /c247 /c232 /c248 (11) T3T3 = T 1T1 /c230 /c246 /c231 /c247 /c232 /c248 (12) /c40 /c41 1T2 = 2 T1+T3c/c118 (13) /c40 /c41 /c40 /c41 /c40 /c41 VCO 221 + T2K KT1 cC1 = × x 2T2 2 2 2 2N 1 + T1 1 + T3c c c /c233 /c249 /c234 /c250 /c118/c102 /c234 /c250 /c234 /c250/c118 /c118 /c118/c234 /c250 /c235 /c251 (14) T2 C1C2 = C1 - 1 , C3 =T1 10 /c230 /c246 /c231 /c247 /c232 /c248 (15) T 2 T 3R1 = , R2 =C2 C3 (16) TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 about 23MHz. It is known that N 4500 and Fpfd 200kHz from our previous example. It is assumed that current setting in register <DB7:DB5 is set to 100 and sets a maximum current of 5.6mA.TI recommends an Icp of 5.6mA, which give the best spur performance, but can be changed for different application. In addition, the bandwidth of the loop filter must be determined. This is a critical consideration as it affects the lock time of the system. Assuming an approximate bandwidth of around 20kHz is required and that for stability a phase margin of about degrees is desired, the following values for the components of the loop filter can be derived. There is almost an infinite number of solutions to the problem of designing the loop filter and the designer is called to make tradeoff decisions for each application. Texas Instruments has provided a loopfilter program in the product folder for the TRF3761. Some terms are interchangeable and are described and equated here: F com F PDF which identify the comparing frequency or phase detector frequency which is also equal to the system channel step size. F OUT must be a multiple of F com F min is the lower frequency of the design band. F max is the upper frequency of the design band. F ref is the reference frequency for the PLL. Fref must be a multiple of F com K vco Kv expressed in MHz per Volt (MHz/V) which is the gain of the VCO. The TRF3761 internal VCO has a Kv 23MHz/V. I cp is the charge pump current. The TRF3761 is typically set to 5.6mA. F c is the loop filter bandwidth which should be no more than F com φ is phase margin in degrees. Values should be between and 70. The higher the phase margin the better the stability of the PLL but the slower the lock time. degrees is a good tradeoff. T3/T1 in percent is the percentage of the poles in the loop filter. Usually set to 45%. The higher the value (closer to 100%) the more the spurs are attenuated, but peaking occurs in the pass band of the loop filter. Submit Documentation Feedback

www.ti.com C1□=□303pF R1□=□8.87k R2□=□3.4k C2□=□1650pF C3□=□330pF /c87 /c87 Locktime□freq□~□250 S/c109 Frequency□jump□from 1046MHz□to□1085MHz: Loop□filter□components: Loop Filter Design Example OUTF = F F = 2130MHz (rounded up)min max (17) OUTFN = = 5325F com (18) 3= 2πF = 125.66 x 10c c/c118 (19) 1 - tancos -6T = = 2.3 x 101 T31 +c T1 /c230 /c246 /c102/c231 /c247/c102/c232 /c248 /c230 /c246/c118 /c231 /c247 /c232 /c248 (20) T -63T = T = 1 x 103 1 T1 /c230 /c246 /c231 /c247 /c232 /c248 (21) TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Figure 79. Frequency Locktime Given these parameters which were used for the lock time plot Figure F min 2085 MHz F max 2175 MHz F com 400 KHz Icp 4.2mA Kvco MHz Fc KHz Phase Margin degrees T3/T1 45% Calculate F OUT of design Next calculate N Then calculate ω c Now calculate T1-T3 to give the RC time constants. Use to find Submit Documentation Feedback

www.ti.com /c40 /c41 1 -6T = = 19.2 x 102 2 T + T1 3C/c118 (22) /c40 /c41 /c40 /c41 /c40 /c41 2 2 2 2 2 VCO 1 + TK KT c 21C1 = × × = 338.75pFT2 N 1 + T 1 + Tc c c1 3 /c233 /c249 /c234 /c250 /c118/c102 /c234 /c250 /c234 /c250/c118 /c118 /c118/c234 /c250 /c235 /c251 (23) T2C2 = C1 - 1 = 2524.14pFT1 /c230 /c246 /c231 /c247 /c232 /c248 (24) C1C3 = = 33.87pF10 (25) T2R2 = = 7.61kΩC2 (26) T3R3 = = 30.2kΩC3 (27) Layout/PCB Considerations TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 Then use and to find Now C1, C2, C3, R1, and are calculated using T1, T2, and T3. Now using and T2, find R2. Use and to find x can be scaled using T3, so if 330pF, then 3.03 k Ω 3.4 k Ω in the loop filter. x can be scaled using T2. Scaling these values helps to improve the lock time. The actual values used in the lock time plot were optimized for lock time as well as using real valued components. The values in figure were taken from the current EVM schematic. This section of the design of the complete PLL is of paramount importance in achieving the desired performance. Wherever possible, a multi-layer PCB board should be used, with at least one dedicated ground plane. A dedicated power plane (split between the supplies if necessary) is also recommended. The impedance of all RF traces (the VCO output and feedback into the PLL) should be controlled to Ω All small value (10pF and 0.1uF) decoupling capacitors should be placed as close to the device pins as possible. It is also recommended that both top and bottom layers of the circuit board be flooded with ground, with plenty of ground vias dispersed as appropriate. Because the digital lines are not in use during normal operation of the device and are only used to program the device on start up and during frequency changes the analog grounds (GND) and digital grounds (DGND) are tied to the same ground plain. The most sensitive part of any PLL is the section between the charge pump output and the input to the VCO. This includes the loop filter components, and the corresponding traces. The charge pump is a precision element of the PLL and any extra leakage on its path can adversely affect performance. Extra care should be given to ensure that parasitics are minimized in the charge pump output, and that the trace runs are short and optimized. Similarly, it is also recommend that extra care is taken in ensuring that any flux residue is thoroughly cleaned and moisture baked out of the PCB. From an EMI perspective, and since the synthesizer is typically a small portion of a bigger, complex circuit board, shielding is recommended to minimize EMI effects. Submit Documentation Feedback

www.ti.com BOTTOM GND BOTTOM GND De-coupling Capacitor’s on□back□side of□board De-coupling Capacitor’s on□top□side of□board TOP GND Via□to□bottom□ground MUX_OUT BOTTOM GND BOTTOM GND De-coupling Capacitor’s on□back□side of□board De-coupling Capacitor’s on□top□side of□board TOP GND Via□to□bottom□ground BOTTOM GND BOTTOM GND De-coupling Capacitor’s on□back□side of□board De-coupling Capacitor’s on□top□side of□board TOP GND Via□to□bottom□ground BOTTOM GND BOTTOM GND De-coupling Capacitor’s on□back□side of□board De-coupling Capacitor’s on□top□side of□board TOP GND Via□to□bottom□ground MUX_OUT Application Example for a High Performance RF Transmit Signal Chain TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 See the Application Information section for Loop Filter Design procedures. Figure 80. TRF3761 Layout Much in the same way as described above, the TRF3761 is an ideal synthesizer to use in implementing a complete high performance RF transmitter chain such as the TSW3000 and TSW3003 Demonstration kits. Using a complete suite of high performance Texas Instruments components, a state-of-the-art transmitter can be implemented featuring excellent performance. Texas Instruments offers ideal solutions for the digital-to-analog conversion portion of transmitter as well as the analog and RF components needed to complete the transmitter. The baseband digital data is converted to I and Q signals through the dual DAC5687, which a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates a digital modulator, independent differential offset control, and I/Q amplitude control. The device is typically used in baseband mode or in low IF mode in conjunction with an analog quadrature modulator. The DAC5687, after filtering, feeds a TRF3703, which is a direct, upconversion IQ modulator. This device accepts a differential input voltage quadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the LO drive frequency. The LO Submit Documentation Feedback

www.ti.com 90° LP A TX ANT Diplexer RX DAC A/D I/Q Demod I/Q Modulator LNA Low□Noise Amplifier□and RF-to-LO□Down□Converter LO-to-Digital□Conveter Gain□and□Power AmplifierDigital-to-RF□Up□Converter DAC5687 CLK1 CLK2 CDCM7005 Clock□Generator VCXO Ref□Osc TRF3761 PLL LO□Generator TRF3703 I/Q Modulator RF□Out TRF3761 SLWS181F OCTOBER 2005 REVISED JANUARY 2007 drive input of the IQ modulator is generated by the TRF3761. The TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for wireless infrastructure applications. The TRF3761 includes an integrated VCO and integer-N PLL. Different members of the TRF3761 family can be chosen for application specific VCO frequency ranges. In addition, the CDC7005 clocking solution can be used to clock the DAC and other portions of the transmitter. A block diagram of the proposed architecture is shown in Figure and Figure For more details, contact Texas Instruments directly. Figure 81. Transmit Chain Block Diagram Figure 82. Transmit Chain Block Diagram Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TRF3761-AIRHAR PREVIEW QFN RHA 40 2500 TBD Call TI Call TI TRF3761-AIRHAT PREVIEW QFN RHA 40 250 TBD Call TI Call TI TRF3761-BIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-BIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-BIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-BIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-CIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-CIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-CIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-CIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-DIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-DIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-DIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-DIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-EIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-EIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-EIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-EIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-FIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-FIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-FIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-FIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-GIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-GIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-GIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-GIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 Addendum-Page 1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) no Sb/Br) TRF3761-HIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-HIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-HIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-HIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-JIRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-JIRHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-JIRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-JIRHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TRF3761-KIRHAR PREVIEW QFN RHA 40 2500 TBD Call TI Call TI TRF3761-KIRHAT PREVIEW QFN RHA 40 250 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TRF3761-BIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-BIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-CIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-CIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-DIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-DIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-EIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-EIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-FIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-FIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-GIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-GIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-HIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-HIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-JIRHAR RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P TRF3761-JIRHAT RHA 40 TAI 330 16 6.3 6.3 1.5 12 16 PKGORN T2TR-MS P PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 2

TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TRF3761-BIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-BIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-CIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-CIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-DIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-DIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-EIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-EIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-FIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-FIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-GIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-GIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-HIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-HIRHAT RHA 40 TAI 342.9 336.6 28.58 TRF3761-JIRHAR RHA 40 TAI 342.9 336.6 28.58 TRF3761-JIRHAT RHA 40 TAI 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 4

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