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SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 HIGH-PERFORMANCE INTEGER-N PLL FREQUENCY SYNTHESIZER

FEATURES

/C0068Single Device Covers Frequencies Up to

2.4 GHz

/C0068Dual Supply Range: 3 V − 3.6 V and 4.5 V − 5.5 V /C0068Separate Charge Pump Supply (V CP) Up to 8 V /C0068Simple 3-Wire Serial Interface Allows for Fully Programmable: − A, B, and R Counters − Dual Modulus Prescaler [8/9, 16/17, 32/33, and 64/65] − Charge Pump Current /C0068Lock Detect Output (Digital and Analog) /C0068Versatile Hardware and Software Power Down /C0068Packaged in a 16-Pin TSSOP Thin Quad FlatPack and a 20-Pin 4 x 4 mm QFN Package

APPLICATIONS

/C0068Wireless Infrastructure − GSM, IS136, EDGE/UWC−136 − IS95, UMTS, CDMA2000 /C0068Portable Wireless Communications /C0068Wireless LAN /C0068Wireless Transceivers /C0068Communication Test Equipment

DESCRIPTION

The TRF3750 frequency synthesizer is ideal for designing the local os cillator portion of wireless transceivers by providing complete programmability and ultra-low phase noise. The device features a user-selectable dual- modulus prescaler, a 14-bit reference (R) divider, a 6-bit A, and a 13-bit B counter. The R divider allows the user to select the frequency of choice for the phase-frequency detector (PFD) circuit, and with the use of the counters implement an N divider of value N = A + P x B. With an extended charge-pump supply (V CP) of up to 8 V, a wide variety of external VCOs can be used to complete the phase-locked loop. Ultra-low phase noise and reference spur performance make the TRF3750 ideal for generating the local oscillator in the most demanding wireless applications. RSET CPOUT CPGND AGND RFIN RFIN AVDD REFIN VCP DVDD MUXOUT LE DATA CLOCK CE DGND PW PACKAGE (TOP VIEW) MUXOUT RGP PACKAGE (TOP VIEW) CPGND CPOUT RSET VCP DVDD DVDD REFIN DGND AVDD 6 7 891 0 20 19 18 17 16 AVDD DGND LE DATA CLOCK CERFIN RFIN AGND AGND PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com Copyright  2004, Texas Instruments Incorporated

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM FOR TSSOP PACKAGE 24-Bit Data Shift Register MUXOUT REFIN RFIN DVDD AVDD VCP CLOCK 11 DATA 12 LE 13 CE 10 Power Down Function Latch RFIN 5 Prescaler P/P+1 N Divider 6-Bit A Counter LD Current Setting 2 N Counter Latch22 R Counter Latch 14-Bit R Counter 136 MUX 14 PFD Lock Detect 13-Bit B Counter LD Charge Pump RSET1 CPOUT2 Current Setting 1 Bias AGND DGND CPGND DVDD Initialization Latch 22

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com

ORDERING INFORMATION

TRF3750IPW TSSOP-16 PW –40°C to 85°C TRF3750 TRF3750IPW Tube 90 TRF3750IPWR TSSOP-16 PW –40°C to 85°C TRF3750 TRF3750IPWR Reel 2000 TRF3750IRGP QFN-20 RGP –40°C to 85°C TRF3750 TRF3750IRGP Tube 91 TRF3750IRGPR QFN-20 RGP –40°C to 85°C TRF3750 TRF3750IRGPR Reel 1000 PIN ASSIGNMENTS TERMINAL NAME QFN(1) NO. TSSOP NO. TYPE DESCRIPTION RSET 19 1 O The user needs to place an external resistor (RSET) from this pin to ground to control the maximum charge pump current. This node’s output voltage is typically around 1 V and the relationship between ICPOUTmax and RSET is: ICPOUTmax /C004323.5 RSET A 4.7-kΩ resistor placed at this pin to ground would hence provide a maximum charge pump output current of approximately 5 mA. CPOUT 20 2 O Charge pump output. This node provides the charge pump current that ultimately controls the external VCO. CPGND 1 3 I Charge pump ground AGND 23 4 I Analog ground RFIN 4 5 I Complementary input to the prescaler. For single-ended applications, bypass with a small capacitor to ground (typically 100 pF). RFIN 5 6 I Input to the prescaler. To complete the PLL, this signal must come from the output of the external VCO. This value should be the same as the DVDD. Appropriate decoupling is necessary for optimal performance. REFIN 8 8 I Reference frequency input. This externally provided reference gets divided by the selectable R divider, and is used to synthesize the desired output frequency. Typically this input is an ac-coupled sinusoid; however, a TTL or CMOS signal can also be used. DGND 9, 10 9 I Digital ground CE 11 10 I Chip enable. Setting this pin low puts the device into power down; setting it high activates the charge pump if the software controlled power down is also disabled. CLOCK 12 11 I Serial clock input. This is the input that is used to clock the serial data into the 24-bit shift register of the device. The data is read at the rising edge of this clock. DATA 13 12 I Serial data input. This is the data stream that contains the data to be loaded into the shift register. The data is loaded MSB first. LE 14 13 I Load enable. When this asynchronous signal is asserted high, the data existing in the shift register get loaded onto the selected latch. MUXOUT 15 14 O This user-selectable output can be controlled to provide the digital or analog lock detect signals, the divide by N RF signal or the divide by R reference. The output can also be 3-stated. value should be the same as the AVDD. Appropriate decoupling is necessary for optimal performance. VCP 18 16 I Charge pump supply. This supply must be at least 1 V greater than the AVDD and DVDD and can be as high as 8 V, accommodating a large range of possible VCOs. (1) The thermal pad on the bottom of the QFN package may be tied to ground, but is not required to meet specified performance.

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT AVDD −0.3 V to 6.5 V Supply voltage range(2) AVDD to DVDD −0.3 V to 0.3 VSupply voltage range VCP to AGND −0.3 V to 9 V Digital I/O voltage to DGND (DGND = 0 V) −0.3 V to 6.5 V Reference signal input REFIN to DGND −0.3 V to DVDD + 0.3 V RF prescaler input RFIN, RFIN to AGND −0.3 V to 6.5 V Continuous power dissipation See Dissipation Rating Table Storage temperature, TStg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR(1) ABOVE TA = 25°C TA = 85°C POWER RATING 16-pin TSSOP 2780 mW 22.2 mW//C0095C 1440 mW 20-pin QFN 2780 mW 29 mW//C0095C 1440 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no airflow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT AVDD = DVDD, 3.3 V range 3 3.3 3.6 V Supply voltage AVDD = DVDD, 5 V range 4.5 5 5.5 VSupply voltage VCP (AVDD, DVDD) + 1 8 V High−level input voltage, VIH LE DATA CLK CE 0.8 x DVDD V Low−level input voltage, VIL LE, DATA, CLK, CE 0.2 x DVDD V High−level output voltage, VOH MUXOUT DVDD − 0.4 V Low−level output voltage, VOL MUXOUT 0.4 V Operating free-air temperature, TA −40 85 °C

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com

ELECTRICAL CHARACTERISTICS

Conditions: (AVDD = DVDD = 3.3 V or 5 V, AVDD + 1≤ VCP ≤ 8 V, RSET = 4.7 kΩ, TA = −40°C to 85°C, REFIN = 10 MHz at +5 dBm) (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I Supply current AVDD = 3.3 V 10 mAIAVDD Supply current AVDD = 5 V 13 mA I Supply current DVDD = 3.3 V 3 mAIDVDD Supply current DVDD = 5 V 3.5 mA IVCP Supply current VCP = 7 V 7.5 mA RFIN input frequency (RF input) 2400 MHz RFIN input power level −15 +5 dBm RF prescaler output frequency (1) 200 MHz REFIN input frequency (reference input) (1) 4 350 MHz REFIN input power level sensitivity −10 dBm REFIN input capacitance 5 pF PFD maximum frequency (1) 60 MHz ICPOUTmax Charge pump max source current 5 mA ICPOUTmin Charge pump max sink current −5 mA VTUNE Output tuning voltage (2) Measured at the output of the external loop filter, in locked condition 1 VCP−1.1 V (1) Assured by design. (2) VTUNE range shown is for optimal spurious performance; the device can function beyond these limits.

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com Conditions (unless otherwise stated): AVDD = DVDD = 3.3 V or 5 V, VCP = 7 V; RSET = 4.7 kΩ, TA = 27°C, REFIN = 10 MHz at 6.5 dBm Referenced to 50 Ω, ICPOUTmax = 5 mA, Power Down: Normal Operation; Timer Counter Control: Not used; MUXOUT Control: 3-state; Fast Lock Mode: Disabled, PFD Polarity: Positive, Anti-backlash Pulse width: 1.5 ns, Resync/Delay: Normal (Delay=0, Resync=0), Counter Operation: Normal, Charge Pump Output: Normal, Lock Detect Precision: 5 cycles PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Phase noise 110 MHz) PFD = 200 kHz, Loop Loop BW = 20 kHz, N 550 Phase noise measured at 1 kHz offset −106 dBc/Hz Reference spurs 110 MHz N =550, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −110 dBc Phase noise 300 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 1500 Phase noise measured at 1 kHz −99 dBc/Hz Reference spurs 300 MHz N =1500, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −110 dBc Phase noise 540 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 2700 Phase noise measured at 1 kHz −94 dBc/Hz Reference spurs 540 MHz N = 2700, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −90 dBc Phase noise 836 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 4180 Phase noise measured at 1 kHz −91 dBc/Hz Reference spurs 836 MHz N = 4180, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −100 dBc Phase noise 900 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 4500 Phase noise measured at 1 kHz −91 dBc/Hz Phase noise 900 MHz, over temperature and supply N = 4500, Phase noise measured at 1−kHz offset spurs measured at ±PFD, ±2 x PFD −90 dBc/Hz Reference spurs 900 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 4500 Phase noise measured at 1 kHz −100 dBc Reference spurs 900 MHz, over temperature and supply N = 4500, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −100 dBc Phase noise 1750 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N = 8750 −84 dBc/Hz Reference spurs 1750 MHz N = 8750 Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −96 dBc Phase noise 1960 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 9800 Phase noise measured at 1 kHz −84 dBc/Hz Phase noise 1960 MHz, over temperature and supply N = 9800, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −82 dBc/Hz Reference spurs 1960 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 9800 Phase noise measured at 1 kHz −90 dBc Reference spurs 1960 MHz, over temperature and supply N = 9800, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −90 dBc Phase noise 2200 MHz PFD = 200 kHz, Loop Loop BW = 20 kHz, N 11000 Phase noise measured at 1 kHz −83 dBc/Hz Reference spurs 2200 MHz N = 11000, Phase noise measured at 1-kHz offset spurs measured at ±PFD, ±2 x PFD −90 dBc

Figure 1. Serial Programming Timing Diagram

Figure 18. Reference Spurs Figure 19. Integrated Phase Noise

1960 MHz, AVDD = DVDD = 5 V

900 MHz, AVDD = DVDD = 5 V

Table 1. S11 Data for RFIN Buffer

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com Phase Frequency Detector (PFD) and Charge Pump Stage The outputs of the R divider and the N counter (please see pulse swallow section) are fed into the PFD stage, where the two signals are compared in frequency and phase. The TRF3750 features an anti-backlash pulse, whose width is controllable by the user, in order to optimize phase and spurious performance. The PFD feeds the charge pump, which is the final output of the TRF3750. The charge pump output pulses need to be fed into an external loop filter, which eventually produces the tuning voltage needed to control the external VCO to the desired frequency. Pulse Swallow/Frequency Synthesis The different stages of the TRF3750 enable the user to synthesize a large range of frequencies at the output of a complete PLL. For a given reference frequency (f REFIN), the user’s choice of the R divider yields the PFD frequency (fPFD), which is the step by which the resultant output frequency can be incremented or decremented. The choice of prescaler, and A and B counters yields the output frequency at the external VCO (RFOUT) as shown below. RFOUT = fPFD x N = (fREFIN / R) x (A + P x B) MUXOUT Stage The TRF3750 features a multiplexer that allows programmable access to several signals. Table 5 and Table 6 show the truth tables. Some of the different signals available are detailed below. Digital Lock Detect This is an active high digital output that indicates when the device has achieved lock. The user can choose between two precision settings for the lock detection, through the reference counter latch. A 0 on the lock detect precision means that the digital lock detect output goes high only if three contiguous cycles of the PFD have an error of less than 15 ns. A 1 would require five contiguous cycles (a more stringent condition). Any error of greater than 25 ns, even on one cycle, would produce a 0 in the digital lock detect signal, indicating loss of lock. Analog Lock Detect Selecting the analog lock detect option at the output of the output multiplexer requires an external pull-up resistor (≈10 kΩ) to be placed on the output (MUXOUT, pin 14). Fastlock Mode The TRF3750 features two Fastlock Modes, which the user may select depending on the particular application. There are two separate charge pump current settings (1 and 2) that can be programmed, and the Fastlock Modes, when activated, enable the device to quickly switch from current setting 1 to current setting 2. The two Fastlock Modes (1 and 2) differ in the way the device reverts back to current setting 1. In normal (steady-state) operation, current setting 1 is used. For transient situations such as frequency jumps, current setting 2 can be used. Fastlock Mode 1 As soon as Fastlock Mode 1 is entered, the charge pump current is switched to the preprogrammed setting 2 and stays there until the charge pump gain programming bit is set to 0 in the N counter latch. This way, the user has immediate software control of the transition between charge pump setting 1 and 2. Fastlock Mode 2 As soon as Fastlock Mode 2 is entered, the charge pump current is switched to the preprogrammed setting 2 and stays there until the timer counter has expired. The timer counter is programmed by the user and counts how many PFD cycles the device spends in current setting 2 in Fastlock Mode 2. The number of timer cycles can be set in increments of four cycles in the range of 3 to 63. When the counter has expired, the device returns to normal operation (fastlock disabled and charge pump current setting 1). This way no extra programming is needed in order for the device to exit fastlock. 3-Wire Serial Programming The TRF3750 features an industry-standard 3-wire serial interface that controls an internal 24-bit shift register. There are a total of 3 signals that need to be applied: the clock (CLK, pin 11), the serial data (DATA, pin 12) and the load enable (LE, pin13). The DATA (DB0−DB23) is loaded MSB first and is read on the rising edge of the CLK. The LE signal is asynchronous to the clock and at its rising edge the DATA gets loaded onto the

the appropriate latch is shown in Table 2. Table 2. Latch Selection Truth Table

Table 3. R Counter Latch

  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • •• Set to 00 AntiBacklash Pulse Width 3 ns ABP1 ABP2 1.5 ns10 6 ns01 3 ns11 Operation 3 contiguous cycles of phase delay < 15 ns must occur before Lock Detect is set. LDP 1 5 contiguous cycles of phase delay < 15 ns must occur before Lock Detect is set. Operation Normal operation SYNC

1 Prescaler resynchronized with nondelayed

1 Prescaler resynchronized with delayed form

Table 4. AB Counter Latch

  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • •• Charge Pump Current Setting Operation Current setting 1 is always used CP Gain F4 (Function Latch D89) Fastlock Enable

1 Current setting 2 is used until fastlock mode exits (returns to current setting 1)

  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • ••
  • •• N/A N/A B11 B12 40• •• 000 B13 B ≥ A † X = Don’t Care

Table 5. Function Latch

1 R, A, B counters

1 Digital lock detect

0 N divider output10

1 DVDD10

0 R divider output01

1 Analog lock detect01

0 Serial data output11

1 DGND11

0 Normal

1 Tri-State

1 Fastlock mode 1

11 Fastlock mode 2

Table 6. Initialization Latch

Table 7. R Counter Latch are used to select the chosen value for the 14-bit counter. DB2 is the LSB and DB15 the MSB. the anti-backlash pulse; the values allowed are 1.5 ns, 3 ns, and 6 ns. it to 1 results in a precision of five cycles. DB21−22 control the sync/delay operation of the device. If DB21 is 0, then the device is in normal operation. resynchronization of the prescaler output, whereas setting DB22 to 1 utilizes a delayed form. Table 8. N Counter Latch programming (DB7, DB6, DB5, DB4, DB3,DB2) = (0,0,0,0,1,0) results in a value of 2 for the A counter. switches into fastlock and when this bit is 0, the device exits fastlock (fastlock mode 1).

Bits DB22−DB23 of the N counter latch are reserved and can be treated as don’t cares by the user. Table 9. Function Latch application, this bit should be set to 0. enabling programming of the device. The hardware power down (CE set to 0) is immediate and asynchronous. of the device is attained when this bit is 0. DB13, DB12, DB11) = (0,0,1,0) results in 11 cycles before the Fastlock Mode times out. actual value of the maximum charge pump current will be dictated by the resistor placed outside on RSET (pin1).

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com Prescaler Selection DB22−DB23 of the function latch controls the prescaler value for the device. There are four possible settings (9/9, 16/17, 32/33, 64/65). For example, setting (DB23, DB22) = (1,0) results in a prescaler choice of 32/33. Initialization Latch / Programming After Power Up Setting (DB1, DB0) = (1,1) selects the initialization latch. The make-up and programming of the initialization latch is identical to that of the function latch. The difference here is that this latch can be used in order to program the device at power up. When the initialization latch is programmed, an internal reset occurs at all the counters (R, A, B) who become ready to get loaded, assuring that the next time data is loaded for the A and B counters the device begins counting efficiently. Subsequent programming of the A and B counters will not, however, cause this internal pulse to recur. This pulse is also used to gate the synchronous power down when that mode is engaged. As soon as the device exits power down, the counting resumes promptly. Alternate Ways of Programming After Power Up In addition to the method of using the initialization latch described above, the user can also utilize the CE pin to achieve initialization. Since the CE does not halt the operation of the serial port, the user can preprogram the counters and as soon as the device is enabled, the counters operate and the device reaches a steady-state and functions normally. A third option in power up is the counter reset method. The function latch is programmed with the desired data, and in addition DB2 (the counter reset bit) is set to 1. The R counter latch is programmed next, followed by the N counter latch. Finally, the function latch is programmed again, but this time with a 0 in the bit DB2, disabling the counter reset. The charge pump is 3-stated during the reset, but the synchronous power down is not triggered. Prescaler Resynchronization DB22 and DB21 of the R counter latch are used to control the delay (DLY) and resynchronization (SYNC) functions of the device. If SYNC is set to 1, then the output of the prescaler is resynchronized with the RF input. In addition, if DLY is also 1, the output of the prescaler gets resynchronized with a delayed form of the RF input signal. In either case, taking the SYNC to 0 reverts the device to normal operation. The use of the SYNC and DLY functionality can improve the device’s phase noise performance by a few dBs. It is, however, susceptible to potential malfunction, in case the chosen edge of the RF input coincides with the prescaler. This phenomenon may be mitigated by using the DLY function, but is nonetheless unpredictable and care should be applied, as fluctuations in temperature, supply and frequency can alter the point at which the feature fails to operate. The normal operation of the device calls for both DLY and SYNC to be set to 0, which is the way the TRF3750 has been characterized.

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com

APPLICATION INFORMATION

SYNTHESIZING A SELECTED FREQUENCY The TRF3750 is an integer-N PLL synthesizer, and because of its flexibility (14-bit R, 6-bit A, 13-bit B counter, and dual modulus prescaler), is ideal for synthesizing virtually any desired frequency. Let us assume that we need to synthesize a 900-MHz local oscillator, with spacing capability (minimum frequency increment) of 200 kHz, as in a typical GSM application. The choice of the external reference oscillator to be used is beyond the scope of this section, but assuming that a 10-MHz reference is selected, we calculate the settings that yield the desired output frequency and channel spacing. There is usually more than one solution to a specific set of conditions, so below is one way of achieving the desired result. First, select the appropriate R counter value. Since a channel spacing of 200 kHz is desired, the PFD can also be set to 200 kHz. Calculate the R value through R = REFIN/PFD = 10 MHz / 200 kHz = 50. Assume a prescaler value of 8/9 is selected. This is a valid choice, since the prescaler output will be well within the 200-MHz limit (900 MHz / 8 = 112.5 MHz). Select the appropriate A and B counter values. We know that RFOUT = f PFD x N = (fREFIN / R) x (A + P x B). Therefore, we need to solve the following equation:

900 MHz = 200 kHz x (A + 8 x B)

Clearly there are many solutions to this single equation with two unknowns; there are some basic constraints on the solution, since 3 ≤ B ≤ 8191, and also B ≥ A. So, if we pick A = 4, solving the equation yields B = 562. Thus, one complete solution would be to choose: R = 50, A = 4, B = 562, and P = 8/9, resulting in the desired N = 4500. The GUI software accompanying the evaluation board of the TRF3750 includes an easy Parameter Selection Assistant that can directly propose appropriate values for all the counters given the user’s requirements. In addition, the software can configure all the possible settings of the TRF3750 and can output the data stream required, so that the user has a reference when programming the serial port. To complete the example, the serial port has to be programmed in order for the correct frequency to appear at the output of the complete PLL. Assuming that the user wanted to program the same modes as used in the RF Performance Specifications section, a possible sequence of serial data going into the device could be the one listed below for the three different latches (note that the initialization latch is not used in this example): Table 10. R Counter Latch Programming Example

10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 11. N Counter Latch Programming Example Table 12. Function Latch Programming Example

SLWS146A − MARCH 2004 − REVISED NOVEMBER 2004 www.ti.com Building a Complete PLL Using the TRF3750 This application of the TRF3750 is just one of many possible ways in which a wireless infrastructure transmitter LO can be implemented for GSM applications and beyond. Supplies/Decoupling Appropriate decoupling is important in ensuring optimum noise performance of the device. Ideally, the AVDD and DVDD supplies should be separated through a ferrite and be at the same potential. A larger capacitor, in the order of a 10 µF, should be placed in the supply chain, followed by a couple of small value decoupling capacitors very close to the device’s supply pins. Typical values are 0.1 µF and 10 pF. The decoupling capacitors should not be shared and should be chosen to have low ESR. The VCP supply needs to be at least 1 V greater than the AVDD and DVDD supplies and similar decoupling should be applied. Reference A large range of frequencies can be used for the reference input. In this example, an external TCXO of 10 MHz is used to provide the stable reference frequency for the REFIN pin of the device. The quality of the reference oscillator is important, and its phase noise needs to be significantly lower than what is expected of the entire loop as it does not get attenuated in the loop. Typically, such devices do not require 50-Ω terminations and can be taken into the PLL ac coupled. The TRF3750 has a large range of power levels that it can accept at the REFIN input; however stronger signals result typically in better phase noise performance. Values of +5 dBms (referred to 50 Ω) should yield excellent performance. The TRF3750 is compatible with most commercially available oscillators. VCO Selection Plenty of VCOs exist in the market that can cover the frequency range of all wireless applications today. One clear advantage of the TRF3750 is that it features an extended charge pump supply, allowing interface to VCOs with larger tuning ranges. V CP can be as high as 8 V, which implies that VCOs with tuning voltage ranges of 7 V can easily be accommodated. In closing the loop with the VCO, it is important to ensure that proper termination is observed, especially in the higher range of frequency operation. A standard resistive splitter implementation works well, where each of the three Rs in the classic T connection assume the value of 16.6Ω. In other cases where impedance matching is less critical than getting maximum power out of the whole PLL loop, the user may decide to leave the resistors out and just tap off a trace from the VCO output and feed it back to the synthesizer. Additionally, a small series resistor can be placed in the feedback path towards the TRF3750 so as to reduce the relative power delivered to the PLL versus that available for the transmitter. The VCO’s supply should also be decoupled as recommended by the manufacturer. Loop Filter Design Numerous methodologies and design techniques exist for designing optimized loop filters for particular applications. The loop filter design can affect the stability of the loop, the lock time, the bandwidth, the extra attenuation on the reference spurs, etc. The role of the loop filter is to integrate and lowpass the pulses of the charge pump and eventually yield an output tuning voltage that drives the VCO. Several filter topologies can be implemented, including both passive and active. In this section, we use a third-order passive filter. For this example, we assume several design parameters. First, the VCO’s manufacturer should specify the device’s K V, which is given in MHz/V. Here we assume a value of 12 MHz/V, meaning that in the linear region, changing the tuning voltage of the VCO by 1 V induces a change of the output frequency of about 12 MHz. We already know that N = 4500 and that our f PFD = 200 kHz. We also further assume that current setting 1 will be used and be set to maximum current of 5 mA. In addition, we need to determine the bandwidth of the loop filter. This is a critical consideration as it affects (among other things) the lock time of the system. Assuming an approximate bandwidth of around 20 kHz is needed, and that for stability we desire a phase margin of about 45 degrees, the following values for the components of the loop filter can be derived. These values, along with the rest of the example circuitry, are shown in Figure 26. It is important to note here that there are almost infinite solutions to the problem of designing the loop filter and the designer is called to make tradeoff decisions for each application.

is typically a small portion of a bigger, complex circuit board, shielding is recommended to minimize EMI effects. Figure 26. Example Application of the TRF3750 for GSM Wireless Infrastructure Transceivers

Figure 27. Texas Instruments’ Proposed Direct Upconversion Wireless

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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