TRF3040 TI | Alldatasheet
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SLWS057 – AUGUST 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00682-GHz Main Synthesizer, Which Incorporates a Dual-Mode 32/33 and 64/65 Prescaler for Fractional-N Operation /C0068200-MHz Auxiliary Synthesizer, Which Incorporates an 8/9 Prescaler /C0068Separate Supply Terminals for Main and Auxiliary Charge Pumps /C0068Internal Compensation for Fractional Spurs /C0068Low Phase Noise /C0068Normal and Integral Charge Pump Outputs /C0068Fully Programmable Main and Auxiliary Dividers /C0068Serial Data Interface /C0068Direct I/Q Modulator /C0068Control Logic for Power-Down Modes /C0068Single-Sideband Suppressed Carrier (SSBSC) Converter to Generate TX Carrier /C0068200-MHz TXIF Synthesizer and Oscillator /C0068Variable Gain Amplifier (VGA) With 50 dB of Dynamic Range /C0068900-MHz Power Amplifier (PA) Driver With 9 dBm Typical Output Power /C0068Reference and Clock Buffers /C0068158 mA Typical Total Operating Current at
3.75 V Supply
/C006848-Pin Quad Flatpack (LQFP) 14 15 XTAL– TXEN DATA CLOCK LOCK STROBE V SSA VDD I I Q Q PHP VDDA RXLO+ RXLO– VSSA VCCP TXLO+ TXLO– VSSP PHSOUT IPEAK TANK+ 17 18 19 20 PHA RCLK MCLK 47 46 45 44 4348 42 PHI RF RN V GND 40 39 3841 21 22 23 24 INA RA TANK– VDDA DUALTX+ DUALTX– VDDA VDDA VDDA XTAL+ PT PACKAGE (TOP VIEW)SS VSSA VSSA VSSA VSSA VSSA VSSA These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1999, Texas Instruments Incorporated
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description
The TRF3040 is an integrated transmit modulator/synthesizer circuit suitable for 900-MHz analog and digital cellular telephones. It consists of a transmit intermediate frequency (TXIF) synthesizer and oscillator, a single-sideband suppressed carrier (SSBSC) converter, a direct conversion I/Q modulator, a variable gain amplifier (VGA) with a power amplifier (PA) driver, a main channel fractional-N synthesizer, an auxiliary channel synthesizer, a crystal oscillator reference buffer, and clock buffers in a small surface-mount package. Very few external components are required. The TXIF synthesizer produces the offset signal, TXIF, needed to translate the external local oscillator (TXLO) signal to the correct transmission frequency. The TXIF_VCO (voltage controlled oscillator) can operate from 90 MHz to 200 MHz, depending on the component values chosen for the external tank circuit. The TXLO signal may be differential or single-ended input. The direct conversion I/Q modulator places the modulation signal (p/4-DQPSK, FM) directly on top of the transmit carrier frequency. The VGA has an output range of –41 dBm to 9 dBm into a 200-W differential load. The balanced output signal simplifies the board layout making it easier to meet isolation requirements.
SLWS057 – AUGUST 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram TXIF_ VCO /C0013N (N = 6, 7, 8, 9) TXIF TXIF_LD +9 0 +9 0 +9 0 S Control Logic Main Prescaler ÷ 32/33 Main Phase Detector Reference Divider Auxiliary Phase Detector Auxiliary Divider Lock Detect TXLO + DUALTX+ I TXEN DATA CLOCK STROBE PHP PHI LOCK PHA –RXLO MCLK RCLK INA TXIF_LD DUALTX– TANK+ TANK– PHSOUT S +12 IPEAK 8 7 INR QQ XTAL XTAL XTAL OSC I RCLK Buffer Main Divider Main Prescaler ÷ 8/9 Auxiliary Synthesizer Input Buffer Reference Divider Buffer MCLK Buffer RXLO Buffer TXIF Phase Detector and Charge Pump TXIF_VCO Buffer TXIF_Buffer TXLO – BPF DUALTX VGA I/Q Modulator Transmit Intermediate Frequency Synthesizer SSBSC Converter and TXIF Buffer TXLO_Buffer TXRF PA Driver
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NAME NO. I/O DESCRIPTION ÁÁÁÁ ÁÁÁÁ CLOCK ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I Serial clock input ÁÁÁÁ ÁÁÁÁ DATA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I Serial data input ÁÁÁÁ DUALTX + ÁÁÁ 20† ÁÁÁ O Differential RF power amplifier driver ÁÁÁÁ ÁÁÁÁ DUALTX – ÁÁÁ ÁÁÁ 22† ÁÁÁ ÁÁÁ O Differential RF power amplifier driver ÁÁÁÁ ÁÁÁÁ GND ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Substrate (GND) ÁÁÁÁ ÁÁÁÁ I ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I Baseband inverting in-phase modulation input ÁÁÁÁ I ÁÁÁ ÁÁÁ I Baseband noninverting in-phase modulation input ÁÁÁÁ ÁÁÁÁ INA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I Auxiliary synthesizer input ÁÁÁÁ ÁÁÁÁ IPEAK ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ TX offset loop charge pump current setting resistor ÁÁÁÁ ÁÁÁÁ LOCK ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ O Lock detect output ÁÁÁÁ MCLK ÁÁÁ 38† ÁÁÁ O Buffered master clock output ÁÁÁÁ ÁÁÁÁ PHA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ O Auxiliary charge pump output ÁÁÁÁ ÁÁÁÁ PHI ÁÁÁ ÁÁÁ 48† ÁÁÁ ÁÁÁ O Main charge pump integral output ÁÁÁÁ ÁÁÁÁ PHP ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ O Main charge pump proportional output ÁÁÁÁ ÁÁÁÁ PHSOUT ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ O TX offset charge pump output ÁÁÁÁ Q ÁÁÁ ÁÁÁ I Baseband inverting quadrature modulation input ÁÁÁÁ ÁÁÁÁ Q ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ I Baseband noninverting quadrature modulation input ÁÁÁÁ ÁÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Auxiliary charge pump current setting resistor ÁÁÁÁ ÁÁÁÁ RCLK ÁÁÁ ÁÁÁ 39† ÁÁÁ ÁÁÁ O Buffered reference clock output ÁÁÁÁ RF ÁÁÁ
47 Fractional compensation charge pump current setting resistor
ÁÁÁÁ ÁÁÁÁ RN ÁÁÁ ÁÁÁ
46 Main charge pump current setting resistor
ÁÁÁÁ ÁÁÁÁ RXLO + ÁÁÁ ÁÁÁ
3 I Differential main synthesizer positive input
ÁÁÁÁ ÁÁÁÁ RXLO – ÁÁÁ ÁÁÁ
4 I Differential main synthesizer negative input
ÁÁÁÁ ÁÁÁÁ STROBE 31 I Data strobe input ÁÁÁÁ TANK + 12 I Differential TXIF_VCO tank positive input ÁÁÁÁ ÁÁÁÁ TANK – 13 I Differential TXIF_VCO tank negative input ÁÁÁÁ ÁÁÁÁ TXEN 35 I Transmit enable ÁÁÁÁ ÁÁÁÁ TXLO + 7 I Differential transmit LO positive input ÁÁÁÁ TXLO – 8 I Differential transmit LO negative input ÁÁÁÁ ÁÁÁÁ VCCP 6 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Main charge pump and bandgap supply voltage VDD 29 Digital supply voltage
2 Main prescaler and bandgap supply voltage
14 TX offset loop supply voltage
VDDA 24† RF modulator supply voltage
40 Oscillator and buffers supply voltage
44 Auxiliary charge pump supply voltage
17, 18 RF modulator ground
5 Main prescaler and bandgap ground
15 TX offset loop groundVSSA 16 TX offset loop and charge pump ground
21, 23 PA driver ground
30 Oscillator, MCLK, and RCLK ground
VSSP 9 Main charge pump ground XTAL + 37 I Crystal oscillator base input XTAL – 36 O Crystal oscillator emitter input † Pins have limited ESD protection
SLWS057 – AUGUST 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device, at these or any other conditions beyond those indicated under “recommended operating conditions”, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are in respect to VSSA (VSSA = VSSP = VSS = GND) recommended operating conditions PARAMETER MIN NOM MAX UNIT Supply voltage, VCCP , VDD , VDDA 3.6 3.75 3.9 V High-level input voltage, VIH (CLOCK, DATA, STROBE, TXEN) 0.7× VDD VDD +0.3 V Low-level input voltage, VIL (CLOCK, DATA, STROBE, TXEN) –0.3 0.3× VDD V Main synthesizer input frequency, fIN(RXLO ±) 2000 MHz Main synthesizer input power, PIN(RXLO ±), (AC coupled, 50-W single ended, 100-W differential) –17 dBm Transmit LO input frequency, fIN(TXLO±) 1050 MHz Transmit LO input power, PIN(TXLO±), (AC coupled, 50-W single ended, 100-W differential) –10 dBm TXIF_VCO tank differential input frequency, fIN(TANK±) 200 MHz Crystal oscillator input frequency, fIN(XTAL+) 25 MHz Auxiliary synthesizer input frequency, fIN(INA) 200 MHz Auxiliary synthesizer input voltage, VIN(INA), (AC coupled) 0.2 VPP In-phase differential input, I/I (quiescent) VDDA /2 V Quadraphase differential input, Q/Q (quiescent) VDDA /2 V Operating free-air temperature, TA –40 25 85 °C dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) supply current I = ICCP + IDD + IDDA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISLEEP Sleep mode supply current 2 3 mA ISTANDBY Standby mode supply current 22 mA IOPER_ANA Operating supply current – full power analog mode (MODE=0) 142 mA IOPER_DIG Operating supply current – full power digital mode (MODE=1) 158 mA dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) digital interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Output voltage low IO = 1 mA 0.050 V VOL O utput voltage, low IO = 2 mA 0.4 V VOH Output voltage high IO = –1 mA VDD – 0.050 V VOH O utput voltage, high IO = –2 mA VDD – 0.4 V
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHA Output current at PHA 200 250 300 mA DIPHA IPHA Relative output current variation (see Figure 1)R A = 100 kW , VPHA = VDDA /2 2% 10% DIPHA Output current matching PHA (see Figure 1) 10% charge pump PHP, normal mode, VRF = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP Output current at PHP ± 250 ± 288 ± 320 mA DIPHP IPHP Relative output current variation (see Figure 1)CN = 128, RN = 120 kW VPHP = VDDA/2 , 2% 10% DIPHP Output current matching PHP (see Figure 1) 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump PHP, speed-up mode, VRF = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP Output current at PHP ± 1.2 ± 1.6 ± 1.9 mA DIPHP IPHP Relative output current variation (see Figure 1)CN = 128, RN = 120 kW VPHP = VDDA/2 , 2% 10% DIPHP Output current matching PHP (see Figure 1) 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump PHI, speed-up mode, VRF = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHI Output current at PHI CN 128 RN 120 k W ± 3.3 ± 4 ± 4.5 mA DIPHI IPHI Relative output current variation (see Figure 1) CN = 128, CK = 3, C L = 1 RN = 120 kW , VPHA = VDDA /2, 2% 10% DIPHI Output current matching PHI (see Figure 1) CL = 1 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode.
SLWS057 – AUGUST 1999 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) fractional compensation PHP, normal mode, VRN = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP–FR Output current PHP vs. fractional numeratorFMOD = 1, RF = 120 kW, –340 –270 –170 nA DIPHP–FR IPHP–FR Relative output current (see Figure 1) CN = 128, CK = 3, VPHP = VDDA/2 , CL = 1 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. fractional compensation PHP, speed-up mode, VRN = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP–FR Output current PHP vs. fractional numeratorFMOD = 1, RF = 120 kW , –1.7 –1.4 –1.1 mA DIPHP–FR IPHP–FR Relative output current (see Figure 1) CN = 128, CK = 3, RF 120 kW , VPHP =VDDA/2 , CL = 1 15% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. fractional compensation PHI, speed-up mode, VRN = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHI–FR Output current PHI vs. fractional numeratorFMOD = 1, RF = 120 kW , –5.1 –4 –2.9 mA DIPHI–FR IPHI–FR Relative output current (see Figure 1) CN = 128, CK = 3, RF 120 kW , VPHI = VDDA/2 , CL = 1 15% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump leakage currents PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHI Output leakage current PHI VRF =V RN =V DDA VPHP =0t oVDDA ± 0.1 ±10 nA IPHA Output leakage current PHA VRF = VRN = VDDA , VPHP = 0 to VDDA ± 0.1 ±10 nA
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ac electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) transmit intermediate frequency synthesizer, SSBSC converter and I/Q modulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TXLO ± Transmit LO input frequency 900 1100 MHz TXLO ± Transmit LO input power AC coupled; 50-W single-ended, 100-W differential –13 –10 dBm TANK ± TXIF_VCO tank differential input frequency range 155 MHz PHSOUT TXIF_PD charge pump output level 0.5 VDDA –0.5 V IPEAK TXIF_PD charge pump current setting R IPEAK = 13 kW 2.3 mA Kf TXIF_PD phase gain PLL in phase lock 1.46 mA/rad XTAL+ XTAL oscillator input frequency 15 25 MHz XTAL + XTAL negative resistance With external capacitors –100 W RCLK Frequency range 20 MHz RCLK, MCLK Output levels RCLK, MCLK load circuit 0.7 1 1.4 VPPMCLK Harmonic content 10 dBc Differential input frequency 1.8 MHz I/I Q/Q Differential modulation level 0.8 0.9 1.0 VPEAKI/I, Q/Q Differential input impedance 10 kW DC bias point 1.65 1.7 2.0 V TXRF TX operating frequency range 820 920 MHz RF output frequency SE = 1, TXEN = 1, AMPS/DAMPS 820 853 MHz Output power (I/Q set to typical conditions) Open collector, matched to
200 W differential impedance
Li it i DAMPS d (I/Q i h l l t t 3rd order 33 36 dBc Linearity in DAMPS mode (I/Q in phase, levels set to nominal conditions Pout set to 8 dBm) 5th order 45 62 dBcnominal conditions Pout set to 8 dBm) 7th order 53 70 dBc Carrier suppressionI&Qi n quadrature VGA set to Pout = 8 dBm 26 40 dBcCarrier suppression, I & Q in quadrature VGA set to Pout = –38 dBm 33 dBc DUALTX ± Sideband suppression, I & Q in quadrature 25 43 dBc Adjacent channel noise power Ar 30 kHz offset –95 dBc/Hz Alternate channel noise power At 60 kHz offset –101 dBc/Hz TXLO 21 33 Upper sideband 21 60 TXLO conversion products (see Note 3) TXLO –2×TXIF 15 dBc TXLO ±3×TXIF 36 Harmonics ≤ 10th 21 Broadband noise (0-dB VGA or 9-dBm output, whichever is less 869 to 894 MHz –124 dBc/Hz NOTE 3: Parameters may vary depending on external output matching circuit.
SLWS057 – AUGUST 1999 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ac electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) frequency synthesizers main divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RXLO ± Main synthesizer input frequency 2000 MHz RXLO ± Main synthesizer input power AC coupled, external shunt 50-W single-ended, 100 W differential –17 dBm RXLO ± Main synthesizer input harmonics and subharmonicsNo multiclocking 30 dBc reference divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INR Operating frequency 25 MHz INR Harmonics No multiclocking 10 dBc auxiliary divider PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Auxiliary synthesizer input frequency 110 MHz INA Auxiliary synthesizer input signal amplitude No multiclocking 0.2 VPP Auxiliary synthesizer input harmonics 10 dBc ZINA Auxiliary synthesizer input impedance Resistance 5 100 kW ZINA Auxiliary synthesizer in ut im edance Capacitance 3 pF timing requirements, serial data interface (see Figure 6) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DATA Serial data input rate 10 MHz CLOCK Serial data clock input 10 MHz STROBE Serial data strobe input 10 TXEN Transmit enable Transmit enable TXEN=1 LogicTXEN Transmit enable Transmit disable TXEN=0 Logic tsu Setup time: Data to CLOCK, CLOCK to STROBE 30 ns tk Hold time. CLOCK to DATA 30 ns CLOCK 30 STROBE (B-G words) 100 tsw Pulse width A-word, PR = 01 1/fVCO × (NM2 × 65) + tw ns A-word, PR = 10 1/fVCO × (NM2 × 65) + (NM3+1) × 72) + tw
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Figure 1. Charge-Pump Output Current Definitions charge-pump sourcing current output at a given charge-pump output (see Figure 1). D IOUT MATCH = ISINK – ISOURCE ; with V1 ≤ Voltage ≤ V2.
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APPLICATION INFORMATION
.01mF 15mF VCC OSC_VCC 9.1kW .01m F C5 15pF C50 15pF 4.7kW RCLK 2200nHXTAL 9.1kW .01mF C7 15pF C71 15pF 4.7kW MCLK 2200nHC11 DNP C12 DNP R11 DNP TXEN DATA CLOCK LOCK STROBE C13 27pF C14 .01m F C15 15mF R12 VCC D_VCC R13 TRF3040 C21 DNP R15 C22 DNP R18 Q C29 DNP R19 C31 DNP C23 27pF C24 C25 .01 mF R16 VCC RF_VCC C28 27pF C27 .01mF C26 TANK– PD_VCC R17 VCC DUALTX C34 27pF C98 15 m F C99 .01mF R57 VCC PA_VCCL3 12nH 12nH DUALTX– C30 2.2pF C33 10pF C35 2.2pF BALUN1 SLT–090G 5C32 1.8pF TANK PHSOUTR14 18kW PHP RXLO TXLO C97 27pF C101 .01mF C104 15mF R23 VCC AUX_VCC PHI 120kW 33kW 100kW PHA C10 27pF .01mF 15mF P_VCC R1010 VCC C19 27pF C18 .01mF C17 15mF CP_VCC R510 VCC INA 15mF Note: DNP = Do Not Place C16 22pF C111 3.3pF 15 mF Figure 2. Evaluation Board Schematic
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M/CO__VCC PHP TXLO + PHI RXLO + C102 27pF L11 12nH R24 C45 100m F C103 27pF C46 .01m F C47 DNP C107 27pF (100mF) VT VVCO 2X7 11 X R20 1.5kW C36 470pF R21 3.9kW C37 1500pF C38 1500pF R22 5.1kW C39 .022m F TXLO R43 R25 R30 R42 180 R40 180 L12 5.6nH C49 4.7pF R26 L13 1.5nH C51 1pF R28 49.9 C42 22pF C48 22pF STRIPLINE J9C55 DNP 9dB ATTENUATOR PAD R27 62R29 100 R31 100 R32 49.9 RXLO 5dB ATTENUATOR PAD MAIN VCO R61 10 MW C56 100 pF NET00033 R37 1 kW R39 1 kW C65 100 pF C63 27 pF C62 .01 mF C61 1 mF R38 1 kW VCC VC1:A KV1470 VC1:B KV1470 C60 3 pF 82 nH TANK+ TANK– PHSOUT C57 330 pF C58 3300 pF R36 360 W R35 51 kW C59 33 pF C64 33 pF TANK CKT W W W WW W W W W W Figure 2. Evaluation Board Schematic (continued)
SLWS057 – AUGUST 1999 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 .01 mF C67 27 pF R41 10 W TCXO_V CC TCO-980 TOYOCOM TCXO C70 0.1 mF C66 .01 mF J10 VCC VCONT OUT GND XTAL REF_IN C81 1 mF C80 .01 mF C79 27 pF R47 10 W AVCO_V CC VCO190-S VARIL AVCO C82 0.1 mF C78 .022 mF J11 VCC MOD OUT VT INA AUX_OUT C77 .022 mF R49 18 W R50 49.9 W R48 18 W PHA R52 0 W R53 6.2 kW R51 1.5 kW C86 0.015 pF C84 470 pF C85 DNP C83 1000 pF R46 18 W AUXILIARY VCO & REFERENCE TCX0
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OPTO_V CC R55 220 W C88 1 mF OPTO_V CC _TP 3.75 V SETTING W CCW CW R59 1 kW LM317LD VR2 NC VO VI VO VO NC VO ADJ 5 V R56 220 W C89 1 mF 5V_TP 5 V SETTING W CCW CW R60 1 kW LM317LD VR5 NC VO VI VO VO NC VO ADJ MVCO_V CC R58 220 W C94 1 mF MVCO_V CC 3.75 V SETTING W CCW CW R63 1 kW LM317LD VR6 NC VO VI VO VO NC VO ADJ TCXO_V CC R64 220 W C100 1 mF TCXO_TP 3 V SETTING W CCW CW R80 1 kW LM317LD VR3 NC VO VI VO VO NC VO ADJ AVCO_V CC R65 220 W C90 1 mF AVCO_V CC _TP 5 V SETTING W CCW CW R67 1 kW C87 1 mF GND POWER POWER Tie GNDs together at this point VR4 LM317MDT VOUTVIN 23 R66 220 W C91 1 mF W CCW CW R68 500 W VCC _TP ADJ VCC 3.75 V SETTING R79 51 W C109 10 mF C110 10 mF C92 .01 mF R69 1.8 kW R70 1.8 kW R71 1.8 kW R72 1.8 kW R73 3.6 kW R74 3.6 kW R75 3.6 kW R76 3.6 kW 5 V DATA_TP1 TXEN_TP1CLOCK_TP1 OPTO_V CC C93 0.1 mF TXEN DATA CLOCK STROBE STROBE_TP1 4N28S 4N28S 4N28S 4N28S 6 5 MOC8030 LOCK C95 0.1 mF R77 2 kW OPTO_V CC LD_TP1LOCK_DETECT R78 2.7 kW 5 V C96 0.1 mF P1:B CLOCK P1:C DATA P1:D STROBE P1:E TXEN P1:J LD P1:R P1:S P1:T P1:U P1:V P1:W P1:X P1:Y
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Table 1. TRF3040 Evaluation Board Parts List (continued)
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power-saving modes disable the circuitry that is not in use at the time in order to reduce power consumption. enabled during each mode, and Table 3 describes the related programming control bit(s). Table 2. TRF3040 Power-Mode Function Usage Table 3. TRF3040 Programming Power-Mode Function synthesizer. Figure 3 illustrates the functionality of the frequency synthesizer.
Figure 3. Frequency Synthesizer Functional Block Diagram
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The TRF3040 operates using CLOCK, DATA, and STROBE pins of the serial data interface. The serial programming data is structured into 24-bit words, of which one or four bits are dedicated address bits. Figure 4 shows the format and the content of each word. Table 4 lists the symbols, number of bits, and the function for each word used in the standard programming mode (ALT = 0). Similarly, the alternate programming mode (ALT = 1) is described in Figure 5 and Table 5. Figure 6 shows the timing diagram for the serial input. When the STROBE goes low, the signal on the DATA input is clocked into a shift register on the positive edges of the CLOCK. When the STROBE goes high, depending on the 1 or 4 address bit(s), data is latched into different working or temporary registers. To fully program the modulator/synthesizer, five words must be sent: G, D, C, B, and A. The E-word is for testing purposes only. The A-word contains new data for the main divider. The A-word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when reprogramming the main divider. The data for CN and PR is stored by the B-word in temporary registers. The data in these temporary registers is loaded into the work registers together with the A-word. This avoids false main-divider input when the A-word is loaded. The value of the auxiliary divider ratio, NA, is defined by a 13-bit field, and the operational mode of the main synthesizer is determined by the least significant bit (LSB) of the C-word: Standard mode: ALT = 0 Alternate mode: ALT = 1 The content of the D-word defines the operation of the reference divider. The OR function of bits EA and EM enables the buffer/amplifier input stage. The reference divider ratio is determined by the value of NR. The main and auxiliary synthesizer sections can individually select a reference postscaler division of 1, 2, 4, or 8 by selecting fields RSM and RSA, respectively. The G-word programs all other functions: VGA power control, ÷ N (TXIF loop), SE (TXIF synthesizer loop enable), AMPS and DAMPS modes, and sleep mode. The E-word is for testing purposes only and is reset when programming the D-word.
0 NF NM1 NM3 NM2
1001 N A 000000C
Figure 4. Serial Input Word Format (Standard Programming, ALT = 0)
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Table 4. Standard Programming (ALT = 0) Function Table (see Notes 4 and 5) † Not including reset cycles and fractional-N effects. R1 = 64, R2 = 65, R3 = 72. NOTES: 4. Data bits are shifted in on the leading clock edge, with the least significant bit (LSB) first in and the most significant bit (MSB) last.
- On the rising edge of the strobe and with the address decoder output = 1, the contents of the input shift register are transferred to
- Field bits setting for the TXIF synthesizer divider ratio
- The MODE bit allows a reduction in current for the DUALTX output driver while in AMPS mode.
- The ALT programming bit allows the user to specify an enhanced programming scheme which allows for a fully programmable
fractional modulus of 1 to 16 for the main synthesizer.
1000 G C N C K C L
Figure 5. Serial Input Word Format (Alternate Programming, ALT = 1)
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Table 5. Alternate Programming (ALT = 1) Function Table Figure 6. Serial Input Timing Sequence
by a single-ended input buffer. The OR function of the serial input bits EM an EA enables this input buffer. Figure 7. Reference Variable Divider bit EA = 1. The auxiliary divider consists of a 13-bit programmable divider with a 8/9 dual-modulus prescaler. The 13-bit field divider is composed of two separate counters: a 3-bit NA2 counter and a 10-bit NA1 counter. of the auxiliary divider is shown in Figure 8.
1001 N A 000000C Word
Figure 8. 13-Bit Field Divider
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in Table 6 (see also Figure 4). Table 6. Main Variable Divider Bit Capacity of 4032 and 266303, respectively. maximum divide ratios of 1096 and 264335, respectively. both counters reset and the cycle repeats.
5 Bits 13 Bits
Figure 9. Main Divider Organization signal is at an active high. reference comparisons at integer multiples of the desired system channel spacing. where 0 ≤ NF < FMOD and 1 ≤ FMOD ≤ 16. sections to divide by N or N+1. accumulator and the resulting N or N+1 division for two fractional division ratios.
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Table 7. Fractional Accumulator Operation accumulator overflow cycle of this particular frequency is described with NF=3 and FMOD=8 (see Table 7). Figure 10 illustrates the division by N and N+1 for this 3/8 fractional channel example. Figure 10. 3/8 Fractional Channel Main Divider Operation
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between the main and compensation pulses. fractional-N sidebands based on VCO frequency and reference frequency. The main VCO is locked on channel.
- Determine the fundamental fractional-N pulse-width portion of the main PHP charge-pump output
waveform for the lower, upper, and mean frequencies. Table 8 also shows the area of the fractional-N portion of the main PHP charge-pump waveform. Table 8. Main PHP Fractional-N Pulse Widths and Areas for 3/8 Channel
- Determine the pulse width of the compensation charge-pump output waveform.
- Determine the fundamental compensation charge pump current magnitude using the fundamental main
Table 9 shows the magnitude of the compensation pulse as a function of the fractional accumulator. Table 9. Compensation Pulse Magnitudes for 3/8 Channel
- Using the result of Step 2, determine the value of RF to give the fundamental compensation pulse
- Determine values of CN and RN to give a main PHP charge-pump peak current of 500 mA. Assume a
mid-range value of CN equal 128.
- The value of the fundamental compensation pulse magnitude calculated in step 3 is fixed, and the
waveform pulse width decreases proportionally, thereby decreasing the area under the same waveform.
SLWS057 – AUGUST 1999
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PRINCIPLES OF OPERATION 1234 main divider – fractional-N sidebands and compensation (continued) The fundamental area mean value of the fractional-N portion of the main PHP charge-pump waveform was calculated to be 0.018268 pSA. If the fundamental area of the fractional-N portion of the main PHP charge-pump waveform uses the actual pulse widths calculated in step 1 in place of the average pulse width, the fractional-N main PHP areas are as follows: Frac Area-LWR = 63.83 ps x 0.288 mA = 0.018383 (E-12 second × Amps), FracArea-UPR = 63.031 ps x 0.288 mA = 0.018383 (E-12 second × Amps). The actual areas under the fractional-N portion of the main PHP waveform require slight modification in the charge-pump current. The variation of CN required for area equalization can be determined using a simple ratio form: CN LWR /C0043 FracArea–AVG FracArea–LWR /C0032CN AVG /C00430.018268 0.018383 /C0032128 /C0043127, CN UPR /C0043 FracArea–AVG FracArea–UPR /C0032CN AVG /C00430.018268 0.018153 /C0032128 /C0043129. Therefore, CN values would vary from 127–129 over the VCO frequency range of 1958.19–1983.15 MHz for optimum fractional-N sideband suppression. Due to component and circuit tolerances, additional deviations in CN may be appropriate. phase detectors The main and auxiliary synthesizer sections (see Figure 13) incorporate dual D-type flip-flop phase-frequency detectors (PFD). The PFD has gain with phase error over a range of +/–2p and exhibits infinite pull-in range. Dead-band compensation about zero phase error is provided by forcing the sourcing and sinking charge pumps to have a minimum on-time rate of 1/f Ref when the loop is operating in a locked condition. The phase detectors can be programmed for polarity sense. Normally, external system VCOs have a positive slope control voltage-frequency characteristic. Some VCOs have a negative slope characteristic. The TRF3040 main and auxiliary phase detectors can be programmed for use with positive or negative slope VCOs using the MCP and ACP fields, respectively, in the B word (EPM mode). For positive slope VCOs: MCP = ACP = 0; for negative slope VCOs: MCP = ACP = 1.
Figure 13. Main and Auxiliary Phase Detector Circuit resistors are used to achieve desired charge-pump peak currents. Table 10. Charge Pump Current Plans Divider – Fractional-N Sidebands and Compensation.
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because the serial interface operates independent of the reference input for the loading of serial words. Table 11. Loop Enable/Disable coefficients CN, CL, and CK. G-field in the B-word and the reference frequency divider period.
lists all available test modes and associated programming bits. Table 12. Test Modes carrier (SSBSC) converter, an I/Q modulator, and an output VGA. signal (enable = 1) turns on the modulator and the VGA. thus disabling the transmit intermediate synthesizer, the I/Q modulator, and the VGA.
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Figure 14. Transmit Intermediate Frequency Synthesizer Reset Circuit Figure 15. Transmit Intermediate Frequency Synthesizer Reset Circuit Timing Diagram
SLWS057 – AUGUST 1999 37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION transmit intermediate frequency (TXIF) synthesizer The transmit intermediate frequency (TXIF) PLL portion of the TRF3040 design consists of the following functional blocks: a reference oscillator, a TXIF phase detector, a divide-by-N (÷N), a TXIF_VCO, and an external passive loop filter. reference oscillator The reference crystal oscillator (XTAL OSC) generates the internal reference signal INR. This signal is directly fed to the phase detector of the PLL in the transmit modulator section and to three other different buffers. The first buffer feeds the reference divider of the main phase detector and the auxiliary phase detector. The second buffer, MCLK, is used to provide a clock for external digital circuitry, which is always on. The third buffer, RCLK, is used as a clock for the external circuitry that is used in standby and transmit modes. TXIF phase detector and charge pump The phase comparator compares the output of the divider with the reference oscillator. It provides an output proportional to the phase difference between the divided down TXIF_VCO and the reference. This output is then filtered and used as the control voltage input to the TXIF_VCO. The phase detector is a Gilbert multiplier cell type, with a linear output from 0 to p ( p /2 ± p /2), followed by a charge pump. The charge-pump peak output current could be programmable to 6.4 mA using an external resistor. TXIF lock detect A lock detect signal is provided and ANDed together with lock detect signals from both the main channel synthesizer and auxiliary synthesizer. While in standby mode, the lock detect signal is forced to a valid lock state so that the lock detect signal will indicate when the main and auxiliary phase detectors achieve phase lock. divide-by-N The ÷N is a 2-bit programmable divider that can be configured for any integer division from 6 to 9. The field bits setting for this ÷N is described in Note 6. The divider converts the VCO output down to the reference frequency before feeding it into the phase comparator. TXIF_VCO The voltage controlled oscillator, TXIF_VCO, generates the transmit IF frequency, TXIF, between 90 MHz and 200 MHz. This TXIF_VCO is configured using an external parallel inductor and a dual common-cathode tuning-varactor diode. DC blocking capacitors are used to isolate the varactor control voltage from the VCO tank dc bias voltages. SSBSC converter and TXIF buffer The TXIF buffer provides isolation between the SSBSC converter and the TXIF_VCO output. The converter is an active Gilbert cell multiplier (matched pair) combined with two quadrature phase shift networks and a band-pass filter. The SSBSC converter rejects the unwanted upper sideband that would normally occur during the conversion process.
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outputs are provided to the variable gain amplifier, DUALTX VGA. Figure 16. Power Control
SLWS057 – AUGUST 1999 39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 4040052/C 11/96 0,13 NOM 0,17 0,27 SQ 6,80 7,20 5,50 TYP 0,25 0,45 0,75 0,05 MIN SQ9,20 8,80 1,35 1,45 1,60 MAX Gage Plane Seating Plane 0,10 0°–7° 0,50 M0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. This may also be a thermally enhanced plastic package with leads connected to the die pads.
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