TRF2056PW

TRF2056 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 24

Technical content

/C0070 3/C0065 32 /C0070/C0065/C0067/C00653 SLWS111– NOVEMBER 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.2-GHz Operation Two Operating Modes: – Philips SA7025 Emulation Mode Terminal-for-Terminal and Programming Compatible – Extended Performance Mode (EPM) Dual RF-IF Phase-Locked Loops Fractional-N or Integer-N Operation Programmable EPM Fractional Modulus of 1–16 Normal, Speed-Up, and Fractional Compensation Charge Pumps Low-Power Consumption

description

The TRF2056 device is a low-voltage, low-power consumption 1.2-GHz fractional-N/integer-N frequency synthesizer component for wireless applications. Fractional-N division and an integral speed-up charge pump achieve rapid channel switching. Two operating modes are available: 1) SA7025 emulation mode in which the device emulates the Philips SA7025 fractional-N synthesizer and 2) extended performance mode (EPM), which provides additional features, including fractional accumulator modulos from 1 to 16 (compared to only 5 or 8 for the SA7025 synthesizer). The TRF2056 device provides external loop filters and all functions necessary for voltage-controlled oscillator (VCO) control in a dual phase-locked loop (PLL) frequency synthesizer system. A main channel is provided for radio frequency (RF) channels and an auxiliary channel for intermediate frequency (IF) channels. The current-output charge pumps directly drive passive resistance-capacitance (RC) filter networks to generate VCO control voltages. Rapid main-channel frequency switching is achieved with a charge pump arrangement that increases the current drive and alters the loop-filter frequency response during the speed-up mode portion of the switching interval. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CLOCK DATA STROBE VSS RFIN RFIN VCCP REFIN RA AUXIN VDD TSETUP LOCK/TEST RF RN VDDA PHP PHI V SSA PHA PW PACKAGE (TOP VIEW) Copyright  2000, Texas Instruments Incorporated /C0067 -%)( %, .++!(- , )" *. -%)( , (,-+.’!(-, + / +%&1 %(&. ! -!,-%(# )" && * ’!-!+,

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram† Serial Control Shift Registers Common Registers EPM Registers SA7025 Registers Conversion and Selection‡ CLOCK STROBE Fractional Accumulator FMOD 5 NF 4 Fractional Compensation Control Lines Compensation Charge Pump Phase Detector Proportional Charge Pump Reference Divider Integral Charge Pump CK 18N NR Phase Detector Auxiliary Charge Pump Auxiliary Divider4/1 12NAPA REFIN AUXIN RF RN PHI LOCK/ TEST RA PHA Main Divider (N/N+1) RFIN RFIN Prescaler CL 2CN 8 PHP CL 2CN 8 1 2 4 8 Select Select SM SA DATA 2 † Terminals 4, 7, 12, 15, and 20 are for supply voltage. Terminal 19 is for testing. These terminals are not shown. ‡ Conversion and selection block provides emulation of SA7025 64/65/72 triple-modulus prescaler operation using the TRF2056 32/33 dual-modulus prescaler. EM+EA EM EA

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION ÁÁÁÁ ÁÁÁÁ AUXIN ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Auxiliary channel RF input ÁÁÁÁ ÁÁÁÁ CLOCK ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Serial interface clock signal ÁÁÁÁ ÁÁÁÁ DATA ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Serial interface data signal ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ LOCK/ TEST ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁ ÁÁ O Lock detector/test mode output ÁÁÁÁ ÁÁÁÁ PHA ÁÁÁ ÁÁÁ ÁÁ ÁÁ O Auxiliary charge pump output ÁÁÁÁ PHI ÁÁÁ ÁÁ O Integral charge pump output ÁÁÁÁ ÁÁÁÁ PHP ÁÁÁ ÁÁÁ ÁÁ ÁÁ O Proportional charge pump output ÁÁÁÁ ÁÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Resistor to VSSA sets auxiliary charge pump reference current ÁÁÁÁ ÁÁÁÁ REFIN ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Reference frequency input signal ÁÁÁÁ ÁÁÁÁ RF ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Resistor to VSSA sets compensation charge pump reference current ÁÁÁÁ ÁÁÁÁ RFIN ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Prescaler positive RF input ÁÁÁÁ ÁÁÁÁ RFIN ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Prescaler negative RF input ÁÁÁÁ ÁÁÁÁ RN ÁÁÁ ÁÁÁ ÁÁ ÁÁ I Resistor to VSSA sets proportional and integral charge pump reference current ÁÁÁÁ STROBE ÁÁÁ ÁÁ I Serial interface strobe signal ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ TSETUP ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁ ÁÁ I Test setup for terminal 18. For lock detect output, terminal 19 connects to VCC through a pullup resistor; for test mode output, terminal 19 terminates to ground. ÁÁÁÁ ÁÁÁÁ VCCP ÁÁÁ ÁÁÁ ÁÁ ÁÁ Prescaler positive supply voltage ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁ ÁÁÁ ÁÁ ÁÁ Digital supply voltage ÁÁÁÁ ÁÁÁÁ VDDA ÁÁÁ ÁÁÁ ÁÁ ÁÁ Analog supply voltage ÁÁÁÁ ÁÁÁÁ VSS ÁÁÁ ÁÁÁ ÁÁ ÁÁ Digital ground ÁÁÁÁ ÁÁÁÁ VSSA ÁÁÁ ÁÁÁ ÁÁ ÁÁ Analog ground absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are with respect to VSSA .

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions MIN NOM MAX UNIT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VDDA ÁÁÁÁ ÁÁÁÁ 3.3 ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 3.9 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Supply voltage, VCCP , VDD ÁÁÁÁ ÁÁÁÁ 2.9 ÁÁÁ ÁÁÁ 3.3 ÁÁÁÁÁ ÁÁÁÁÁ 3.9 ÁÁÁ ÁÁÁ V Operating free-air temperature, TA –40 25 85 °C dc electrical characteristics VDD = VDDA = VCCP = 3.3 V, TA =25/C0095C internal registers: CN = 128, CL = 1, CK = 3, PA = 1 external components: RN = 18 kW , RF = 20 kW , RA = 100 kW (unless otherwise noted) supply current: I = IDD + ICCP + IDDA PARAMETER TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ ISTANDBY Total standby supply currents EM = EA = 0 (see Note 2) ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 200ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ IMAIN Operational supply currents EM = 1, EA = 0 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 7.0 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ IAUX Operational supply currents EM = 0, EA = 1 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 1.5 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ ÁÁÁÁÁ ITOTAL Operational supply currents ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ EM = EA = 1 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 7.5 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ mA NOTE 2: V RN = VRA = VRF = VDDA digital interface PARAMETER MIN TYP MAX UNIT VIH High-level input voltage DATA CLOCK STROBE 0.7 VDD VDD + 0.3 V VIL Low-level input voltage DATA, CLOCK, STROBE –0.3 0.3 VDD V IIH High-level input current DATA CLOCK STROBE 10 mA IIL Low-level input current DATA, CLOCK, STROBE 10 mA charge pump currents (see Figure 1) auxiliary charge pump PARAMETER ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ |IPHA | Output current PHA ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VPHA = 0.5 VDDA ÁÁÁ ÁÁÁ 200 ÁÁÁ ÁÁÁ 250 ÁÁÁ ÁÁÁ 300 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ DIPHA |IPHA | Relative output current variation PHA (see Figure 1) ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 10% ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DIPHA Output current matching PHA (see Figure 1) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VPHA = 0.5 VDDA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ±50 ÁÁÁ ÁÁÁ mA proportional charge pump, normal mode, VRF = VDDA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ TEST CONDITIONS MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ |IPHP-NM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current PHP ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VPHP = 0.5 VDDA 400 ÁÁÁ ÁÁÁ 500 ÁÁÁ ÁÁÁ 600 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ DIPHP-NM |IPHP-NM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Relative output current variation PHP (see Figure 1) ÁÁÁÁÁÁÁ Á ÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 10% ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DIPHP-NM ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current matching PHP (see Figure 1) ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ VPHP = 0.5 VDDA ÁÁÁ ÁÁÁ ±50 ÁÁÁ ÁÁÁ mA

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 charge pump currents (see Figure 1) (continued) proportional charge pump, speed-up mode, VRF = VDDA (see speed-up mode operation) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER TEST CONDITIONS MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ |IPHP-SM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current PHP VPHP = 0.5 VDDA 2 ÁÁÁ 2.5 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ DIPHP-SM |IPHP-SM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Relative output current variation PHP (see Figure 1) ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 10% ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DIPHP-SM ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current matching PHP (see Figure 1) VPHP = 0.5 VDDA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ±300 ÁÁÁ ÁÁÁ mA integral charge pump, speed-up mode, VRF = VDDA (see speed-up mode operation) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PARAMETER TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ |IPHI-SM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output current PHI VPHI = 0.5 VDDA ÁÁÁ ÁÁÁ 4.8 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 7.2 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ DIPHI-SM |IPHI-SM | ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Relative output current variation PHI (see Figure 1) ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ DIPHI-SM Output current matching PHI (see Figure 1) VPHI = 0.5 VDDA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ±600 ÁÁÁ ÁÁÁ mA fractional compensation proportional charge pump, normal mode, VRN = VDDA PARAMETER TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ |IPHP-F-NM | Output current PHP vs fractional numerator (see Note 3) VPHP = 0.5 VDDA , FNUM = 1 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ 1.25 ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ mA NOTE: 3. Fractional compensation current is proportional to the numerator content of the fractional accumulator (FNUM). charge pump leakage currents, VRN = VRA = VRF = VDDA PARAMETER ÁÁÁÁÁÁ ÁÁÁÁÁÁ TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ IPHP Output current PHP ÁÁÁÁÁÁ ÁÁÁÁÁÁ VPHP = 0.5 VDDA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ±10 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ IPHI Output current PHI ÁÁÁÁÁÁ VPHI = 0.5 VDDA ÁÁÁ ÁÁÁ ±10 ÁÁÁ ÁÁÁ nA ÁÁÁÁ ÁÁÁÁ IPHA Output current PHA ÁÁÁÁÁÁ ÁÁÁÁÁÁ VPHA = 0.5 VDDA ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ±10 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ac electrical characteristics, VDD = VCCP = 2.9 V, VDDA = 3.9 V, TA = 25°C (unless otherwise noted) main divider PARAMETER TEST CONDITIONS ÁÁÁ MIN ÁÁÁ TYP ÁÁÁ MAX ÁÁÁ UNIT ÁÁÁÁ ÁÁÁÁ fRFIN RF input frequency ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 1.2 ÁÁÁ ÁÁÁ GHz ÁÁÁÁ ÁÁÁÁ VID_RFIN Differential RF input power50- single-ended characteristic impedance; ac-coupled ÁÁÁ ÁÁÁ –20 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ dBm

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ac electrical characteristics, VDD = VCCP = 2.9 V, VDDA = 3.9 V, TA = 25°C (unless otherwise noted) (continued) auxiliary divider PARAMETER TEST CONDITIONS ÁÁÁ MIN ÁÁÁ TYP ÁÁÁ MAX ÁÁÁ UNIT ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ fAUXIN Auxiliary input frequency (ac-coupled) PA = 1: VI_AUXIN = 350 mVpp ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ ÁÁÁ Á Á Á ÁÁÁ MHz ÁÁÁÁÁ ÁÁÁÁÁ ZAUXIN Auxiliary input impedance ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 100 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ kW ÁÁÁÁÁ ÁÁÁÁÁ ZAUXIN Auxiliary input impedance ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ pF reference divider PARAMETER TEST CONDITIONS ÁÁÁ ÁÁÁ MIN ÁÁÁ ÁÁÁ TYP ÁÁÁ ÁÁÁ MAX ÁÁÁ ÁÁÁ UNIT ÁÁÁÁÁ ÁÁÁÁÁ fREFIN Reference input frequency ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 16.8 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ MHz ÁÁÁÁÁ ÁÁÁÁÁ VI_REFIN Reference input voltage ac-coupled, 16.8 MHz ÁÁÁ ÁÁÁ 0.350 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ VPP ÁÁÁÁÁ ÁÁÁÁÁ ZREFIN Reference input impedance ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ 100 ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ kW ÁÁÁÁÁ ÁÁÁÁÁ ZREFIN R eference input impe dance ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ pF timing requirements, serial data interface (see Figure 2) MIN MAX UNIT fCLOCK Clock frequency 10 MHz tw_CLKHI Clock high time pulse width, CLOCK high 30 ns tw_CLKLO Clock low time pulse width, CLOCK low 30 ns tsu_Data Setup time, data valid before CLOCK↑ 30 ns th_Data Hold time, data valid after CLOCK↑ 30 ns th_Strobe Hold time, STROBE high before CLOCK↑ 30 ns tsu_Strobe Setup time, STROBE low after CLOCK↑ 30 ns tw_STRBHI STROBE high time pulse width, STROBE high 50 ns

Figure 1. Charge-Pump Output Current Definitions charge-pump sourcing current output at a given charge-pump output (see Figure 1).

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 2. Serial-Data Interface Timing The TRF2056 internal registers are programmed using a three-wire (CLOCK, DATA, STROBE) serial interface. the operational mode of the TRF2056 device: 00 = SA7025 emulation, 01 = EPM. TRF2056 device is operated in the SA7025 emulation mode. synthesizer, four words must be sent: D, C, B, and A. The E-Word is for testing purposes only. synchronization signal is also active. This is done to avoid phase jumps while reprogramming the main divider. The synchronization signal is generated by the main divider. which are located on outputs PHP and PHI, to speed-up mode, as long as STROBE is high. in order to set the mode of operation (SA7025 or EPM).

Figure 3. Serial Word Format for SA7025 Emulation Mode

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 1. SA7025 Emulation Serial-Word-Format Function Listing

4 Binary acceleration factor for integral charge pump current

2 Binary acceleration factor for proportional charge pump current

8 Binary current-setting factor for main charge pumps

1 Auxiliary divider enable flag:

1 Fractional-N modulus selection:

1 A word format selection:

3 Fractional-N increment

12 Number of main divider cycles when prescaler modulus = 64

2 Prescaler type:

Figure 4. Serial Word Format for Extended Performance Mode

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 2. Extended Performance Mode Function

1 Yes

5 No Fraction accumulator modulus

12 Yes Reference divider ratio

2 Yes Reference select for main phase detector

the total division ratio desired (fractional effects are ignored). The N-division ratio has a range of 992 ≤ NTotal ≤ 262143.

5 Bits 13 Bits

Figure 5. Main Divider Organization SA7025 programming codes without change.

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

For contiguous channels, the following rules must be observed: For PR = 01: 61 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 63, which yields minimum and maximum divide ratios of 4032 and 266303, respectively. For PR = 10: 14 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 15, and 0 ≤ NM3 ≤ 15, which yields minimum and maximum divide ratios of 1096 and 264335, respectively. main divider – synchronization The A-Word is loaded only when a main divider synchronization signal is active. This prevents phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider, and it is active while the main divider is counting down from the programmed value. When the main divider reaches its terminal count, a main divider output pulse is sent to the main phase detector. Also at this time, the loading of the A-Word is disabled. Therefore, to correctly load the new A-Word, STROBE must be active high for at least a minimum number of VCO input cycles at RFIN. main divider – fractional accumulator The TRF2056 main synthesizer loop can operate as a traditional integer-N feedback PLL or as a fractional-N feedback PLL. The integer-N feedback loop divides the VCO frequency by integer values of N, which results in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides the VCO frequency by an integer term plus a fractional term, which results in phase detector reference comparisons at integer multiples of the desired system channel spacing. Integer-N division: VCO frequency N = phase detector reference frequency = channel spacing Fractional-N division: VCO frequency (N + NF/FMOD) = phase detector reference frequency = FMOD × channel spacing where 0 ≤ NF < FMOD and 1 ≤ FMOD ≤ 16. Because the main counter and prescaler sections cannot divide by a fraction of an integer, the fractional-N division is accomplished by averaging main divider cycles by N and N+1. A fractional accumulator is programmed with values of NF and FMOD to control the main counter and prescaler sections to divide by N or N+1. The fractional accumulator operates modulo FMOD and is incremented by NF at the completion of each main divider cycle. When the fractional accumulator overflows, division by N+1 occurs. Otherwise, the main counters and prescaler divide by N; division by N+1 is transparent to the user. Table 3 shows the contents of the fractional accumulator and the resulting N or N+1 division for two fractional division ratios.

Table 3. Fractional Accumulator Operation illustrates the division by N or N+1 for this 3/8 fractional channel example. Figure 6. 3/8 Fractional Channel Main Divider Operation

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NF/FMOD. Figure 7 shows the fractional-N phase detector ripple for a 3/8 fractional channel. Figure 7. Fractional-N Phase Detector Ripple for 3/8 Channel under the main PHP charge-pump curve represents the amount of charge delivered to the loop filter network. generated to have equal and opposite sign magnitude area to the main PHP charge pump.

Figure 8. Main PHP and Compensation Charge Pump Fractional-N Waveforms for 3/8 Channel between the main and compensation pulses. fractional-N sidebands based on VCO frequency and reference frequency. The main VCO is locked on channel.

19.44 MHz reference frequency

1. Determine the fundamental fractional-N pulse width portion of the main PHP charge-pump output waveform

for the lower, upper, and mean frequencies.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 4. Main PHP Fractional-N Pulse-Widths and Areas for 3/8 Channel

1. Determine the pulse width of the compensation charge-pump output waveform.
2. Determine the fundamental compensation charge-pump current magnitude using the fundamental main

Table 5 shows the magnitude of the compensation pulse as a function of the fractional accumulator. Table 5. Compensation Pulse Magnitudes for 3/8 Channel

1. Using the result of step 3, determine the value of RF to give the fundamental compensation pulse

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION 1234 5. Determine the values of CN and RN for the main PHP charge-pump peak current of 500 mA. Assume that a midrange value of CN equals 128. RN (k) /C0043/C046618.75 CN 256 1 I(mA )/C0467–0 . 7 5/C0043/C046618.75 128 256 1 0.5 mA/C0467–0 . 7 5/C004318 k 6. The values of the fundamental compensation pulse magnitude calculated in step 3 and the compensation pulse width calculated in step 2 are fixed. However, because the VCO can tune over a significant range of frequencies, the pulse width of the fractional-N portion of the main PHP charge-pump waveform varies; thus, the area of the same waveform varies. In order to maintain equal areas under the fractional-N portion of the main PHP charge-pump and compensation waveforms, CN must vary with the VCO frequency. As the VCO frequency increases, the fractional-N portion of the main PHP charge-pump waveform pulse width decreases proportionally, thereby decreasing the area under the same waveform. Therefore, CN is adjusted to equalize the main PHP and compensation waveform areas, as follows: Frac PW-LWR = 132.557 ps for fVCO = 942.99 MHz FracPW-UPR = 129.815 ps for fVCO = 962.91 MHz The fundamental area of the fractional-N portion of the main PHP charge-pump waveform (step 1) is calculated as 0.065593 ps-A. If you calculate the fundamental area of the fractional-N portion of the main PHP charge-pump waveform using the actual pulse widths above in place of the average pulse width calculated in step 1, the fractional-N main PHP areas are obtained as follows: Frac Area-LWR = (132.557 ps) (0.500 mA) = 0.066279 (ps-A) FracArea-UPR = (129.815 ps) (0.500 mA) = 0.064908 (ps-A) The actual areas under the fractional-N portion of the main PHP waveform require slight modification in the charge-pump current. The variation of CN required for area equalization is determined using a simple ratio form: CN LWR /C0043 FracArea–AVG CN AVG /C00430.065593 0.066279 128 /C0043126 CN UPR /C0043 FracArea/C0042AVG FracArea/C0042UPR CN AVG /C00430.065593 0.064908 128 /C0043130 FracArea/C0042LPR Therefore, for this example, CN can vary from 126 to 130 over the VCO frequency range of 942.99 MHz to 962.91 MHz for optimum fractional-N sideband suppression. Due to component and circuit tolerances, additional deviations in CN may be appropriate. auxiliary divider The input signal on AUXIN is amplified by a single-ended, ac-coupled input buffer/amplifier that has sufficient sensitivity (200 mVpp at 100 MHz) for direct connection to a typical VCO. The 12-bit (NA) auxiliary divider incorporates a divide by 1 (PA = 1) or divide by 4 (PA = 0) prescaler. The total division ratio can be expressed as: N Total = 4 x NA where PA = 0 N Total = NA, where PA = 1 and NA = 4 to 4095.

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SM and SA, respectively (see Figure 9). Figure 9. Reference Divider detectors (PFD). A PFD has gain with a phase error over a range of ±2p and exhibits an infinite pull-in range. to have a minimum on-time of 1/fRef when the loop is operating in a locked condition. MCP and ACP fields, respectively, in the B-Word (EPM mode).

Figure 10. Main and Auxiliary Phase Detector Circuit resistors achieve desired charge-pump peak currents. Table 6. Charge Pump Current Plans fractional-N sidebands and compensation.

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interface operates independent of the reference input for the loading of serial words. Table 7. Loop Enable/Disable programmable coefficients CN, CL, and CK. REFIN. The LOCK terminal can be polled to determine the synthesizer lock condition of either or both loops. through a 10-kW pull-up resistor. Table 8. Test Modes

/C0084/C0082/C0070 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0262/C0071/C0072/C0122 /C0070/C0082/C0065/C0067/C0084/C0073/C0079/C0078/C0065/C0076/C0262/C0078/C0073/C0078/C0084/C0069/C0071/C0069/C0082/C0262/C0078 /C0083/C0089/C0078/C0084/C0072/C0069/C0083/C0073/C0090/C0069/C0082 SLWS111– NOVEMBER 2000 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040064/D 10/95

14 PIN SHOWN

0,10 MIN1,20 MAX A 0,19 4,50 4,30 6,10 6,70 0,32 0,75 0,50 0,25 Gage Plane 0,15 NOM 0,65 M0,13 0°–8° 0,10 PINS ** A MIN A MAX DIM 2,90 3,10 4,90 5,10 6,60 6,404,90 5,10 7,70 7,90 9,60 9,80 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  2000, Texas Instruments Incorporated