TPSM63602V5RDHR.A

Texas Instruments

TPSM63602 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 2-A Power Module With Enhanced HotRod™ QFN Package APRIL 2022

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TPSM63602 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 2-A Power Module With Enhanced HotRod™ QFN Package

1 Features

Versatile synchronous buck DC/DC module – Integrated MOSFETs, inductor, and controller – Wide input voltage range of 3 V to 36 V – Adjustable output voltage from 1 V to 16 V – 4-mm × 6-mm × 1.8-mm overmolded package – –40°C to 125°C junction temperature range – Frequency adjustable from 200 kHz to 2.2 MHz using the RT pin or an external SYNC signal – Negative output voltage capability
Ultra-high efficiency across the full load range – 93% peak efficiency at 12 VIN, 5 VOUT, 1 MHz – External bias option for improved efficiency – Shutdown quiescent current of 0.6 µA (typical) – 0.3-V typical dropout voltage at 2-A load
Ultra-low conducted and radiated EMI signatures – Low-noise package with dual input paths and integrated capacitors reduces switch ringing – Resistor-adjustable switch-node slew rate – Constant-frequency FPWM mode of operation – Meets CISPR 11 and 32 class B emissions
Suitable for scalable power supplies – Pin compatible with the TPSM63603 (36 V, 3 A)
Inherent protection features for robust design – Precision enable input and open-drain PGOOD indicator for sequencing, control, and VIN UVLO – Overcurrent and thermal shutdown protections
Create a custom design using the TPSM63602 with the WEBENCH® Power Designer

2 Applications

Test and measurement, aerospace and defense
Factory automation and control
Buckand inverting buck-boost power supplies

3 Description

The TPSM63602 synchronous buck power module is a highly integrated 36-V, 2-A DC/DC solution that combines power MOSFETs, a shielded inductor, and passives in an Enhanced HotRod™ QFN package. The module has pins for VIN and VOUT located at the corners of the package for optimized input and output capacitor layout placement. Four larger thermal pads beneath the module enable a simple layout and easy handling in manufacturing. With an output voltage from 1 V to 16 V , the TPSM63602 is designed to quickly and easily implement a low-EMI design in a small PCB footprint. The total solution requires as few as four external components and eliminates the magnetics and compensation part selection from the design process. Although designed for small size and simplicity in space-constrained applications, the TPSM63602 module offers many features for robust performance: precision enable with hysteresis for adjustable input- voltage UVLO, resistor-programmable switch node slew rate for improved EMI, integrated VCC, bootstrap and input capacitors for increased reliability and higher density, constant switching frequency over the full load current range for enhanced load transient performance, and a PGOOD indicator for sequencing, fault protection, and output voltage monitoring. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) TPSM63602 B0QFN (30) 4.0 mm × 6.0 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space PG EN/SYNC RT PGND AGND VOUT FB VLDOIN VIN COUT RFBB TPSM63602 RRT IOUT(max) = 2 A VIN = 3 V...36 V VCC VOUT = 5 V CIN CBOOT RBOOT RFBT * VOUT enters dropout if VIN < 5.4 V CVCC Typical Schematic Output Current (A) Efficiency (%) 100 VIN = 12 V VIN = 24 V VIN = 36 V Typical Efficiency, VOUT = 5 V, fSW = 1 MHz TPSM63602 SLVSGK8 – APRIL 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

7.8 Typical Characteristics — 2-A Device (VIN = 12 V)... 11 7.9 Typical Characteristics — 2-A Device (VIN = 24 V)...12

7.10 Typical Characteristics — 2-A Device (VIN = 36

12.3 Receiving Notification of Documentation Updates..35

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES April 2022 * Initial Release TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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5 Device Comparison Table

Spectrum Output Voltage External Sync Junction Temperature TPSM63602 TPSM63602RDHR FPWM No Adjustable Yes –40°C to 125°C TPSM63602V3 TPSM63602V3RDHR FPWM No Fixed 3.3 V Yes –40°C to 125°C TPSM63602V5 TPSM63602V5RDHR FPWM No Fixed 5 V Yes –40°C to 125°C

6 Pin Configuration and Functions

Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. RT 1 I Frequency setting pin. This analog pin is used to set the switching frequency between 200 kHz and 2.2 MHz by placing an external resistor from this pin to AGND. Do not leave this pin open or connect this pin to ground. EN/SYNC 2 I Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. It also functions as the synchronization input pin. Used to synchronize the device switching frequency to a system clock. Triggers on the rising edge of an external clock. A capacitor can be used to AC couple the synchronization signal to this pin. The module can be turned off by using an open-drain or collector device to connect this pin to AGND. An external voltage divider can be placed between this pin, AGND, and VIN to create an external UVLO. VIN 3, 4, 18, 19 P Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device. Refer to Section 11.2 for input capacitor placement example. PGND 5, 6, 16, 17, 28, G Power ground. This is the return current path for the power stage of the device. Connect this pad to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout. VOUT 7–10, 12–15, P Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND. SW 11 O Switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI. CBOOT 20 I/O Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. This pin is brought out to use in conjunction with RBOOT to effectively lower the value of the internal RBOOT resistor to adjust the SW node slew rate, if necessary. RBOOT 21 I/O External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected between this pin and the CBOOT pin. This pin is brought out to use in conjunction with CBOOT to effectively lower the value of the internal RBOOT resistor to adjust the switch node slew rate, if necessary. VLDOIN 22 P Input bias voltage. Supplies the control circuitry of the power module. Input to internal LDO. Connect to an output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to ground. VCC 23 O Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high-quality 1-μF ceramic capacitor from this pin to PGND. AGND 24, 27 G Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. This pin must be connected to PGND at a single point. See Section 11.2 for a recommended layout. FB 25 I Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See Section 11.2 for a feedback resistor placement. For a fixed output version, connect this pin directly to output capacitor. Do not leave open or connect to ground. PG 26 O Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup voltage. If not used, this pin can be left open or connected to PGND. (1) P = Power, G = Ground, I = Input, O = Output, NC = No connect TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

Limits apply over TJ = –40°C to 125°C (unless otherwise noted). (1) MIN MAX UNIT Input voltage VIN to AGND, PGND –0.3 40 V RBOOT to SW –0.3 5.5 CBOOT to SW –0.3 5.5 VLDOIN to AGND, PGND –0.3 16 EN/SYNC to AGND, PGND –0.3 40 RT to AGND, PGND –0.3 5.5 FB to AGND, PGND –0.3 16 PG to AGND, PGND 0 20 PGND to AGND –1 2 Output voltage VCC to AGND, PGND –0.3 5.5 VSW to AGND, PGND(2) –0.3 40 VOUT to AGND, PGND –0.3 16 Input current PG — 10 mA TJ Junction temperature –40 125 °C TA Ambient temperature –40 105 °C Tstg Storage temperature –55 150 °C Peak reflow case temperature 260 °C Maximum number of reflows allowed 3 Mechanical shock Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted 1500 G Mechanical vibration Mil-STD-883D, Method 2007.2, 20 to 2000 Hz 20 G (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM63602

7.3 Recommended Operating Conditions

Limits apply over TJ = –40°C to 125°C (unless otherwise noted). MIN NOM MAX UNIT Input voltage VIN (Input voltage range after start-up) 3 36 V Input voltage VLDOIN 12 V Output voltage VOUT(1) 1 16 V Output voltage VOUT(1) TPSM63602V3 3.3 V Output voltage VOUT(1) TPSM63602V5 5 V Output current IOUT(2) 0 2 A Frequency fSW set by RT or SYNC 200 2200 kHz Input current PG 2 mA Output voltage PG 0 16 V TJ Operating junction temperature –40 125 °C TA Operating ambient temperature –40 105 °C (1) Under no conditions should the output voltage be allowed to fall below 0 V. (2) Maximum continuous DC current may be derated when operating with high switching frequency, high ambient temperature, or both. Refer to the Typical Characteristics section for details.

7.4 Thermal Information

THERMAL METRIC(1) RDH (QFN) UNIT

30 PINS

RθJA Junction-to-ambient thermal resistance (TPSM63603 EVM) 29.1 °C/W RθJA Junction-to-ambient thermal resistance(2) 33.5 °C/W ψJT Junction-to-top characterization parameter(3) 4.1 °C/W ψJB Junction-to-board characterization parameter(4) 21.5 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 64-mm × 83-mm four-layer PCB with 2-oz. copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information see the Layout section. (3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1 mm from the device. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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7.5 Electrical Characteristics

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, fSW = 800 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE VIN Input operating voltage range Needed to start up (over IOUT range) 3.95 36 V Once operating (over IOUT range) 3 36 V VIN_HYS Hysteresis(1) 1.0 V IQ_VIN Input operating quiescent current (non-switching) TA = 25°C, VEN/SYNC = 3.3 V, VFB = 1.5 V 4 µA ISDN_VIN VIN shutdown quiescent current VEN/SYNC = 0 V, TA = 25°C 3 µA ENABLE VEN_RISE EN voltage rising threshold 1.161 1.263 1.365 V VEN_FALL EN voltage falling threshold 0.91 V VEN_HYS EN voltage hysteresis 0.275 0.353 0.404 V VEN_WAKE EN wake-up threshold 0.4 V IEN Input current into EN/SYNC (non-switching) VEN/SYNC = 3.3 V, VFB = 1.5 V 1.65 µA tEN EN HIGH to start of switching delay(1) 0.7 ms INTERNAL LDO VCC VCC Internal LDO VCC output voltage 3.4 V ≤ VLDOIN ≤ 12.5 V 3.3 V VLDOIN = 3.1 V, non-switching 3.1 V VCC_UVLO VCC UVLO rising threshold VLDOIN < 3.1 V(1) 3.6 V VIN < 3.6 V(2) 3.6 V VCC_UVLO_HYS VCC UVLO hysteresis(2) Hysteresis below VCC_UVLO 1.1 V IVLDOIN Input current into VLDOIN pin (non-switching, maximum at TA = 125°C)(3) VEN/SYNC = 3.3 V, VFB = 1.5 V 25 31.2 µA FEEDBACK VOUT Adjustable output voltage range (TPSM63602) Over the IOUT range 1 16 V Fixed output voltage (TPSM63602V3) 3.3 V Fixed output voltage (TPSM63602V5) 5.0 V VFB Feedback voltage TA = 25°C, IOUT = 0 A 1.0 V VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, fSW = 200 kHz –1% +1% VFB Load regulation TA = 25°C, 0 A ≤ IOUT ≤ 3 A 0.1% VFB Line regulation TA = 25°C, IOUT = 0 A, 4.0 V ≤ VIN ≤ 36 V 0.1% IFB Input current into the FB pin VFB = 1.0 V 10 nA CURRENT IOUT Output current TA = 25°C 0 2.0 A IOCL Output overcurrent (DC) limit threshold 3.8 A IL_HS High-side switch current limit Duty cycle approaches 0% 4.48 4.87 5.32 A IL_LS Low-side switch current limit 2.07 2.4 2.80 A IL_NEG Negative current limit –3 A VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40% tW Short circuit wait time ("hiccup" time before soft start) (1) 80 ms SOFT START tSS Time from first SW pulse to VREF at 90% VIN ≥ 4.2 V 3.5 5 7 ms tSS2 Time from first SW pulse to release of FPWM lockout if the output not in regulation(1) VIN ≥ 4.2 V 9.5 13 17 ms www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM63602

7.5 Electrical Characteristics (continued)

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, fSW = 800 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD PGOV PG upper threshold — rising % of VOUT setting 105% 107% 110% PGUV PG lower threshold — falling % of VOUT setting 92% 94% 96.5% PGHYS PG upper threshold hysteresis (rising and falling) % of VOUT setting 1.3% VIN_PG_VALID Input voltage for valid PG output 46-μA pullup, VEN/SYNC = 0 V 1.0 V VPG_LOW Low level PG function output voltage 2-mA pullup to the PG pin, VEN/SYNC = 3.3 V 0.4 V IPG Input current into the PG pin when open-drain output is high VPG = 3.3 V 10 nA IOV Pulldown current at the SW node under overvoltage condition 0.5 mA tPG_FLT_RISE Delay time to PG high signal 1.5 2.0 2.5 ms tPG_FLT_FALL Glitch filter time constant for PG function 120 µs SWITCHING FREQUENCY fSW_RANGE Switching frequency range by RT or SYNC 200 2200 kHz fSW_RT1 Default switching frequency by RT RRT = 66.5 kΩ 180 200 220 kHz fSW_RT2 Default switching frequency by RT VIN = 12 V, RRT = 5.76 kΩ 1980 2200 2420 kHz SYNCHRONIZATION VEN_SYNC Edge amplitude necessary to sync using EN/SYNC Rise and fall time < 30 ns 2.4 V tB Blanking of EN after rising or falling edges(1) 4 28 µs tSYNC_EDGE Enable sync signal hold time after edge for edge recognition(1) 100 ns POWER STAGE VBOOT_UVLO Voltage on CBOOT pin compared to SW which will turn off high-side switch 2.1 V tON_MIN Minimum ON pulse width(1) VOUT = 1 V, IOUT = 1 A, RBOOT shorted to CBOOT 55 70 ns tON_MAX Maximum ON pulse width(1) 9 µs tOFF_MIN Minimum OFF pulse width VIN = 4 V, IOUT = 1 A, RBOOT shorted to CBOOT 65 85 ns THERMAL SHUTDOWN TSDN Thermal shutdown threshold (1) Temperature rising 158 168 180 °C THYST Thermal shutdown hysteresis(1) 10 °C (1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested. (2) Production tested with VIN = 3 V. (3) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total input current to the system while regulating. For additional information, reference the Systems Characteristics and the Input Supply Current sections. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IIN Input supply current when in regulation VIN = 24 V, VOUT = 3.3 V, VEN/SYNC = VIN, VVLDOIN = VOUT, fSW = 800 kHz, IOUT = 0 A 10 mA OUTPUT VOLTAGE VFB Load regulation VOUT = 3.3 V, VIN = 24 V, IOUT = 0.1 A to full load 1 mV VFB Line regulation VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 3 A 6 mV VOUT Load transient VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A at 2 A/μs, COUT(derated) = 49 μF 50 mV EFFICIENCY η Efficiency VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 800 kHz 89.5% VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 800 kHz 87.5% VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 1 MHz 91% VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, fSW = 1 MHz 88.1% VOUT = 12 V, VIN = 24 V, IOUT = 1.5 A, VLDOIN = VOUT, fSW = 2 MHz 94.1% www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM63602

7.7 Typical Characteristics

VIN = 24 V, unless otherwise specified Input Voltage (V) Shutdown Current (  A) 0 6 12 18 24 30 36 T J = -55  C T J = 25  C T J = 125  C VEN/SYNC = 0 V Figure 7-1. Shutdown Supply Current Junction Temperature ( C) Feedback Voltage (V) -55 -35 -15 5 25 45 65 85 105 125 0.99 0.995 1.005 1.01 V IN = 3.3V V IN = 36V Figure 7-2. Feedback Voltage Frequency (kHz) RT Resistance (k  ) 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 Figure 7-3. Switching Frequency Set by the RT Resistor Junction Temperature (  C) MOSFET R DS(on) (m  ) -55 -35 -15 5 25 45 65 85 105 125 High-side MOSFET Low-side MOSFET Figure 7-4. High-Side and Low-Side MOSFET RDS(on) Junction Temperature (  C) Enable Threshold Voltage (V) -55 -35 -15 5 25 45 65 85 105 125 0.2 0.4 0.6 0.8 1.2 1.4 V EN Rising V EN Falling V EN_WAKE Rising V EN_WAKE Falling Figure 7-5. Enable Thresholds Junction Temperature (  C) PG Threshold (%) -55 -35 -15 5 25 45 65 85 105 125 100 105 110 115 OV Tripping OV Recovery UV Recovery UV Tripping Figure 7-6. Power-Good (PG) Thresholds TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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7.8 Typical Characteristics — 2-A Device (VIN = 12 V)

Refer to Section 9.2 for circuit designs. Output Current (A) Efficiency (%) 100 VOUT, FSW 5.0 V, 1.0 MHz

3.3 V, 800 kHz

2.5 V, 750 kHz

1.8 V, 600 kHz

VLDOIN = VOUT Figure 7-7. Efficiency Output Current (A) Power Dissipation (W) 0.0 0.3 0.6 0.9 1.2 VOUT, FSW 5.0 V, 1.0 MHz VLDOIN = VOUT Figure 7-8. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT, FSW 5.0 V, 1.0 MHz COUT = 2 × 47-µF ceramic, 25-V, 1206 case size Figure 7-9. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow Nat Conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-10. Safe Operating Area (All VOUT) www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSM63602

7.9 Typical Characteristics — 2-A Device (VIN = 24 V)

Refer to Section 9.2 for circuit designs. Output Current (A) Efficiency (%) 100 VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz VLDOIN = VOUT Figure 7-11. Efficiency Output Current (A) Power Dissipation (W) 0.0 0.4 0.8 1.2 1.6 2.0 VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz VLDOIN = VOUT Figure 7-12. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz COUT = 2 × 47-µF ceramic, 25-V, 1206 case size Figure 7-13. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-14. Safe Operating Area (VOUT = 3.3 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-15. Safe Operating Area (VOUT = 5.0 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-16. Safe Operating Area (VOUT = 12 V) TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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7.10 Typical Characteristics — 2-A Device (VIN = 36 V)

Refer to Section 9.2 for circuit designs. Output Current (A) Efficiency (%) 100 VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz VLDOIN = VOUT Figure 7-17. Efficiency Output Current (A) Power Dissipation (W) 0.0 0.5 1.0 1.5 2.0 2.5 VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz VLDOIN = VOUT Figure 7-18. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT, FSW 12 V, 2.0 MHz 5.0 V, 1.0 MHz COUT = 2 × 47-µF ceramic, 25-V, 1206 case size Figure 7-19. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-20. Safe Operating Area (VOUT = 3.3 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-21. Safe Operating Area (VOUT = 5.0 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv The device is soldered to a 64-mm × 83-mm, 4-layer PCB. Figure 7-22. Safe Operating Area (VOUT = 12 V) www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM63602

8 Detailed Description

8.1 Overview

The TPSM63602 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, and 24-V supply rails. With an integrated power controller, inductor, and MOSFETs, the TPSM63602 delivers up to 3-A DC load current with high efficiency and ultra-low input quiescent current in a very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop compensation is not required, reducing design time and external component count. With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal , the TPSM63602 incorporates specific features to improve EMI performance in noise-sensitive applications:

An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch- voltage ringing, and radiated field coupling.
Clock synchronization and FPWM mode enable constant switching frequency across the load current range.
Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching.
Adjustable switch-node slew rate allows optimization of EMI at higher frequency harmonics. The TPSM63602 module also includes inherent protection features for robust system requirements:
An open-drain PGOOD indicator for power-rail sequencing and fault reporting
Precision enable input with hysteresis, providing: – Programmable line undervoltage lockout (UVLO) – Remote ON and OFF capability
Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
Thermal shutdown with automatic recovery These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for a simple layout, requiring few external components. See Section 11 for a layout example.

8.2 Functional Block Diagram

2.2 µH SW RBOOT VIN 100 SYNC detect RT VLDOIN OTP EN OTP OCP UVLO IOUT(max) = 2 A VIN = 3 V to 36 V Optional external bias (from VOUT) VOUT = 1 V to 16 V PGOOD indicator RENT RENB Precision enable for VIN UVLO RRT RFBB RFBT To VOUT sense point VIN Adjustable output variant only CVCC TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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8.3 Feature Description

8.3.1 Input Voltage Range

With a steady-state input voltage range from 3 V to 36 V, the TPSM63602 module is intended for step-down conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in Figure 8-1 shows all the necessary components to implement a TPSM63602-based buck regulator using a single input supply. PG EN/SYNC RT PGND AGND VOUT FB VLDOIN VIN PGND VIN CIN2 COUT RFBB TPSM63602 RRT IOUT(max) = 2 A VIN = 3 to 36 V RENT RENB CSYNC SYNC optional Optional external bias Precision Enable UVLO Optional synchronization RPG VCC PGOOD indicator VOUT = 1 to 16 V CIN1 VOUT CBOOT RBOOT 1 nF RFBT PGND CVCC Figure 8-1. TPSM63602 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V Take extra care to make sure that the voltage at the VIN pins does not exceed the absolute maximum voltage rating of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum ratings can damage the IC.

8.3.2 Adjustable Output Voltage (FB)

The TPSM63602 has an adjustable output voltage range of 1 V to 16 V. Setting the output voltage requires two resistors, RFBT and RFBB (see Figure 8-2). Connect RFBT between VOUT, at the regulation point, and the FB pin. Connect RFBB between the FB pin and AGND (pin 10). The recommended value of R FBB is 10 kΩ. The value for RFBT can be calculated using Equation 1. Table 8-1 lists the standard resistor values for several output voltages and the recommended switching frequency. The minimum required output capacitance for each output voltage is also included in Table 8-1. The capacitance values listed represent the effective capacitance, taking into account the effects of DC bias and temperature variation. (1) www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM63602

10 kΩ Figure 8-2. FB Resistor Divider Table 8-1. Standard RFBT Values, Recommended fSW and Minimum COUT VOUT (V) RFBT (kΩ)(1) Recommended fSW (kHz) COUT(MIN) (µF) (Effective) VOUT (V) RFBT (kΩ)(1) Recommended fSW (kHz) COUT(MIN) (µF) (Effective) 1.0 Short 400 300 3.3 23.2 800 40 1.2 2 500 200 5.0 40.2 1000 25 1.5 4.99 500 160 7.5 64.9 1300 20 1.8 8.06 600 120 10 90.9 1500 15 2.0 10 600 100 12 110 2000 5 2.5 15 750 65 15 140 2200 4 3.0 20 750 50 16 150 2200 3 (1) RFBB = 10 kΩ Note that higher feedback resistances consume less DC current, which is mandatory if light-load efficiency is critical. However, R FBT larger than 1 M Ω is not recommended because the feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful layout of the feedback path. It is important to keep the feedback trace as short as possible while keeping the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Section 11. Fixed Output Voltage Variants The TPSM63602V3 and TPSM63602V5 are the fixed output voltage variants of the module with 3.3-V and 5-V fixed output voltages, respectively. In these variants, the resistor feedback dividers are located internal to the module. Therefore, the FB pin can be connected directly to output voltage regulation point.

8.3.3 Input Capacitors

Input capacitors are required to limit the input ripple voltage to the module due to switching-frequency AC currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. Equation 2 gives the input capacitor RMS current. The highest input capacitor RMS current occurs at D = 0.5, at which point, the RMS current rating of the capacitors must be greater than half the output current. 2 L CIN,rms OUT II D I 1 D 12 © ¹ (2) where TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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D = VOUT / VIN is the module duty cycle. Ideally, the DC and AC components of the input current to the buck stage are provided by the input voltage source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of amplitude (I OUT – I IN) during the D interval and sink I IN during the 1 – D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resulting capacitive component of the AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, Equation 3 gives the peak-to-peak ripple voltage amplitude. OUT IN OUT ESR SW IN I D 1 DV I R F C ' (3) Equation 4 gives the input capacitance required for a particular load current. OUT IN SW IN ESR OUT D 1 D IC F V R I t ' (4) where
ΔVIN is the input voltage ripple specification. The TPSM63602 requires a minimum of 2 × 4.7-µF ceramic type input capacitance. Only use high-quality ceramic type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a low impedance source to the converter in addition to supplying the ripple current and isolating switching noise from other circuits. Additional capacitance can be required for applications with transient load requirements. The voltage rating of the input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. Table 8-2 includes a preferred list of capacitors by vendor. Table 8-2. Recommended Input Capacitors Vendor(1) Dielectric Part Number Case Size Capacitor Characteristics Voltage Rating (V) Capacitance (µF)(2) TDK X7R C3216X7R1H475K160AC 1206 50 4.7 Murata X7R GRM31CR71H475KA12L 1206 50 4.7 TDK X7R CGA6P3X7R1H475K250AB 1210 50 4.7 Murata X7S GCM31CC71H475KA03L 1206 50 4.7 (1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer. (2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature.)

8.3.4 Output Capacitors

Table 8-1 lists the TPSM63602 minimum amount of required output capacitance. The effects of DC bias and temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contribute to differences between the standard rated value and the actual effective value of the capacitance. When adding additional capacitance above C OUT(MIN), the capacitance can be ceramic type, low-ESR polymer type, or a combination of the two. See Table 8-3 for a preferred list of output capacitors by vendor. Table 8-3. Recommended Output Capacitors Vendor(1) Temperature Coefficient Part Number Case Size Capacitor Characteristics Voltage (V) Capacitance (µF)(2) TDK X7R CGA5L1X7R1C106K160AC 1206 16 10 Murata X7R GCM31CR71C106KA64L 1206 16 10 TDK X7R C3216X7R1E106K160AB 1206 25 10 Murata X7S GCJ31CC71E106KA15L 1206 25 10 www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM63602

Table 8-3. Recommended Output Capacitors (continued) Vendor(1) Temperature Coefficient Part Number Case Size Capacitor Characteristics Voltage (V) Capacitance (µF)(2) Murata X6S GRM31CC81E226K 1206 25 22 Murata X7R GRM32ER71E226M 1210 25 22 (1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer. (2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature.)

8.3.5 Switching Frequency (RT)

The switching frequency range of the TPSM63602 is 200 kHz to 2.2 MHz. The switching frequency can easily be set by connecting a resistor (R RT) between the RT pin and AGND. Use Equation 5 to calculate the RRT value for a desired frequency or simply select from Table 8-4. Note that a resistor value outside of the recommended range can cause the device to shut down. This prevents unintended operation if the RT pin is shorted to ground or left open. Do not apply a pulsed signal to this pin to force synchronization. The switching frequency must be selected based on the output voltage setting of the device. See Table 8-4 for RRT resistor values and the allowable output voltage range for a given switching frequency for common input voltages. (5) Table 8-4. Switching Frequency Versus Output Voltage (IOUT = A) FSW (kHz) RRT (kΩ) VIN = 5 V VIN = 12 V VIN = 24 V VIN = 36 V VOUT Range (V) VOUT Range (V) VOUT Range (V) VOUT Range (V) Min Max Min Max Min Max Min Max TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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8.3.6 Output ON and OFF Enable (EN/SYNC) and VIN UVLO

The EN/SYNC pin provides precision ON and OFF control for the TPSM63602. Once the EN/SYNC pin voltage exceeds the threshold voltage and V IN is above the minimum turn-on threshold, the device starts operation. The simplest way to enable the TPSM63602 is to connect EN/SYNC directly to VIN, allowing the TPSM63602 to start up when V IN is within its valid operating range. However, many applications benefit from the employment of an enable divider network as shown in Figure 8-3, which establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of deep discharge of a battery power source. An external logic signal can also be used to drive the enable input to toggle the output on and off and for system sequencing or protection. EN/SYNC VIN RENT AGND VIN RENB Figure 8-3. VIN UVLO Using the EN/SYNC Pin RENB can be calculated using Equation 6. (6) where

RENT is 100 kΩ (typical).
VEN is 1.263 V (typical).
VIN(ON) is the desired start-up input voltage. Note The EN/SYNC pin can also be used as an external synchronization clock input. See Section 8.3.7 for additional information. A blanking time of 4 µs to 28 µs is applied to the enable logic after a clock edge is detected. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM63602

8.3.7 Frequency Synchronization (EN/SYNC)

The TPSM63602 can be synchronized to an external clock using the EN/SYNC pin. The synchronization frequency range is 200 kHz to 2.2 MHz. The internal oscillator can be synchronized by AC coupling a positive clock edge into the EN/SYNC pin, as shown in Figure 8-4. It is recommended to keep the parallel combination value of R ENT and R ENB in the 100-k Ω range. R ENT is required for synchronization, but R ENB can be left open. The external clock must be off before start-up to allow proper start-up sequencing. After a valid synchronization signal is applied for 2048 cycles, the clock frequency changes to that of the applied signal. RENT RENB EN/SYNC AGND VIN CSYNC AGND Clock Source Figure 8-4. Typical Synchronization Using the EN/SYNC Pin Referring to Figure 8-5, the AC-coupled voltage edge at the EN/SYNC pin must exceed the SYNC amplitude threshold, VEN_SYNC, of 2.4 V to trip the internal synchronization pulse detector. In addition, the minimum EN/ SYNC rising pulse and falling pulse durations must be longer than the SYNC signal hold time, t SYNC_EDGE, of 100 ns and shorter than the minimum blanking time, tB. A 3.3-V or higher amplitude pulse signal coupled through a 1-nF capacitor, CSYNC, is suggested. VEN EN Voltage VEN_SYNC tSYNC_EDGE Time tSYNC_EDGE VEN_SYNC Figure 8-5. Typical SYNC Waveform

8.3.8 Power-Good Monitor (PG)

The TPSM63602 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. The PGOOD pin voltage goes low when the feedback voltage is outside of the PGOOD thresholds. This occurs during the following:

While the device is disabled
In current limit
In thermal shutdown
During normal start-up, when the output voltage has not reach its regulation value A glitch filter prevents false flag operation for short excursions (< 120 µs typical) of the output voltage, such as during line and load transients. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 20 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is above 1 V (typical). Use the PG signal for start-up sequencing of downstream regulators, as shown in Figure 8-6, or for fault protection and output monitoring. 10FB

14 EN/SYNC

VOUT1 = 5 V RFB1 RFB2 40.2 k 10 k

1 V 10FB

23.2 k 10 k 1 V VOUT2 = 3.3 V VIN(on) = 13.9 V VIN(off) = 10 V Regulator #1 Start-up based on input voltage UVLO Regulator #2 Sequential start-up based on PG PG 13 PG 13 RUV2 100 k EN/SYNC Figure 8-6. TPSM63602 Sequencing Implementation Using PG and EN/SYNC

8.3.9 Adjustable Switch-Node Slew Rate (RBOOT and CBOOT)

Adjust the switch-node slew rate of the TPSM63602 to slow the switch-node voltage rise time and improve EMI performance at high frequencies. However, slowing the rise time decreases efficiency. Take care to balance the improved EMI versus the decreased efficiency. Internal to the device, a 100- Ω bootstrap resistor is connected between the RBOOT and CBOOT pins as shown in Figure 8-7. Leaving these pins open incorporates the 100- Ω resistor into the BOOT circuit, slowing the SW voltage slew rate and optimizing EMI. However, if improved EMI is not required, connecting RBOOT to CBOOT shorts the internal resistor, resulting in higher efficiency. Placing a resistor across RBOOT and CBOOT allows adjustment of the internal resistor to balance EMI and efficiency.

3 CBOOT

100 Ω Power MOSFET gate drivers RBOOT4 C BOOT 100 nF R BOOT VCC C VCC 1 µF Figure 8-7. Internal BOOT Resistor

8.3.10 Internal LDO, VCC Output, and VLDOIN Input

The TPSM63602 has an internal LDO to power internal circuitry. The VCC pin is the output of the internal LDO. This pin must not be used to power external circuitry. Connect a high-quality, 1- μF capacitor from this pin to AGND, close to the device pins. Do not load the VCC pin or short it to ground. The VLDOIN pin is an optional input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF capacitor from this pin to ground for improved noise immunity. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM63602

The LDO generates the VCC voltage from one of the two inputs: V IN or the VLDOIN input. When VLDOIN is tied to ground or below 3.1 V, the LDO is powered from VIN. When VLDOIN is tied to a voltage higher than 3.1 V, the LDO input is powered from VLDOIN. VLDOIN voltage must be lower than both VIN and 12.5 V. The VLDOIN input is designed to reduce the LDO power loss. The LDO power loss is: PLDO-LOSS = ILDO × (VIN_LDO – VVCC) (7) The higher the difference between the input and output voltages of the LDO, the more loss occurs to supply the same LDO output current. The VLDOIN input provides an option to supply the LDO with a lower voltage than VIN, to reduce the difference of the input and output voltages of the LDO, and reduce power loss. For example, if the LDO current were 10 mA at a certain frequency with V IN = 24 V and VOUT = 5 V. The LDO loss with VLDOIN tied to ground is: 10 mA × (24 V – 3.3 V) = 207 mW (8) The loss with VLDOIN tied to VOUT (5 V) is: 10 mA × (5 V – 3.3 V) = 17 mW (9) The efficiency improvement is more significant at light and mid loads because the LDO loss is a higher percentage of the total loss. The improvement is more significant with higher switching frequency because the LDO current is higher at higher switching frequency. The improvement is more significant when V IN » V OUT because the voltage difference is higher. Figure 8-8 and Figure 8-9 show typical efficiency waveforms with VLDOIN powered by different input voltages. Output Current (A) Efficiency (%) 0 0.5 1 1.5 2 100 VLDOIN 3.3V GND VIN = 24 V VOUT = 5 V fSW = 1 MHz ILDO = 10 mA Figure 8-8. Efficiency Improvements with VLDOIN (VOUT = 5 V) TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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Output Current (A) Efficiency (%) 0 0.5 1 1.5 2 2.5 3 100 VLDOIN 3.3V 12V GND VIN = 24 V VOUT = 12 V fSW = 2 MHz ILDO = 20 mA Figure 8-9. Efficiency Improvements with VLDOIN (VOUT = 12 V)

8.3.11 Overcurrent Protection (OCP)

The TPSM63602 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak inductor current. The current is compared every switching cycle to the current limit threshold. During an overcurrent condition, the output voltage decreases. The TPSM63602 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode, the regulator is shut down and kept off for 80 ms (typical) before the TPSM63602 tries to start again. If an overcurrent or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions and prevents overheating and potential damage to the device. Once the fault is removed, the module automatically recovers and returns to normal operation.

8.3.12 Thermal Shutdown

Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the TPSM63602 attempts to restart when the junction temperature falls to 158°C (typical).

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN/SYNC pin provides ON and OFF control for the TPSM63602. When VEN/SYNC is below approximately 0.4 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The input quiescent current in shutdown mode drops to 0.6 µA (typical). The TPSM63602 also employs internal undervoltage protection. If the input voltage is below its UV threshold, the regulator remains off.

8.4.2 Standby Mode

The internal LDO has a lower enable threshold than the regulator itself. When VEN/SYNC is above 1.1 V (maximum) and below the precision enable threshold of 1.263 V (typical), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal V CC is above its UVLO threshold. The switching action and voltage regulation are not enabled until VEN/SYNC rises above the precision enable threshold.

8.4.3 Active Mode

The TPSM63602 is in active mode when V IN and VEN/SYNC are above their relevant thresholds and no fault conditions are present. The simplest way to enable the operation is to connect the EN/SYNC pin to V IN, which allows self-start–up when the applied input voltage exceeds the minimum start-up voltage. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM63602

9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPSM63602 only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. The following section describes the design procedure to configure the TPSM63602 power module. To expedite and streamline the design process, WEBENCH® online software is available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. To expedite and streamline the design process for a TPSM63602-based regulator, a comprehensive TPSM63602 quickstart calculator. As mentioned previously, the TPSM63602 also integrates several optional features to meet system design requirements, including the following:

Precision enable with hysteresis
External adjustable UVLO
Adjustable SW node slew rate
A power-good indicator The following application circuits show the TPSM63602 configuration options suitable for several application use cases. Refer to the TPSM63603EVM User's Guide for more detail.

9.2 Typical Applications

The following designs show sample typical applications and design procedures to implement the TPSM63602.

9.2.1 Design 1 — 2-A Synchronous Buck Regulator for Industrial Applications

Figure 9-1 shows the schematic diagram of a 5-V, 2-A buck regulator with a switching frequency of 1 MHz. The nominal input voltage for the sample design is 24 V. A 13-k Ω RRT resistor sets the free-running switching frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency for this specific application. PG EN/SYNC RT PGND AGND VOUT FB VLDOIN VIN PGND VIN CIN2 COUT RFBB TPSM63602 RRT IOUT(max) = 2 A VIN = 24 V RENT RENB CSYNC SYNC optional Optional external bias VIN(on) = 6 V VIN(off) = 4.3 V Optional synchronization RPG VCC PGOOD indicator VOUT = 5 V CIN1 VOUT CBOOT RBOOT 2 47 F 13 k 10 k 40.2 k 4.7 F4.7 F 100 k 374 k 100 k 1 nF RFBT PGND F CVCC Figure 9-1. Circuit Schematic TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters and follow the design procedures in Section 9.2.1.2. Table 9-1. Design Example Parameters Design Parameter Value Input voltage 24 V Output voltage 5 V Output current 0 A to 2 A Switching frequency 1 MHz Table 9-2 gives the selected buck module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation. Table 9-2. List of Materials for Application Circuit 1 Reference Designator Qty Specification Manufacturer(1) Part Number CIN1, CIN2 2 4.7 µF, 50 V, X7R, 1210, ceramic Taiyo Yuden UMK325B7475KN-TR TDK CGA6P3X7R1H475K250AB 4.7 µF, 100 V, X7S, 1206, ceramic Murata GRM31CC72A475KE11L COUT1, COUT2 2 47 µF, 10 V, X7R, 1210, ceramic Murata GRM32ER71A476ME15L AVX 1210ZC476MAT2A CVCC 1 1 µF, 16 V, X7R, 0603, ceramic Murata GCM188R71C105KA64J 1 µF, 16 V, X5R, 0402, ceramic Taiyo Yuden EMK105BJ105KVHF U1 1 TPSM63602 36-V, 2-A synchronous buck module Texas Instruments TPSM63602RDLR (1) See the Third-Party Products Disclaimer. More generally, the TPSM63602 module is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of output capacitance.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM63602 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.1.2.2 Output Voltage Setpoint

The output voltage of the TPSM63602 device is externally adjustable using a resistor divider. The recommended value of RFBB is 10 kΩ. The value for RFBB can be selected from Table 8-1 or calculated using Equation 10: www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM63602

(10) For the desired output voltage of 5 V, the formula yields a value of 40.2 k Ω. Choose the closest available standard value of 40.2 kΩ for RFBT.

9.2.1.2.3 Switching Frequency Selection

The recommended switching frequency for standard output voltages can be found in Table 8-1. For a 5-V output, the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect a 13.0-k Ω resistor between the RT pin and AGND.

9.2.1.2.4 Input Capacitor Selection

The TPSM63602 requires a minimum input capacitance of 2 × 4.7-µF ceramic type. High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, select two 4.7-µF, 50-V, 1210 case size, ceramic capacitors.

9.2.1.2.5 Output Capacitor Selection

For a 5-V output, the TPSM63602 requires a minimum of 25 µF of effective output capacitance for proper operation (see Table 8-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient load requirements. For this design example, select two 47-µF, 10-V, 1210 case size, ceramic capacitors, which have a total effective capacitance of approximately 48 µF at 5 V.

9.2.1.2.6 Other Connections

Short RBOOT to CBOOT for best efficiency.
Connect VLDOIN to VOUT to improve efficiency.
Place a 1-µF capacitor between the VCC pin and PGND, located near to the device. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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9.2.1.3 Application Curves

Unless otherwise indicated, VIN = 24 V, VOUT = 5 V, IOUT = 2 A), and fSW = 1 MHz VIN (20 V/DIV) PG (5 V/DIV) 2 ms/DIV VOUT (5 V/DIV) EN (5 V/DIV) VIN = 24 V VOUT = 5 V Figure 9-2. Start-Up Waveforms PG (5 V/DIV) 500 µs/DIV VOUT (5 V/DIV) EN (5 V/DIV) VIN (20 V/DIV) VIN = 24 V VOUT = 5 V Figure 9-3. Shutdown Waveforms VOUT (200 mV/DIV) IOUT (2 A/DIV) 50 µs/DIV VIN = 24 V VOUT = 5 V fSW = 1 MHz COUT = 2 × 47 µF Figure 9-4. Load Transient, 0 A to 2 A, 1 A/µs VOUT (200 mV/DIV) IOUT (1 A/DIV) 50 µs/DIV VIN = 24 V VOUT = 5 V fSW = 1 MHz COUT = 2 × 47 µF Figure 9-5. Load Transient, 1 A to 2 A, 1 A/µs VOUT (100 mV/DIV) IOUT (1 A/DIV) 50 µs/DIV 3.3V VIN = 24 V VOUT = 3.3 V fSW = 1 MHz COUT = 2 × 47 µF Figure 9-6. Load Transient, 0 A to 2 A, 1 A/µs VOUT (100 mV/DIV) IOUT (1 A/DIV) 50 µs/DIV 3.3V VIN = 24 V VOUT = 3.3 V fSW = 1 MHz COUT = 2 × 47 µF Figure 9-7. Load Transient, 1 A to 2 A, 1 A/µs www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM63602

Figure 9-8. Thermal Image, VIN = 12 V, VOUT = 3.3 V, fSW = 1 MHz, IOUT = 2 A Figure 9-9. Thermal Image, VIN = 12 V, VOUT = 5 V, fSW = 1 MHz, IOUT = 2 A Figure 9-10. Thermal Image, VIN = 24 V, VOUT = 3.3 V, fSW = 1 MHz, IOUT = 2 A Figure 9-11. Thermal Image, VIN = 24 V, VOUT = 5 V, fSW = 1 MHz, IOUT = 2 A TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

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9.2.2 Design 2 — Inverting Buck-Boost Regulator with a –5-V Output

Figure 9-12 shows the schematic diagram of a –5-V inverting buck-boost regulator with a switching frequency of 1 MHz. The input voltage range for the sample design is 12 V to 24 V. PG EN/SYNC RT PGND AGND VOUT FB VLDOIN VIN PGND VIN CIN2 COUT RFBB TPSM63602 RRT RENT RENB Optional external bias VIN(on) = 8.9 V VCC CIN1 VOUT CBOOT RBOOT 2 47 F 13 k 10 k 40.2 k 4.7 F4.7 F 100 k 604 k RFBT PGND 1 F CVCC VIN = 12 V to 24 V CIN3 10 F VIN+ VIN– –VOUT –VOUT IOUT(max) = –1 A VOUT = –5 V VOUT– –VOUT –VOUT Optional Schottky Diode Figure 9-12. Circuit Schematic

9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-3 as the input parameters and follow the design procedures in Section 9.2.2.2. Table 9-3. Design Example Parameters Design Parameter Value Input voltage 12 to 24 V Output voltage –5 V Output current 0 A to 1 A Switching frequency 1 MHz Table 9-4 gives the selected module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation. Table 9-4. List of Materials for Application Circuit 2 Reference Designator Qty Specification Manufacturer(1) Part Number CIN1, CIN2, CIN3 3 4.7 µF, 50 V, X7R, 1210, ceramic Taiyo Yuden UMK325B7475KN-TR TDK CGA6P3X7R1H475K250AB 4.7 µF, 50 V, X7S, 1206, ceramic Murata GCM31CC71H475KA03K COUT1, COUT2 2 47 µF, 10 V, X7R, 1210, ceramic Murata GRM32ER71A476ME15L AVX 1210ZC476MAT2A CVCC 1 1 µF, 16 V, X7R, 0603, ceramic Murata GCM188R71C105KA64J U1 1 TPSM63602 36-V, 2-A synchronous buck module Texas Instruments TPSM63602RDLR More generally, the TPSM63602 module is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of output capacitance. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPSM63602

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Output Voltage Setpoint

The output voltage of the TPSM63602 device is externally adjustable using a resistor divider. The recommended value of RFBB is 10 kΩ. Calculate the value for RFBT using Equation 11. (11) For the desired output voltage of –5 V, enter the absolute value of 5 V for V OUT in Equation 11. The formula yields a value of 40.2 kΩ. Choose the closest available standard value of 40.2 kΩ for RFBT.

9.2.2.2.2 IBB Maximum Output Current

The achievable output current with an IBB topology using the TPSM63602 is: IOUT(max) = ILDC(max) × (1 – D) (12) where

ILDC(max) = 2 A is the rated current of the module.
D = |VOUT| / (VIN + |VOUT|) is the module duty cycle. Therefore, in the case of VIN = 12 V and VOUT = –5 V, the maximum output current is 1.4 A.

9.2.2.2.3 Switching Frequency Selection

To set the switching frequency to 1 MHz, connect a 13.0-k Ω resistor between the RT pin and AGND pins of the module based on Equation 5.

9.2.2.2.4 Input Capacitor Selection

The TPSM63602 requires a minimum input capacitance of 2 × 4.7-µF ceramic type between the VIN pins and PGND pins as close as possible to the module. High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. In an inverting buck-boost configuration, the maximum voltage between VIN and PGND pin of the module is equal to VIN + |VOUT|. For this design, two 4.7-µF, 50-V, 1210 case size, ceramic capacitors are selected.

9.2.2.2.5 Output Capacitor Selection

The TPSM63602 requires a minimum of 25 µF of effective output capacitance for proper operation. High- quality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient load requirements. For this design example, two 47-µF, 10-V, 1210 case size, ceramic capacitors are used, which have a total effective capacitance of approximately 48 µF at 5 V.

9.2.2.2.6 Other Connections

Short RBOOT to CBOOT and connect VLDOIN to VOUT for the best efficiency. Place a 1-µF capacitor between the VCC pin and PGND, located near to the device. The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it does not appear at low frequency for a –5-V output and has minimal effect on the loop response for this application. In an inverting buck-boost configuration, the input capacitor, C IN, and output capacitor, C OUT, can form an AC capacitive divider during a fast V IN transient or hot-plugged event at the input. This event will result in a positive voltage spike at the output that can disturb the load. In this case, an optional Schottky diode can be installed between –VOUT and GND as shown in Figure 9-12 to clamp the output spike. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

Product Folder Links: TPSM63602

9.2.2.2.7 EMI

The TPSM63602 is compliant with EN55011 radiated emissions. Figure 9-13, Figure 9-14, and Figure 9-15 show typical examples of radiated emission plots for the TPSM63603 , which is in the same family of parts . The graphs include the plots of the antenna in the horizontal and vertical positions. EMI plots were measured using the standard TPSM63603EVM. Figure 9-13. Radiated Emissions, 24-V Input, 5-V Output, 3-A Load Figure 9-14. Radiated Emissions, 24-V Input, 5-V Output, 3-A Load, Spread Spectrum www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPSM63602

Figure 9-15. Radiated Emissions, 24-V Input, 3.3-V Output, 3-A Load

10 Power Supply Recommendations

The TPSM63602 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator circuit. Estimate the average input current with Equation 13. K IN OUTOUT IN V IVI (13) where

η is efficiency. If the module is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can cause false UVLO triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the module and use an electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit configurations. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

Product Folder Links: TPSM63602

11 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal thermal performance, and minimal generation of unwanted EMI.

11.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:

Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
Place ceramic input and output capacitors close to the device pins to minimize high-frequency noise.
Locate additional output capacitors between the ceramic capacitors and the load.
Connect AGND to PGND at a single point.
Place RFBT and RFBB as close as possible to the FB pin.
Use multiple vias to connect the power planes to internal layers.

11.2 Layout Example

Figure 11-1. Typical Top-Layer Layout Figure 11-2. Typical Top Layer

11.2.1 Package Specifications

Table 11-1. Package Specifications Table TPSM63602 Value Unit Weight 123 mg Flammability Meets UL 94 V-0 MTBF calculated reliability Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 84 MHrs www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPSM63602

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

With an input operating voltage from 3 V to 36 V and rated output current from 2 A to 6 A, the TPSM63602, TPSM63603, TPSM63604, and TPSM63606 family of synchronous buck power modules specified in Table 12-1 provides flexibility, scalability and optimized solution size for a range of applications. These modules enable DC/DC solutions with high density, low EMI and increased flexibility. Available EMI mitigation features include pseudo-random spread spectrum (PRSS), RBOOT-configured switch-node slew rate control, and integrated input bypass capacitors. All modules are rated for an ambient temperature up to 105°C. Table 12-1. Synchronous Buck DC/DC Power Module Family DC/DC Module Rated IOUT Package Dimensions Features EMI Mitigation TPSM63602 2 A B0QFN (30) 4.0 × 6.0 × 1.8 mm RT adjustable fSW, external synchronization PRSS, RBOOT, integrated input and BOOT capacitorsTPSM63603 3 A TPSM63604 4 A B3QFN (20) 5.0 × 5.5 × 4.0 mm PRSS, RBOOT, integrated input, VCC and BOOT capacitorsTPSM63606 6 A For development support, see the following:

TPSM63602 Quickstart Calculator
TPSM63602 Simulation Models
TPSM63603 and TPSM63603S EVM User's Guide
TPSM63603 Altium Layout Design Files
For TI's reference design library, visit the TI Reference Design library.
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.
TI Reference Designs: – Multiple Output Power Solution For Kintex 7 Application – Arria V Power Reference Design – Altera Cyclone V SoC Power Supply Reference Design – Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count – 3- To 11.5-VIN, –5-VOUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems
Technical Articles: – Powering Medical Imaging Applications With DC/DC Buck Converters – How To Create A Programmable Output Inverting Buck-boost Regulator
To view a related device of this product, see the LM61460 36-V, 6-A synchronous buck converter.

12.1.2.1 Custom Design With WEBENCH® Tools

Product Folder Links: TPSM63602

In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

Texas Instruments, Innovative DC/DC Power Modules selection guide
Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package Technology white paper
Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
Texas Instruments, Simplify Low EMI Design with Power Modules white paper
Texas Instruments, Power Modules for Lab Instrumentation white paper
Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Soldering Considerations for Power Modules application report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, Using the TPSM53602, TPSM53603, and TPSM53604 for Negative Output Inverting Buck-Boost Applications application report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TPSM63602 SLVSGK8 – APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPSM63602

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPSM63602 SLVSGK8 – APRIL 2022 www.ti.com

Product Folder Links: TPSM63602

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPSM63602RDHR Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602 TPSM63602RDHR.A Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602 TPSM63602RDHR.B Active Production B0QFN (RDH) | 30 3000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM63602RDHRG4 Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 63602 TPSM63602RDHRG4.A Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 63602 TPSM63602V3RDHR Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602V3 TPSM63602V3RDHR.A Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602V3 TPSM63602V3RDHR.B Active Production B0QFN (RDH) | 30 3000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM63602V5RDHR Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602V5 TPSM63602V5RDHR.A Active Production B0QFN (RDH) | 30 3000 | LARGE T&R Exempt NIPDAU Level-3-260C-168 HR -40 to 125 63602V5 TPSM63602V5RDHR.B Active Production B0QFN (RDH) | 30 3000 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 9-Nov-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSM63602RDHR B0QFN RDH 30 3000 336.0 336.0 48.0 TPSM63602RDHRG4 B0QFN RDH 30 3000 336.0 336.0 48.0 TPSM63602V3RDHR B0QFN RDH 30 3000 336.0 336.0 48.0 TPSM63602V5RDHR B0QFN RDH 30 3000 336.0 336.0 48.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 4.1 3.9 6.1 5.9 1.9 1.7 0.01 0.00 2X 3 12X 0.5 2X 2.425 .000 PKG 0 2X 1.775 2X 0.975 2X 0.325 2X 0.475 2X 1.125 2X 1.775 2X 2.425 4X 0.675 0.575 22X 0.3 0.2 12X 0.75 0.55 10X 0.6 0.4 2X 1.25 0.1 2X 1.6 0.1 1.925 0.1 0.6 0.1 0.6 0.1 1.925 0.1 2X 1 0.1 2X 0.74 0.1 4X 0.8 0.7 (0.2) TYP (0.15) TYP (0.125) TYP B0QFN - 1.9 mm max heightRDH0030A PLASTIC QUAD FLATPACK - NO LEAD 4226150/B 01/2022 0.08 C

0.1 C A B

0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM SCALE 2.500 AB C

www.ti.com EXAMPLE BOARD LAYOUT (5.7) 2X (1) 2X (0.74) 2X (0.5) 2X (1.25) 2X (1.6) (3.55) 12X (0.5) 2X (3) 30X (0.25) 12X (0.85) 4X (0.95) 4X (0.5) 4X (0.825) 4X (0.625) 2X ( ) 0.325 .000 PKG 0 2X ( ) 0.975 2X ( ) 1.775 2X ( ) 2.425 2X ( ) 0.475 2X ( ) 1.125 2X ( ) 1.775 2X ( ) 2.425 2X ( ) 0.6 1.925 2X ( ) 0.6 1.925 10X (0.7) (R0.05) TYP( 0.2) TYP

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 4X (0.05) 4226150/B 01/2022 B0QFN - 1.9 mm max heightRDH0030A PLASTIC QUAD FLATPACK - NO LEAD NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SYMM EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENINGSOLDER MASK OPENING EXPOSED METAL METAL EDGE

www.ti.com EXAMPLE STENCIL DESIGN 2X (1.17) 2X (1.47) (3.55) 4X (0.825) 4X (0.5) 4X (0.95) 2X (0.74) 2X (0.95) 4X (0.625) 2X (3) 12X (0.5) 10X (0.7) 12X (0.85) (5.7) 0.325 .000 PKG 0 0.975 1.775 2.425 0.475 1.125 1.775 2.425 ( ) 1.925 ( ) 0.6 ( ) 1.925 ( ) 0.6 4X (0.05) B0QFN - 1.9 mm max heightRDH0030A PLASTIC QUAD FLATPACK - NO LEAD 4226150/B 01/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 27 & 30: 94% PRINTED SOLDER COVERAGE BY AREA EXPOSED PAD 28 & 29 87% PRINTED SOLDER COVERAGE BY AREA SCALE:15X SYMM

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Product Information

TPSM63602V5RDHR.A specifications and overview.

Summary

TPSM63602 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 2-A Power Module With Enhanced HotRod™ QFN Package APRIL 2022

Description

TPSM63602 High-Density, 3-V to 36-V Input, 1-V to 16-V Output, 2-A Power Module With Enhanced HotRod™ QFN Package APRIL 2022

Source title TPSM63602V5RDHR.A Datasheet(PDF) - Texas Instruments

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