TPSM5601R5H TI | Alldatasheet

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Technical content

TPSM5601R5Hx, 60-V Input, 1-V to 16-V Output, 1.5-A Power Module in Enhanced HotRod™ QFN Package

1 Features

  • Functional Safety-Capable – Documentation available to aid functional safety system design
  • 5-mm × 5.5-mm × 4-mm Enhanced HotRod™ QFN – Excellent thermal performance: up to 18-W output power at 85°C, no airflow – Standard footprint: single large thermal pad and all pins accessible from perimeter
  • Designed for reliable and rugged applications – Wide input voltage range: 4.2 V to 60 V – Input voltage transient protection up to 66 V – Operating junction range: –40°C to +125°C – EXT-suffix junction range: –55°C to +125°C
  • Fixed 1-MHz switching frequency
  • FPWM mode of operation
  • Optimized for ultra-low EMI requirements – Integrated shielded inductor and high-frequency bypass capacitors – Meets EN55011 EMI standards – Spread spectrum option reduces emissions
  • 26-µA non-switching quiescent current
  • Monotonic start-up into prebiased output
  • No loop-compensation or bootstrap components
  • Precision enable and input UVLO with hysteresis
  • Thermal shutdown protection with hysteresis
  • Create a custom regulator design using WEBENCH® Power Designer

2 Applications

  • Field transmitters and sensors, PLC modules
  • Thermostats, video surveillance, HVAC systems
  • AC and servo drives, rotary encoders
  • Industrial transport, asset tracking
  • Negative output applications

3 Description

The TPSM5601R5Hx power module is a highly integrated 1.5-A power solution that combines a 60- V input, step-down DC/DC converter with power MOSFETs, a shielded inductor, and passives in a thermally-enhanced QFN package. The 5-mm × 5.5-mm × 4-mm, 15-pin QFN package uses Enhanced HotRod QFN technology for enhanced thermal performance, small footprint, and low EMI. The package footprint has all pins accessible from the perimeter and a single large thermal pad for simple layout and easy handling in manufacturing. The TPSM5601R5Hx is a compact, easy-to-use power module with a wide adjustable output voltage range of 1.0 V to 16 V. The total solution requires as few as four external components and eliminates the loop compensation and magnetics part selection from the design process. The full feature set includes power good, programmable UVLO, prebias start-up, overcurrent and temperature protections, making the TPSM5601R5Hx an excellent device for powering a wide range of applications. Space- constrained applications benefit from the 5-mm × 5.5- mm package. Additionally, the TPSM5601R5H EXT offers extended low temperature operation of –55°C and the TPSM5601R5H S offers frequency spread- spectrum operation. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPSM5601R5H QFN (15) 5.0 mm × 5.5 mmTPSM5601R5HE TPSM5601R5HS (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Schematic Output Current (A) Efficiency (%) 100 VOUT = 12 V VIN = 24 V VIN = 48 V VIN = 60 V Typical Efficiency, VOUT = 12 V TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.3 Receiving Notification of Documentation Updates..25

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (March 2021) to Revision B (October 2021) Page Changes from Revision * (December 2020) to Revision A (March 2021) Page TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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5 Device Comparison Table

TPSM5601R5H 60-V input voltage, 1-V to 16-V output voltage, 1.5-A power module, fixed 1-MHz switching, operating junction temperature range: –40°C to +125°C TPSM5601R5HS Equivalent to TPSM5601R5H, but with spread spectrum operation TPSM5601R5HEXT Equivalent to TPSM5601R5H, but with extended junction temperature range: –55°C to +125°C www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSM5601R5H TPSM5601R5HE

6 Pin Configuration and Functions

Figure 6-1. 15-Pin QFN RDA Package (Top View) Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME

10 AGND G

Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. This pin must be connected to PGND at a single point. See Section 11.2 for a recommended layout. 5 DNC — Do not connect. Do not connect this pin to ground, to another pin, or to any other voltage. This pin is connected to the internal bootstrap capacitor. This pin must be soldered to an isolated pad.

2 EN I

Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low. This pin can be connected directly to VIN. Do not float. This pin can be used to set the input undervoltage lockout with two resistors. See Section 8.3.4.

9 FB I

Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. 3, 6, 13 NC — Not connected. These pins are not connected to any circuitry within the module. Leaving these pins unconnected to any other signal increases spacing near the high voltage pins (VIN, SW, EN, DNC). However, if the high voltage spacing is not needed in the application, connecting these pins to the PGND plane can help to enhance shielding and thermal performance.

15 PGND G

Power ground. This is the return current path for the power stage of the device. Connect this pad to the input supply return, load return, and capacitors associated with the VIN and VOUT pins. See Section 11.2 for a recommended layout.

12 PGOOD O

Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required and can be tied to the V5V pin or other DC voltage less than 18 V. If not used, this pin can be left open or connected to PGND. 4 SW O Switch node. Do not place any external component on this pin or connect to any signal. 1, 14 VIN I Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device. 7, 8 VOUT O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND. 11 V5V O Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can be used as logic supply for PGOOD pin. (1) G = Ground, I = Input, O = Output TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

Over the operating ambient temperature range(1) PARAMETER MIN MAX UNIT Input voltage VIN to PGND –0.3 66 V EN to AGND(2) –0.3 VIN + 0.3 PGOOD to AGND(2) –0.3 22 FB to AGND –0.3 5.5 AGND to PGND –0.3 0.3 Output voltage VOUT to PGND(2) –0.3 30 V VCC to AGND 0 5.5 Operating IC junction temperature, TJ (3) Non-EXT suffix device –40 125 °C EXT suffix device –55 125 °C Storage temperature, Tstg –55 150 °C Peak reflow case temperature 245 °C Maximum number or reflows allowed 3 Mechanical vibration Mil-STD-883H, Method 2007.3, 1 msec, 1/2 sine, mounted 20 G Mechanical shock Mil-STD-883H, Method 2002.5, 20 to 2000Hz 500 G (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any conditions beyond those indicated in Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V (3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the module is never exceeded.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±1500 V Charged-device model (CDM)(2) ±1500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM5601R5H TPSM5601R5HE

7.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage, VIN 4.2 60 V Output voltage, VOUT 1 16 (3) V Output current, IOUT 0 1.5 A EN voltage, VEN (2) 0 VIN V PGOOD pullup voltage, VPGOOD (2) 0 18 V Operating ambient temperature, TA Non-EXT suffix device –40 105 °C EXT suffix device –55 105 °C (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Section 7.5. (2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V. (3) The recommended maximum output voltage varies depending input voltage.

7.4 Thermal Information

THERMAL METRIC(1) TPSM5601R5Hx UNITRDA (QFN)

15 PINS

RθJA Junction-to-ambient thermal resistance (2) Nat Conv 20.4 °C/W 100 LFM 18.9 °C/W 200 LFM 17.6 °C/W ψJT Junction-to-top characterization parameter (3) 3.6 °C/W ψJB Junction-to-board characterization parameter (4) 15.3 °C/W TSHDN Thermal shutdown temperature 170 °C Recovery temperature 158 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics app-note. (2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 6.35 cm × 8.25 cm, four-layer PCB with (3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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7.5 Electrical Characteristics

Limits apply over TA = –40°C to +105°C (EXT suffix device; TA = –55°C to +105°C), VIN = 24 V, VOUT = 3.3 V, IOUT = 1.5 A, (unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE (VIN) VIN Input voltage range Over IOUT range 4.2 (1) 60 V VIN turn on VIN increasing, IOUT = 0 A, VEN = VIN 3.8 V VIN turn off VIN decreasing, IOUT = 0 A, VEN = VIN 3.3 V ISHDN Shutdown supply current VEN = 0 V, IOUT = 0 A 5 µA INTERNAL LDO (VCC) VCC Internal LDO output voltage appearing at the VCC pin 6 V ≤ VIN ≤ 60 V 4.75 5 5.25 V FEEDBACK VFB Feedback voltage(2) IOUT = 0A 0.985 1 1.015 V Load regulation TA = +25°C, 0A ≤ IOUT ≤ 1.5A 0.057 % Line regulation TA = +25°C, IOUT = 0A, 6 V ≤ VIN ≤ 60 V 0.024 % IFB Current into FB pin FB = 1 V 0.2 nA CURRENT IOUT Output current TA = 25ºC 0 1.5 A IOUT Over6current threshold VOUT = 3.3 V, TA = 25ºC 1.9 A VHC FB pin voltage required to trip short- circuit hiccup mode 0.4 V tHC Time between current-limit hiccup burst 94 ms ENABLE (EN PIN) VEN-VCC-H EN input level required to turn on internal LDO Rising threshold 1.14 V VEN-VCC-L EN input level required to turn off internal LDO Falling threshold 0.3 V VEN-H EN input level required to start switching Rising threshold 1.157 1.231 1.30 V VEN-HYS Hysteresis below VEN-H Hysteresis below VEN-H; falling 110 mV ILKG-EN Enable input leakage current VEN = 3.3 V 0.2 nA POWER GOOD (PGOOD PIN) VPG-LOW-UP VOUT rising (fault) % of FB voltage 107% VPG-HIGH-DN VOUT falling (good) % of FB voltage 105% VPG-HIGH-UP VOUT rising (good) % of FB voltage 95% VPG-LOW-DN VOUT falling (fault) % of FB voltage 93% RPG Power-good flag RDSON VEN = 0 V 35 Ω VIN-PG Minimum input voltage for proper PGOOD function IPG = 50 µA, EN = 0 V 2 V www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM5601R5H TPSM5601R5HE

7.5 Electrical Characteristics (continued)

Limits apply over TA = –40°C to +105°C (EXT suffix device; TA = –55°C to +105°C), VIN = 24 V, VOUT = 3.3 V, IOUT = 1.5 A, (unless otherwise noted); Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PERFORMANCE η Efficiency VOUT = 3.3 V, IOUT = 0.75 A, TA = 25ºC 81% η Efficiency VOUT = 5.0 V, IOUT = 0.75 A, TA = 25ºC 86% SOFT START tSS Internal soft-start time 4.5 ms SWITCHING FREQUENCY ƒSW Switching frequency IOUT = 0.75 A, TA = 25ºC 0.85 1(3) 1.15 MHz ƒSW ss device Switching frequency for spread spectrum device only IOUT = 0.75 A, TA = 25ºC 0.80 1 1.20 MHz (1) The recommended minimum VIN is 4.2 V or (VOUT + 600 mV), whichever is greater. (2) The overall output voltage tolerance is affected by the tolerance of the external RFBT and RFBB resistors. (3) The typical switching frequency of this device will change based on operating conditions. See the Switching Frequency section for more information. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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7.6 Typical Characteristics (VIN = 12 V)

TA = 25°C, unless otherwise noted. Output Current (A) Efficiency (%) 100 VOUT 5.0 V 3.3 V 2.5 V 1.8 V 1.2 V Figure 7-1. Efficiency Output Current (A) Power Dissipation (W) 0.2 0.4 0.6 0.8 1.2 VOUT 5.0 V 3.3 V 2.5 V 1.8 V 1.2 V Figure 7-2. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT 5.0 V 3.3 V 2.5 V 1.8 V 1.2 V COUT = 2 × 47 µF, 25-V, ceramic Figure 7-3. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-4. Safe Operating Area (VOUT = 1.2 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-5. Safe Operating Area (VOUT = 3.3 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-6. Safe Operating Area (VOUT = 5.0 V) www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM5601R5H TPSM5601R5HE

7.7 Typical Characteristics (VIN = 24 V)

TA = 25°C, unless otherwise noted. Output Current (A) Efficiency (%) 100 VOUT 15 V 12 V 9 V 5 V 3.3 V 2.5 V 1.8 V Figure 7-7. Efficiency Output Current (A) Power Dissipation (W) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 VOUT 15 V 12 V 9 V 5 V 3.3 V 2.5 V 1.8 V Figure 7-8. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT 15 V 12 V 9 V 5 V 3.3 V 2.5 V 1.8 V COUT = 2 × 47-µF, 25-V, ceramic Figure 7-9. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-10. Safe Operating Area (VOUT = 1.8 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-11. Safe Operating Area (VOUT = 5.0 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-12. Safe Operating Area (VOUT = 12 V) TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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7.8 Typical Characteristics (VIN = 48 V)

TA = 25°C, unless otherwise noted. Output Current (A) Efficiency (%) 100 VOUT 15 V 12 V 9 V 5 V 3.3 V Figure 7-13. Efficiency Output Current (A) Power Dissipation (W) 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 VOUT 15 V 12 V 9 V 5 V 3.3 V Figure 7-14. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT 15 V 12 V 9 V 5 V 3.3 V COUT = 2 × 47-µF, 25-V, ceramic Figure 7-15. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-16. Safe Operating Area (VOUT = 5.0 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-17. Safe Operating Area (VOUT = 12 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-18. Safe Operating Area (VOUT = 15 V) www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSM5601R5H TPSM5601R5HE

7.9 Typical Characteristics (VIN = 60 V)

TA = 25°C, unless otherwise noted. Output Current (A) Efficiency (%) 100 VOUT 15 V 12 V 9 V 5 V 3.3 V Figure 7-19. Efficiency Output Current (A) Power Dissipation (W) 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 VOUT 15 V 12 V 9 V 5 V 3.3 V Figure 7-20. Power Dissipation Output Current (A) Output Voltage Ripple (mV) VOUT 15 V 12 V 9 V 5 V 3.3 V COUT = 2 × 47-µF, 25-V, ceramic Figure 7-21. Output Voltage Ripple Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-22. Safe Operating Area (VOUT = 5.0 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-23. Safe Operating Area (VOUT = 12 V) Output Current (A) Ambient Temperature (°C) 105 115 Airflow 400LFM 200LFM 100LFM Nat conv Device soldered to a 63.5-mm × 82.5-mm, 4-layer PCB Figure 7-24. Safe Operating Area (VOUT = 15 V) TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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8 Detailed Description

8.1 Overview

The TPSM5601R5Hx converter is an easy-to-use, synchronous buck, DC-DC power module that operates from a 4.2-V to 60-V supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 48-V unregulated, semi-regulated, or fully-regulated supply rails. With an integrated power controller, inductor, and MOSFETs, the TPSM5601R5Hx delivers up to 1.5-A DC load current, with high efficiency and ultra-low input quiescent current, in a very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. Control-loop compensation is not required, reducing design time and external component count. The TPSM5601R5Hx incorporates several features for comprehensive system requirements, including the following:

  • Open-drain Power Good circuit for power-rail sequencing and fault reporting
  • Monotonic start-up into prebiased loads
  • Precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO)
  • Overcurrent and thermal shutdown with automatic recovery Additionally, the TPSM5601R5HxS offers frequency spread-spectrum operation. These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple PCB layout, requiring as few as four external components.

8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Adjustable Output Voltage (FB)

The TPSM5601R5Hx has an adjustable output voltage range of 1.0 V to 16 V. Setting the output voltage requires two resistors, R FBT and R FBB (see Figure 8-1). Connect R FBT between VOUT, at the regulation point, and the FB pin. Connect R FBB between the FB pin and AGND (pin 10). The recommended value of R FBT is 10 kΩ. The value for RFBB can be calculated using Equation 1. RFBB = VOUT 1.0 1.0 × RFBT (1) AGND VOUT FB RFBT 10 k RFBB Figure 8-1. FB Resistor Divider Table 8-1. Standard RFBB Values VOUT (V) RFBB (kΩ) (1) VOUT (V) RFBB (kΩ) (1) 1.0 open 3.3 4.32 1.2 49.9 5.0 2.49 1.5 20.0 7.5 1.54 1.8 12.4 10 1.10 2.0 10.0 12 0.909 2.5 6.65 15 0.715 3.0 4.99 16 0.665 (1) RFBT = 10 kΩ Selecting an R FBT value of 10 k Ω is recommended for most applications. A larger R FBT consumes less DC current, which is mandatory if light-load efficiency is critical. However, R FBT larger than 1 M Ω is not recommended as the feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful layout of the feedback path. It is important to keep the feedback trace as short as possible while keeping the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Section 11. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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8.3.2 Minimum Input Capacitance

The TPSM5601R5Hx requires a minimum input capacitance of 9.4 μF (2 × 4.7 μF) of ceramic type. High-quality, ceramic-type X5R or X7R capacitors with sufficient voltage rating are required. Place the input capacitors, as close as possible to both VIN pins of the device, between VIN and PGND as shown in Section 11.1. Applications with transient load requirements can benefit from adding additional bulk capacitance to the input as well.

8.3.3 Minimum Output Capacitance

The TPSM5601R5Hx requires a minimum amount of ceramic output capacitance depending on the output voltage setting. The amount of required output capacitance is shown in Figure 8-2 and is the amount of effective capacitance. The effects of DC bias and temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contributes to differences between the standard rated value and the actual effective value of the capacitance. When adding additional capacitance above the minimum, the capacitance can be ceramic type, low-ESR polymer type, or a combination of the two. Output Voltage (V) Minimum Effective COUT (µF) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 100 125 150 175 200 225 250 275 Figure 8-2. Minimum Required Output Capacitance www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM5601R5H TPSM5601R5HE

8.3.4 Precision Enable (EN), Undervoltage Lockout (UVLO), and Hysteresis (HYS)

The EN pin provides precision ON and OFF control for the TPSM5601R5Hx. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. The simplest way to enable the device is to connect EN directly to VIN. This allows the device to start up when V IN is within its valid operating range. An external logic signal can also be used to drive the EN input to toggle the output on and off and for system sequencing or protection. This input must not be allowed to float. The TPSM5601R5Hx implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.8 V (typical) with a typical hysteresis of 500 mV. If an application requires a higher UVLO threshold, the EN input supports adjustable UVLO by connecting a resistor divider from VIN to the EN pin. Applying a voltage of ≥ 1.14 V causes the device to enter standby mode, powering the internal LDO, but not producing an output voltage. Increasing the EN voltage to 1.231 V (typ.) fully enables the device, allowing it to enter start-up mode and starting the soft-start period. When the EN input is brought below 1.121 V (110 mV hysteresis), the regulator stops running and enters standby mode. Further decrease in the EN voltage to below 0.3 V completely shuts down the device. The TPSM5601R5Hx utilizes a reference-based soft start that prevents output voltage overshoots and large inrush currents as the regulator is starting up. The rise time of the output voltage is about 4 ms.

8.3.5 Power Good (PGOOD)

The TPSM5601R5Hx provides a PGOOD signal to indicate when the output voltage is within regulation. Use the PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 18 V. V5V or VOUT can be used as the pullup voltage source. Typical range of pullup resistance is 10 k Ω to 100 k Ω. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail. If this function is not needed, the PGOOD pin must be grounded. When the output voltage exceeds 95% (rising) or decreases below 105% (falling) of the setpoint, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 93% or rises above 107% of the setpoint, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the power-good function.

8.3.6 Spread Spectrum Operation

Spread spectrum is a factory option in the TPSM5601R5HS variant. The purpose of the spread spectrum is to eliminate peak emissions at specific frequencies by spreading emissions across a wider range of frequencies than a part with fixed frequency operation. In most systems, low frequency conducted emissions from the first few harmonics of the switching frequency can be easily filtered. A more difficult design criterion is reduction of emissions at higher harmonics which fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node. The TPSM5601R5HS device with triangular spread spectrum uses a ±4% spreading rate (typical) with the modulation rate set at 16 kHz (typical). The spread spectrum is only available while the internal clock is free running at its natural frequency. Any of the following conditions override spread spectrum, turning it off:

  • At high input voltages/low output voltage ratio when the device operates at minimum on time the internal clock is slowed disabling spread spectrum.
  • The clock is slowed during dropout.

8.3.7 Overcurrent Protection (OCP)

The TPSM5601R5Hx is protected from overcurrent conditions using cycle-by-cycle current limiting for overload conditions and hiccup mode for short circuits. The current is compared every switching cycle to the current limit threshold. During an overcurrent condition, the output voltage decreases. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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8.3.8 Thermal Shutdown

Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C (typ.) to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the TPSM5601R5Hx restarts when the junction temperature falls to 158°C (typ.).

8.4 Device Functional Modes

8.4.1 Active Mode

The TPSM5601R5Hx is in active mode when VIN is above the turn-on threshold and the EN pin voltage is above the EN high threshold. Connect the EN pin to VIN to allow the device to start up when a valid input voltage is applied. This allows self start-up of the TPSM5601R5Hx when the input voltage is in the operation range of 4.2 V to 60 V. Connecting a resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the turn on until VIN is closer to its regulated voltage.

8.4.2 Standby Mode

Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use of an external voltage divider to provide an adjustable input UVLO. Applying a voltage of ≥ 1.14 causes the device to enter standby mode, powering the internal LDO, but not producing an output voltage. Increasing the EN voltage to 1.231 V (typ.) fully enables the device, allowing it to enter start-up mode and starting the soft-start period. When the EN input is brought below 1.121 V (110-mV hysteresis), the regulator stops running and enters standby mode. Further decrease in the EN voltage to below 0.3 V completely shuts down the device.

8.4.3 Shutdown Mode

The EN pin provides ON and OFF control for the TPSM5601R5Hx. When VEN is below the EN low threshold, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 5 µA at VIN = 24 V. www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM5601R5H TPSM5601R5HE

9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPSM5601R5Hx only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. To expedite and streamline the process of designing of a TPSM5601R5Hx, WEBENCH® online software is available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. The following section describes the design procedure to configure the TPSM5601R5Hx power module. As mentioned previously, the TPSM5601R5Hx also integrates several optional features to meet system design requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below shows TPSM5601R5Hx configuration options suitable for several application use cases. Refer to the TPSM5601R5HxEVM user's guide for more detail.

9.2 Typical Application

Figure 9-1 shows the schematic diagram of a 24-V input, 5-V output, 1.5-A converter. VIN PGND VOUT 2.49 kO FB 10 kO PGOOD EN V5V TPSM5601R5H AGND VOUT = 5 V 47 µF 10 V 47 µF 10 V VIN = 24 V 4.7 µF 100 V 100 kO 4.7 µF 100 V Figure 9-1. TPSM5601R5Hx Typical Schematic

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1 as the input parameters and follow the design procedures in Section 9.2.2. Table 9-1. Design Example Parameters DESIGN PARAMETER VALUE Input voltage VIN 24 V typical Output voltage VOUT 5 V Output current rating 1.5 A TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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9.2.2 Detailed Design Procedure

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM5601R5Hx device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance.
  • Run thermal simulations to understand board thermal performance.
  • Export customized schematic and layout into popular CAD formats.
  • Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM5601R5Hx device is externally adjustable using a resistor divider. The recommended value of R FBT is 10 k Ω. The value for R FBB can be selected from Table 8-1 or calculated using Equation 2: RFBB = VOUT 1.0 1.0 × RFBT (2) For the desired output voltage of 5 V, the formula yields a value of 2.5 kΩ. Choose the closest available standard value of 2.49 kΩ for RFBB.

9.2.2.3 Input Capacitors

The TPSM5601R5Hx requires a minimum input capacitance of 2 × 4.7-µF ceramic type. High-quality ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, 2 × 4.7-µF, 100-V ceramic capacitors are selected.

9.2.2.4 Output Capacitor Selection

The TPSM5601R5Hx requires a minimum amount of output capacitance for proper operation. The minimum amount of required output varies depending on the output voltage. See Figure 8-2 for the required output capacitance. Additional output capacitance can be added to reduce ripple voltage or for applications with transient load requirements. For this design example, 2 × 47-µF, 10-V, ceramic capacitors are used.

9.2.2.5 Power Good Signal

Applications requiring a power good signal to indicate that the output voltage is present and in regulation must use a pullup resistor between the PGOOD pin and a valid voltage source. For this design a 100-k Ω resistor is placed between the PGOOD pin and the V5V pin (the internal 5-V LDO output). www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM5601R5H TPSM5601R5HE

9.2.3 Application Curves

VIN = 24 V VOUT = 5 V IOUT = 1.5 A Figure 9-2. Start-up Waveforms VIN = 24 V VOUT = 5 V IOUT = 1.5 A Figure 9-3. Enable Shutdown Waveforms COUT = 2 × 47 µF IOUT = 1.5 A Figure 9-4. Output Ripple Waveform COUT = 2 × 47 µF 1-A load step 2.5 A/µs Figure 9-5. Transient Response Waveform

10 Power Supply Recommendations

The TPSM5601R5Hx is designed to operate from an input voltage supply range between 4.2 V and 60 V. This input supply must be able to provide the maximum input current and maintain a voltage above the set UVLO voltage. Ensure that the resistance of the input supply rail is low enough that an input current transient does not cause a high enough drop at the TPSM5601R5Hx supply rail to cause a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the TPSM5601R5Hx, additional bulk capacitance can be required in addition to the ceramic input capacitance. A 47- μF electrolytic capacitor is a typical choice for this function, whereby the capacitor ESR provides a level of damping against input filter resonances. A typical ESR of 0.5 Ω provides enough damping for most input circuit configurations. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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11 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal thermal performance, and minimal generation of unwanted EMI.

11.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 11-1 and Figure 11-2 show a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
  • Connect all PGND pins together using copper plane.
  • Connect AGND pin to the PGND copper at a single point near the pin.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Place RFBT and RFBB as close as possible to their respective pins.
  • Use multiple vias to connect the power planes to internal layers.

11.2 Layout Example

Figure 11-1. Typical Layout Figure 11-2. Typical Top-Layer Figure 11-3. Typical Mid-Layer Figure 11-4. Typical PGND-Layer www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM5601R5H TPSM5601R5HE

11.2.1 Theta JA versus PCB Area

The amount of PCB copper as well as airflow effects the thermal performance of the device. Figure 11-5 shows the effects of copper area and airflow on the junction-to-ambient thermal resistance (R θJA) of the TPSM5601R5Hx. The junction-to-ambient thermal resistance versus PCB area is plotted for a 4-layer PCB. To determine the required copper area for an application: 1. Determine the maximum power dissipation of the device in the application by referencing the power dissipation graphs in the Typical Characteristics. 2. Calculate the maximum θJA using Equation 3 and the maximum ambient temperature of the application. JA = (ÛC/W)(125ÛC ± TA(max)) PD(max) (3) 3. Reference Figure 11-5 to determine the minimum required PCB area for the application conditions. PCB Area (cm²) Theta JA (°C/W) 0 5 10 15 20 25 30 35 40 45 50 55 Nat Conv

100 LFM

200 LFM

Figure 11-5. θJA vs PCB Area

11.2.2 Package Specifications

Table 11-1. Package Specifications Table TPSM5601R5H VALUE UNIT Weight 429 mg Flammability Meets UL 94 V-O MTBF Calculated Reliability Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 87.7 MHrs TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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11.2.3 EMI

The TPSM5601R5H is compliant with EN55011 radiated emissions. Figure 11-6 through Figure 11-9 show typical examples of radiated emission plots for the TPSM5601R5H. The graphs include the plots of the antenna in the horizontal and vertical positions.

11.2.3.1 EMI Plots

EMI plots were measured using the standard TPSM5601R5HEVM. Figure 11-6. Radiated Emissions 24-V Input, 5-V Output, 1.5-A Load Figure 11-7. Radiated Emissions 24-V Input, 5-V Output, 1.5-A Load (Spread spectrum) www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM5601R5H TPSM5601R5HE

Figure 11-8. Radiated Emissions 24-V Input, 12-V Output, 1.5-A Load Figure 11-9. Radiated Emissions 48-V Input, 12-V Output, 1.5-A Load TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.1.2 Development Support

For development support, see the following:

  • For TI's reference design library, visit TI Designs.
  • To view a related device of this product, see the TPSM5601R5Hx.

12.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM5601R5H device with WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance.
  • Run thermal simulations to understand board thermal performance.
  • Export customized schematic and layout into popular CAD formats.
  • Print PDF reports for the design, and share the design with colleagues. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

  • Texas Instruments, TPSM5601R5HxEVM User's Guide
  • Texas Instruments, Using the TPSM5601R5Hx in an Inverting Buck-Boost Topology Application Report
  • Texas Instruments, Using New Thermal Metrics Application Report
  • Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. www.ti.com TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM5601R5H TPSM5601R5HE

is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refer to the left-hand navigation. TPSM5601R5H, TPSM5601R5HE SLVSFI4B – DECEMBER 2020 – REVISED OCTOBER 2021 www.ti.com

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www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPSM5601R5HEXTRDAR Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -55 to 125 5601R5HEXT TPSM5601R5HEXTRDAR.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -55 to 125 5601R5HEXT TPSM5601R5HEXTRDAR.B Active Production B3QFN (RDA) | 15 1000 | LARGE T&R - Call TI Call TI -55 to 125 TPSM5601R5HRDAR Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5H TPSM5601R5HRDAR.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5H TPSM5601R5HRDAR.B Active Production B3QFN (RDA) | 15 1000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM5601R5HRDARG4 Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5H TPSM5601R5HRDARG4.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5H TPSM5601R5HSRDAR Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5HS TPSM5601R5HSRDAR.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5HS TPSM5601R5HSRDAR.B Active Production B3QFN (RDA) | 15 1000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM5601R5HSRDARG4 Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5HS TPSM5601R5HSRDARG4.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 5601R5HS (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 9-Nov-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSM5601R5HEXTRDAR B3QFN RDA 15 1000 336.0 336.0 48.0 TPSM5601R5HRDAR B3QFN RDA 15 1000 336.0 336.0 48.0 TPSM5601R5HRDARG4 B3QFN RDA 15 1000 336.0 336.0 48.0 TPSM5601R5HSRDAR B3QFN RDA 15 1000 336.0 336.0 48.0 TPSM5601R5HSRDARG4 B3QFN RDA 15 1000 336.0 336.0 48.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 5.1 4.9 5.6 5.4

4.1 MAX

2.6 TYP

8X 0.65 2X 0.725 1.43 2X 0.975 2.5 0.05 2.5 0.05 4.6 0.05 1.5 0.05 3X 1.3 1.1 10X 0.6 0.4 1.3 1.1 4X 0.6 0.4 10X 0.45 0.25 (0.16) TYP B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PIN 1 INDEX AREA 0.08 C SEATING PLANE PKG PKG

0.1 C A B

0.05 C 0.05 C PIN 1 ID SCALE 1.800 AB C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(4.7) 2X (4) (1) TYP (1) TYP (4.6) (2.5) (1.5) (2.5) 4X (1.4) 4X (0.5) 10X (0.7) 10X (0.35) 2X (1.43) 8X (0.65) 2X (0.725) 2X (0.975) (R0.05) TYP ( 0.2) VIA TYP B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 16X PKG PKG SCALE 30.000 SOLDER MASK DETAILS EXPOSED METAL METAL EDGESOLDER MASK OPENING EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.65) 10X (0.3) 4X (0.6) (0.65) (0.95) 4X (0.475) 2X (4) (4.7) 2X (0.975) 4X (1.35) 4X (0.45) 2X (1.43) 8X (0.65) 2X (0.725) (R0.05) TYP (1.15) 4X (0.425) 4X (1.675) 4X (0.625) B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 15: 56% PRINTED SOLDER COVERAGE BY AREA SCALE: 16X PKG PKG

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