TPSM53602RDARG4.A

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TPSM53602 36-V Input, 2-A Power Module in Enhanced HotRod™ QFN Package REVISED SEPTEMBER 2021

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TPSM53602 36-V Input, 2-A Power Module in Enhanced HotRod™ QFN Package

1 Features

Functional Safety-Capable – Documentation available to aid functional safety system design
5-mm × 5.5-mm × 4-mm Enhanced HotRod™ QFN package – 85-mm2 solution size (single sided) – Low EMI: meets CISPR11 radiated emissions – Excellent thermal performance: Up to 14 W output power at 85°C, no airflow – Standard footprint: single large thermal pad and all pins accessible from perimeter
Input voltage range: 3.8 V to 36 V
Output voltage range: 1 V to 7 V
Efficiency up to 95%
Power-good flag
Precision enable
Built-in hiccup-mode short-circuit protection, over- temperature protection, start-up into pre-bias output, soft start, and UVLO
Operating IC junction range: –40°C to +125°C
Operating ambient range: –40°C to +105°C
Shock and vibration tested to Mil-STD-883D
Pin compatible with: 3-A TPSM53603 and 4-A TPSM53604
Create a custom design using the TPSM53602 with the WEBENCH® Power Designer
Download the EVM Design Files for fast board design

2 Applications

General purpose wide VIN power supplies
Factory automation and control
Test and measurement
Aerospace and defense
Negative output voltage applications

3 Description

The TPSM53602 power module is a highly integrated 2-A power solution that combines a 36-V input, step-down, DC/DC converter with power MOSFETs, a shielded inductor, and passives in a thermally- enhanced QFN package. The 5-mm x 5.5-mm x 4- mm, 15-pin package uses Enhanced HotRod QFN technology for improved thermal performance, small footprint, and low EMI. The package footprint has all pins accessible from the perimeter and a single large thermal pad for simple layout and easy handling in manufacturing. The total solution requires as few as four external components and eliminates the loop compensation and magnetics part selection from the design process. The full feature set includes power good, programmable UVLO, prebias start-up, overcurrent, and overtemperature protections, making the TPSM53602 an excellent device for powering a wide range of applications. Device Information DEVICE NUMBER (1) PACKAGE BODY SIZE (NOM) TPSM53602 B3QFN (15) 5.0 mm × 5.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Enhanced HotRod QFN and Typical Layout VIN PGND VIN VOUT VOUT FB PGOOD EN V5V TPSM53602 AGND CIN RFBT RFBB COUT GND Simplified Schematic Output Current (A) Efficiency (%) 0 0.5 1 1.5 2 100 VOUT = 5 V EFF5 VIN 12 V

24 V 5 VOUT Efficiency

SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11.3 Receiving Notification of Documentation Updates.. 27

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2020) to Revision B (September 2021) Page Changes from Revision * ( December 2019) to Revision A (August 2020) Page TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. RDA Package 15-Pin QFN Top View Table 5-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME

12 AGND G

Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. This pin must be connected to PGND at a single point. See Section 10 for a recommended layout. 4, 5 DNC — Do not connect. Do not connect these pins to ground, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

2 EN I

Enable pin. This pin turns the converter on when pulled high and turns off the converter when pulled low. This pin can be connected directly to VIN. Do not float. This pin can be used to set the input under voltage lockout with two resistors. See Section 7.3.6.

9 FB I

Feedback input. Connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. 3, 10, 11 NC — Not connected. These pins are not connected to any circuitry within the module. It is recommended that these pins be connected to the PGND plane on the application board to enhance shielding and thermal performance.

15 PGND G

Power ground. This is the return current path for the power stage of the device. Connect this pad to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See Section 10 for a recommended layout.

6 PGOOD O

Power-good pin. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required and can be tied to the V5V pin or other DC voltage less than 22 V. If not used, this pin can be left open or connected to PGND. 1, 14 VIN I Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device. 7, 8 VOUT O Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND. 13 V5V O Internal 5-V LDO output. Supplies internal control circuits. Do not connect to external loads. This pin can be used as logic supply for PGOOD pin. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSM53602

6 Specifications

6.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range(1) PARAMETER MIN MAX UNIT Input voltage VIN to PGND –0.3 38 V EN to AGND(2) –0.3 VIN + 0.3 PGOOD to AGND(2) –0.3 22 FB to AGND –0.3 5.5 AGND to PGND –0.3 0.3 Output voltage VOUT to PGND(2) -0.3 VIN + 0.3 V V5V to AGND 0 5.5 Operating IC junction temperature, TJ (3) –40 150 °C Storage temperature, Tstg –55 150 °C Peak reflow case temperature 245 °C Maximum number or reflows allowed 3 Mechanical vibration Mil-STD-883D, Method 2007.2, 20 to 2000 Hz 20 G Mechanical shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 500 G (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V. (3) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the module is never exceeded.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±2500 V Charged-device model (CDM)(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted) (1) MIN MAX UNIT Input voltage, VIN 3.8 (3) 36 V Output voltage, VOUT 1 7 (4) V Output current, IOUT 0 2 A EN voltage, VEN (2) 0 VIN V PGOOD pullup voltage, VPGOOD (2) 0 18 V PGOOD sink current 3 mA Operating ambient temperature, TA –40 105 °C Input capacitance, CIN (5) 20 µF Output capacitance, COUT min (6) 1000 µF (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see the Section 6.5. (2) The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V. (4) The recommended maximum output voltage varies depending input voltage. See the Section 7.3.9 section for more information. (5) Minimum CIN of 20 µF must be ceramic type. (6) The minimum amount of required output capacitance varies depending on the output voltage. See Table 7-1. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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6.4 Thermal Information

THERMAL METRIC(1) TPSM53602 UNITRDA (QFN)

15 PINS

RθJA Junction-to-ambient thermal resistance (2) 19.5 °C/W ψJT Junction-to-top characterization parameter (3) 1.0 °C/W ψJB Junction-to-board characterization parameter (4) 5.5 °C/W TSHDN Thermal shutdown temperature 165 °C Recovery temperaure 148 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75-mm x 75-mm four-layer PCB with 2-oz. copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA. For more information see the Section 10.3 section. (3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device.

6.5 Electrical Characteristics

Limits apply over TA = –40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, IOUT = IOUT maximum, (unless otherwise noted); CIN1 = 2x10 µF, 50-V, 1206 ceramic; CIN2 = 100 nF, 50-V, 0603 ceramic; COUT = 3x22 µF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VOLTAGE (VIN) VIN Input voltage range Over IOUT range 3.8 (1) 36 V VIN turn on VIN increasing, IOUT = 0 A 3.55 V VIN turn off VIN decreasing, IOUT = 0 A 3.05 V IQ Quiescient current Non-switching, VFB = 1.2 V 24 µA ISHDN Shutdown supply current VEN = 0 V, IOUT = 0 A 5 10 µA INTERNAL LDO (V5V) V5V Internal LDO output voltage appearing at the V5V pin 6 V ≤ VIN ≤ 36 V 4.75 5 5.25 V FEEDBACK VFB Feedback voltage(2) –40°C ≤ TJ ≤ +125°C, IOUT = 0.75 A 0.985 1 1.015 V Load regulation TA = +25°C, 0.5 A ≤ IOUT ≤ 2 A 0.06 % Line regulation TA = +25°C, IOUT = 0.75 A, Over VIN range 0.15 % IFB Current into FB pin FB = 1 V 0.2 50 nA CURRENT IOUT Output current TA = 25°C 0 2 A IOUT Over-current threshold 3.5 A VHC FB pin voltage required to trip short- circuit hiccup mode 0.4 V tHC Time between current-limit hiccup burst 94 ms ENABLE (EN PIN) VEN-VCC-H EN input level required to turn on internal LDO Rising threshold 1 V VEN-VCC-L EN input level required to turn off internal LDO Falling threshold 0.3 V VEN-H EN input level required to start switching Rising threshold 1.2 1.23 1.26 V VEN-HYS Hysteresis below VEN-H Falling 100 mV ILKG-EN Enable input leakage current VEN = 3.3 V 0.2 nA www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM53602

Limits apply over TA = –40°C to +105°C, VIN = 12 V, VOUT = 3.3 V, IOUT = IOUT maximum, (unless otherwise noted); CIN1 = 2x10 µF, 50-V, 1206 ceramic; CIN2 = 100 nF, 50-V, 0603 ceramic; COUT = 3x22 µF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD (PGOOD PIN) VPG-HIGH-UP VOUT rising (fault) % of FB voltage 107 % VPG-HIGH-DN VOUT falling (good) % of FB voltage 105 % VPG-LOW-UP VOUT rising (good) % of FB voltage 94 % VPG-LOW-DN VOUT falling (fault) % of FB voltage 92 % RPG Power-good flag RDSON VEN = 0 V 35 Ω VIN-PG Minimum input voltage for proper PGOOD function 50-µA, EN = 0 V 2 V VPG PGOOD logic low output 50-µA, EN = 0 V, VIN = 2 V 0.2 V PERFORMANCE η Efficiency IOUT = 2 A, TA = 25°C 91 % SOFT START tSS Internal soft-start time 4 ms SWITCHING FREQUENCY ƒSW-MAX Max switching frequency IOUT = 2 A, TA = 25°C 1.4(3) MHz (2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors. (3) The typical switching frequency of this device will change based on operating conditions. See the Section 7.4.2 section for more information. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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6.6 Typical Characteristics (VIN = 5 V)

The typical characteristic data has been developed from actual products tested at T A = 25°C. This data is considered typical for the device. Output Current (A) Efficiency (%) 100 D001 VOUT 3.3 V 2.5 V 1.8 V 1.0 V VIN = 5 V Linear Scale Figure 6-1. Efficiency versus Output Current Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 100 D002 VOUT 3.3 V 2.5 V 1.8 V 1.0 V VIN = 5 V Log Scale Figure 6-2. Efficiency versus Output Current Output Current (A) Power Dissipation (W) 0.0 0.2 0.4 0.6 0.8 D003 VOUT 3.3 V 2.5 V 1.8 V 1.0 V VIN = 5 V Figure 6-3. Power Dissipation versus Output Current Output Current (A) Output Voltage Ripple (mVpp) D004 VOUT 3.3 V 2.5 V 1.8 V 1.0 V VIN = 5 V COUT = 4x 47µF Figure 6-4. Voltage Ripple versus Output Current Output Current (A) Ambient Temperature (°C) 0 0.5 1 1.5 2 105 115 D005 Airflow Nat conv VIN = 5 V VOUT ≤ 4 V PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-5. Safe Operating Area www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM53602

6.7 Typical Characteristics (VIN = 12 V)

The typical characteristic data has been developed from actual products tested at T A = 25°C. This data is considered typical for the device. Output Current (A) Efficiency (%) 100 D007 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V 1.0 V VIN = 12 V Linear Scale Figure 6-6. Efficiency versus Output Current Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 100 D008 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V 1.0 V VIN = 12 V Log Scale Figure 6-7. Efficiency versus Output Current Output Current (A) Power Dissipation (W) 0.0 0.2 0.4 0.6 0.8 1.0 D009 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V 1.0 V VIN = 12 V Figure 6-8. Power Dissipation versus Output Current Output Current (A) Output Voltage Ripple (mV) D010 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V 1.0 V VIN = 12 V COUT = 4x 47µF Figure 6-9. Voltage Ripple versus Output Current Output Current (A) Ambient Temperature (°C) 0 0.5 1 1.5 2 105 115 D011 Airflow Nat conv VIN = 12 V All VOUT PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-10. Safe Operating Area TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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6.8 Typical Characteristics (VIN = 24 V)

The typical characteristic data has been developed from actual products tested at T A = 25°C. This data is considered typical for the device. Output Current (A) Efficiency (%) 100 D013 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V VIN = 24 V Figure 6-11. Efficiency versus Output Current Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 100 D014 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V VIN = 24 V Figure 6-12. Efficiency versus Output Current Output Current (A) Power Dissipation (W) 0.0 0.3 0.6 0.9 1.2 1.5 1.8 D015 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V VIN = 24 V Figure 6-13. Power Dissipation versus Output Current Output Current (A) Output Voltage Ripple (mVpp) D016 VOUT 7.0 V 5.0 V 3.3 V 2.5 V 1.8 V VIN = 24 V COUT = 4x 47µF Figure 6-14. Voltage Ripple versus Output Current Output Current (A) Ambient Temperature (°C) 105 115 D017 Airflow Nat conv VIN = 24 V VOUT ≤ 1.8 V PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-15. Safe Operating Area Output Current (A) Ambient Temperature (°C) 105 115 D018 Airflow 400LFM 200LFM 100LFM Nat conv VIN = 24 V VOUT = 5 V PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-16. Safe Operating Area www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM53602

6.9 Typical Characteristics (VIN = 36 V)

The typical characteristic data has been developed from actual products tested at T A = 25°C. This data is considered typical for the device. Output Current (A) Efficiency (%) 100 D019 VOUT 7.0 V 5.0 V 3.3 V 2.5 V VIN = 36 V Figure 6-17. Efficiency versus Output Current Output Current (A) Efficiency (%) 0.001 0.01 0.1 1 2 100 D020 VOUT 7.0 V 5.0 V 3.3 V 2.5 V VIN = 36 V Figure 6-18. Efficiency versus Output Current Output Current (A) Power Dissipation (W) 0.0 0.4 0.8 1.2 1.6 2.0 2.4 D021 VOUT 7.0 V 5.0 V 3.3 V 2.5 V VIN = 36 V Figure 6-19. Power Dissipation versus Output Current Output Current (A) Output Voltage Ripple (mVpp) D022 VOUT 7.0 V 5.0 V 3.3 V 2.5 V VIN = 36 V COUT = 4x 47µF Figure 6-20. Voltage Ripple versus Output Current Output Current (A) Ambient Temperature (°C) 105 115 D023 Airflow 400LFM 200LFM 100LFM Nat conv VIN = 36 V VOUT = 1.8 V PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-21. Safe Operating Area Output Current (A) Ambient Temperature (°C) 105 115 D024 Airflow 400LFM 200LFM 100LFM Nat conv VIN = 36 V VOUT = 5 V PCB = 85-mm × 65-mm, 4-layer, 2-oz. copper Figure 6-22. Safe Operating Area TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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7 Detailed Description

7.1 Overview

The TPSM53602 is a full-featured, 36-V input, 2-A, synchronous step-down converter with PWM, MOSFETs, shielded inductor, and control circuitry integrated into a low-profile, over-molded package. The device integration enables small designs while providing the ability to adjust key parameters to meet specific design requirements. The TPSM53602 provides an output voltage range of 1 V to 7 V. An external resistor divider is used to adjust the output voltage to the desired value. The device provides accurate voltage regulation over a wide load range by using a precision internal voltage reference. Input undervoltage lockout is internally set at 3.55 V (typical), but can be adjusted upward using a resistor divider on the EN pin of the device. The EN pin can also be pulled low to put the device into standby mode to reduce input current draw. A power-good signal is provided to indicate when the output is within its nominal voltage range. Thermal shutdown and current limit features protect the device during an overload condition. A 15-pin, QFN package that includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Adjusting the Output Voltage

A resistor divider connected to the FB pin (pin 9) sets the output voltage of the TPSM53602. The output voltage adjustment range is from 1 V to 7 V. Figure 7-1 shows the feedback resistor connections for setting the output voltage. The recommended value of R FBT is 10 k Ω. The value for R FBB can be calculated using Equation 1. Table 7-1 lists the standard resistor values for several output voltages. The minimum required output capacitance for each output voltage is also included in Table 7-1. The capacitance values listed represent the effective capacitance, taking into account the effects of DC bias and temperature variation. RFBB = (VOUT ± 1) )10 (1) AGND VOUT FB RFBT 10k RFBB Figure 7-1. Setting the Output Voltage Table 7-1. Setting the Output Voltage VOUT (V) RFBB (kΩ)(1) COUT(MIN) (µF) (EFFECTIVE) VOUT (V) RFBB (kΩ)(1) COUT(MIN) (µF) (EFFECTIVE) 1.0 open 150 3.0 4.99 46 1.1 100 137 3.3 4.32 42 1.2 49.9 125 4.0 3.32 34 1.3 33.2 114 4.5 2.87 30 1.4 24.9 105 5.0 2.49 27 1.5 20.0 98 5.5 2.21 24 1.8 12.4 80 6.0 2.00 22 2.0 10.0 72 6.5 1.82 20 2.5 6.65 56 7.0 1.65 19 (1) RFBT = 10.0 kΩ

7.3.2 Switching Frequency

The switching frequency of the TPSM53602 is set to 1.4 MHz, internal to the device. The switching frequency cannot be adjusted. When the load current is high enough and the device is operating in PWM mode, the device operates at a fixed frequency. As the load current drops and the device switches to PFM mode, the switching frequency is reduced resulting in reduced power dissipation. See Section 7.4.2 for typical information on when the device switches from PWM mode to PFM mode. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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7.3.3 Input Capacitors

The TPSM53602 requires a minimum input capacitance of 20 μF (2 × 10 μF) of ceramic type. High-quality, ceramic-type X5R or X7R capacitors with sufficient voltage rating are recommended. TI recommends an additional 47 µF of non-ceramic capacitance for applications with transient load requirements. The voltage rating of input capacitors must be greater than the maximum input voltage. Table 7-2. Recommended Input Capacitors VENDOR(1) SERIES SIZE PART NUMBER CAPACITOR CHARACTERISTICS VOLTAGE RATING (V) CAPACITANCE (3) (µF) Murata X5R 1206 GRT31CR61H106ME01L 50 10 TDK X5R 1206 CGA5L3X5R1H106M160AB 50 10 TDK X7R 1206 CGA5L1X7R1H106K160AC 50 10 Murata X7R 1210 GRM32ER71H106KA12L 50 10 TDK X7R 1210 C3225X7R1H106M250AC 50 10 (1) Capacitor Supplier Verification, RoHS, Lead-free, and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. (2) Maximum ESR at 100 kHz, 25°C. (3) Standard capacitance values

7.3.4 Output Capacitors

Table 7-1 lists the TPSM53602 minimum output capacitance. The effects of DC bias and temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package size, voltage rating, and dielectric material contributes to differences between the standard rated value and the actual effective value of the capacitance. When adding additional capacitance above C OUT(min), the capacitance can be ceramic type, low-ESR polymer type, or a combination of the two. See Table 7-3 for a preferred list of output capacitors by vendor. Table 7-3. Recommended Output Capacitors VENDOR(1) SERIES PART NUMBER CAPACITOR CHARACTERISTICS VOLTAGE RATING (V) CAPACITANCE (2) (µF) ESR(2) (mΩ) TDK X5R C3225X5R0J476K 6.3 47 2 Murata X7R GCM32ER70J476KE19L 6.3 47 2 Murata X5R GRM21BR61A476ME15L 10 47 2 TDK X5R C3216X5R1A476M160AB 10 47 2 Murata X7R GRM32ER71A476KE15L 10 47 2 Murata X5R GRM32ER61C476K 16 47 3 TDK X5R C3225X5R0J107M 6.3 100 2 Murata X5R GRM32ER60J107M 6.3 100 2 Murata X5R GRM32ER61A107M 10 100 2 Kemet X5R C1210C107M4PAC7800 16 100 2 Panasonic POSCAP 6TPE100MI 6.3 100 18 Panasonic POSCAP 10TPF150ML 10 150 15 Panasonic POSCAP 6TPF220M9L 6.3 220 9 Panasonic POSCAP 6TPF330M9L 6.3 330 9 Panasonic POSCAP 6TPE470MAZU 6.3 470 35 (1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. (2) Standard capacitance values. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM53602

7.3.5 Output On/Off Enable (EN)

The voltage on the EN pin provides electrical ON/OFF control of the device. This input features precision thresholds, allowing the use of an external voltage divider to provide a programmable UVLO (see Section 7.3.6). Applying a voltage of V EN ≥ VEN-LDO_H causes the device to enter standby mode, powering the internal LDO, but not producing an output voltage. Increasing the EN voltage to V EN-H fully enables the device, allowing it to enter start-up mode and beginning the soft-start period. When the EN input is brought below V EN-H by VEN-HYS, the regulator stops running and enters standby mode. Further decrease in the EN voltage to below V EN-LDO-L completely shuts down the device. Figure 7-2 shows this behavior. The values for the various EN thresholds can be found in Section 6.5. EN V5V VEN-H VEN-H ± VEN-HYS VEN-LDO-L VOUT VOUT VEN-LDO-H Figure 7-2. Precision Enable Behavior The EN pin cannot be open circuit or floating. The simplest way to enable the operation of the TPSM53602 is to connect the EN pin to VIN directly as shown in Figure 7-3. This allows self start-up of the TPSM53602 when VIN is within the operation range. If an application requires controlling the EN pin, an external logic signal can be used to drive EN pin as shown in Figure 7-4. Applications using an open drain/collector device to interface with this pin require a pullup resistor to a voltage above the enable threshold. EN VIN PGND VIN Figure 7-3. Enabling the Device EN PGND Figure 7-4. Typical Enable Control TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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7.3.6 Programmable Undervoltage Lockout (UVLO)

The TPSM53602 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 3.55 V (typical) with a typical hysteresis of 500 mV. If an application requires a higher UVLO threshold, a resistor divider can be placed between VIN, the EN pin, and AGND as shown in Figure 7-5 . The enable rising threshold (V EN-H) is 1.23 V (typ) with 100 mV (typ) hysteresis. Table 7-4 lists recommended resistor values for RENT and RENB to adjust the ULVO voltage. To ensure proper start-up and reduce input current surges, TI recommends to set the UVLO threshold to approximately 80% to 85% of the minimum expected input voltage. EN VIN RENT AGND VIN RENB Figure 7-5. Adjustable UVLO Table 7-4. Resistor Values for Adjusting UVLO VIN UVLO (V) 6.5 10 15 20 25 30 RENT (kΩ) 100 100 100 100 100 100

7.3.7 Power Good (PGOOD)

The TPSM53602 has a built-in power-good signal (PGOOD) which indicates whether the output voltage is within its regulation range. The PGOOD pin is an open-drain output that requires a pullup resistor to a nominal voltage source of 18 V or less. The internal 5-V LDO output (V5V pin) can be used as the pullup voltage source. A typical pullup resistor value is between 10 k Ω and 100 kΩ. The maximum recommended PGOOD sink current is 3 mA. Once the output voltage rises above 94% of the set voltage, the PGOOD pin rises to the pullup voltage level. The PGOOD pin is pulled low when the output voltage drops lower than 92% or rises higher than 107% of the nominal set voltage. See Figure 7-6 for typical power-good thresholds. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM53602

107% 105% 92% 94% High Low Figure 7-6. Power-good Flag

7.3.8 Light Load Operation

In light load conditions, the device turns on the high-side MOSFET until the inductor current reaches a controlled minimum value of approximately 1 A. As the input voltage decreases, reducing the voltage headroom between VIN and VOUT, the amount of time required to reach this minimum current increases. During this time, additional energy flows from V IN to V OUT, resulting in increased output voltage ripple. To eliminate this behavior, the EN UVLO function must be used to maintain at least 1 V of headroom above V OUT. Alternatively, additional output capacitance can be added to reduce the output voltage ripple in applications that operate at light loads with very low VIN to VOUT headroom.

7.3.9 Voltage Dropout

Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output voltage regulation while providing the rated output current. To ensure the TPSM53602 maintains output voltage regulation over the operating temperature range, the minimum VIN is 3.8 V or (VOUT + 1 V), whichever is greater. The TPSM53602 operates in a frequency foldback mode when the dropout voltage is less than the recommendation above. Frequency foldback reduces the switching frequency to allow the output voltage to maintain regulation as input voltage decreases. At light load, the TPSM53602 operates in PFM mode which is a reduced frequency operation. See Section 7.4.2 for more information on PFM mode. Figure 7-7 through Figure 7-12 show typical dropout voltage and frequency foldback curves for 3.3 V, 5 V, and 7 V outputs at TA = 25°C. Note As ambient temperature increases, dropout voltage and frequency foldback occur at higher input voltage. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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Product Folder Links: TPSM53602

7.3.10 Overcurrent Protection (OCP)

The TPSM53602 is protected from overcurrent conditions. Cycle-by-cycle current limit is used for overloads while hiccup mode is used for short circuits. Hiccup mode is activated if a fault condition persists on the output. Hiccup mode reduces power dissipation under severe overcurrent conditions and prevents overheating and potential damage to the device. In hiccup mode, the regulator is shut down and kept off for 94 ms typical before the TPSM53602 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Once the fault is removed, the module automatically recovers with a normal soft-start power up. The typical current limit threshold for the TPSM53602 varies slightly as a function of input voltage and output voltage. Figure 7-13 shows the typical current limit threshold for several output voltages over the input voltage range. Input Voltage (V) Typical Current Limit (A) 0 5 10 15 20 25 30 35 40 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 D025 VOUT 1 V 1.8 V 3.3 V 5 V 7 V Figure 7-13. Current Limit Threshold

7.3.11 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 165°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 148°C typically. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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Product Folder Links: TPSM53602

7.4 Device Functional Modes

7.4.1 Active Mode

The TPSM53602 is in active mode when VIN is above the turnon threshold and the EN pin voltage is above the EN high threshold. The most direct way to enable the TPSM53602 is to connect the EN pin to VIN. This allows self start-up of the TPSM53602 when the input voltage is in the operation range of 3.8 V to 36 V. Connecting a resistor divider between VIN, EN, and AGND adjusts the UVLO to delay the turn on until V IN is closer to its regulated voltage.

7.4.2 Auto Mode

In auto mode, the device moves between Pulse-Width Modulation (PWM) and Pulse-Frequency Modulation (PFM) as the load changes. At light loads, the regulator operates in PFM mode. At higher loads, the mode changes to PWM mode. The typical load current for which the device moves from PFM to PWM can be found in Figure 7-14 and Figure 7-15. The output current at which the device changes modes depends on the input voltage and the output voltage. For output currents above the curve, the device is in PWM mode. If the curve is a solid line, the PWM switching frequency is 1.4 MHz nominal. If the curve is a dashed line, the PWM switching frequency is reduced due to the minimum on-time of the internal controller to maintain output voltage regulation. For currents below the curves, the device is in PFM mode. For applications where the switching frequency must be known for a given condition, the above mentioned effects must be carefully tested before the design is finalized. In PWM mode, the regulator operates at a constant frequency using PWM to regulate the output voltage. While operating in this mode, the output voltage is regulated by switching at a constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line and load regulation and low output voltage ripple. In PFM mode, the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The duration of the burst and the actual switching frequency depends on the input voltage, output voltage, and load current. The frequency of these bursts is adjusted to regulate the output while diode emulation is used to maximize efficiency. This mode provides high light-load efficiency by reducing the amount of input supply current required to regulate the output voltage at small loads. However, in this mode, expect larger output voltage ripple and variable switching frequency. Figure 7-14. PFM/PWM Thresholds (3.3 V, 5 V, and 7 V) Figure 7-15. PFM/PWM Thresholds (1 V and 1.8 V)

7.4.3 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPSM53602. When the EN pin voltage is below the EN low threshold, the device is in shutdown mode. In shutdown mode, the standby current is 5 μA typical. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM53602

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPSM53602 is a synchronous, step-down, DC/DC power module. It is used to convert a higher DC voltage to a lower DC voltage with a maximum output current of 2 A. The TPSM53602 can be configured in a negative output voltage, inverting buck-boost (IBB) topology. For more details, see the Negative Output Voltage using the TPSM53602/3/4 application note. The following design procedure can be used to select components for the TPSM53602. Alternately, the WEBENCH® software can be used to generate complete designs. When generating a design, the WEBENCH® software uses an iterative design procedure and accesses comprehensive databases of components. See www.ti.com for more details.

8.2 Typical Application

The TPSM53602 only requires a few external components to convert from a wide input voltage supply range to a wide range of output voltages. Figure 8-1 shows a basic TPSM53602 schematic for a typical design. VIN PGND VOUT 2.49 kO FB 10 kO PGOOD EN V5V TPSM53602 AGND VOUT = 5 V 47 µF 10 V 47 µF 10 V VIN = 24 V 10 µF 50 V 100 kO 100 kO 10 µF 50 V Figure 8-1. TPSM53602 Typical Schematic

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1 as the input parameters and follow the design procedures in Section 8.2.2. Table 8-1. Design Example Parameters DESIGN PARAMETER VALUE Input voltage VIN 24 V typical Output voltage VOUT 5 V Output current rating 2 A TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM53602 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM53602 device is externally adjustable using a resistor divider. The recommended value of RFBT is 10 kΩ. The value for RFBB can be selected from Table 7-1 or calculated using Equation 2: RFBB = (VOUT ± 1) )10 (2) For the desired output voltage of 5 V, the formula yields a value of 2.5 k Ω. Choose the closest available value of 2.49 kΩ for RFBB.

8.2.2.3 Input Capacitors

The TPSM53602 requires a minimum input capacitance of 20 µF (or 2 × 10 μF) ceramic type. High-quality ceramic type X5R or X7R capacitors with sufficient voltage rating are recommended. An additional 47 µF of non-ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of the input capacitors must be greater than the maximum input voltage. For this design example, two 10-µF, 50-V, ceramic capacitors are used.

8.2.2.4 Output Capacitor Selection

The TPSM53602 requires a minimum amount of output capacitance for proper operation. The minimum amount of required output varies depending on the output voltage. See Table 7-1 for the required output capacitance. For this design example, two 47-µF, 10-V, ceramic capacitors are used. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM53602

8.2.3 Application Curves

VIN = 24 V VOUT = 5 V COUT = 2 × 47 µF Figure 8-2. Enable Turn-ON VIN EN VOUT PGOOD VIN = 24 V VOUT = 5 V COUT = 2 × 47 µF Figure 8-3. Enable Turn-OFF VOUT IOUT VIN = 24 V VOUT = 5 V COUT = 2 × 47 µF IOUT = 0.5 A to 1.5 A Slew rate: 1 A/µs Figure 8-4. Transient Response

9 Power Supply Recommendations

The TPSM53602 is designed to operate from an input voltage supply range between 3.8 V and 36 V. This input supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause a high enough drop at the TPSM53602 supply voltage that can cause a false UVLO fault triggering and system reset. If the input supply is located more than a few centimeters from the TPSM53602, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. The typical amount of bulk capacitance is a 47-µF electrolytic capacitor. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

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Product Folder Links: TPSM53602

10 Layout

The performance of any switching power supply depends as much on the layout of the PCB as the component selection. The following guidelines help users design a PCB with the best power conversion performance, optimal thermal performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 10-1 through Figure 10-3 shows a typical PCB layout. The following are some considerations for an optimized layout.

Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
Locate additional output capacitors between the ceramic capacitor and the load.
Connect AGND to PGND at a single point.
Place RFBT and RFBB as close as possible to the FB pin.
Use multiple vias to connect the power planes to internal layers.
Download the EVM Design Files for fast board design

10.2 Layout Examples

Figure 10-1. Typical Top-Layer Layout Figure 10-2. Typical Layer-2 Layout Figure 10-3. Typical PGND Layer www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM53602

10.3 Theta JA versus PCB Area

The amount of PCB copper affects the thermal performance of the device. Figure 10-4 shows the effects of copper area on the junction-to-ambient thermal resistance (R θJA) of the TPSM53602. The junction-to-ambient thermal resistance is plotted for a 4-layer PCB with PCB area from 30 cm2 to 80 cm2. To determine the required copper area for an application: 1. Determine the maximum power dissipation of the device in the application by referencing the power dissipation graphs in Section 6.6 through Section 6.9. 2. Calculate the maximum RθJA using Equation 3 and the maximum ambient temperature of the application. A(max) JA D(max)

125 C T )R ( C / W) PT

q q ( (3) 3. Reference Figure 10-4 to determine the minimum required PCB area for the application conditions. PCB Area (cm²) Theta JA (°C/W) 30 40 50 60 70 80 D047 4-layer PCB Figure 10-4. RθJA versus PCB Area (per layer) TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

Product Folder Links: TPSM53602

10.4 Package Specifications

Flammability Meets UL 94 V-O MTBF Calculated Reliability Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 89.3 MHrs

10.5 EMI

The TPSM53602 is compliant with EN55011 Class-B radiated emissions. Figure 10-5 and Figure 10-6 show typical examples of radiated emissions plots for the TPSM53602. The graphs include the plots of the antenna in the horizontal and vertical positions. EMI plots were measured using the standard TPSM53602EVM with no input filter. Figure 10-5. Radiated Emissions 24-V Input, 5-V Output, 2-A Load www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM53602

Figure 10-6. Radiated Emissions 12-V Input, 5-V Output, 2-A Load TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

Product Folder Links: TPSM53602

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

11.1.2.1 Custom Design With WEBENCH® Tools

Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following: Texas Instruments, Negative Output Voltage using the TPSM53602/3/4 application report

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. are registered trademarks of Texas Instruments. All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. www.ti.com TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM53602

11.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPSM53602 SNVSBD0B – DECEMBER 2019 – REVISED SEPTEMBER 2021 www.ti.com

Product Folder Links: TPSM53602

www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPSM53602RDAR Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 TPSM53602 TPSM53602RDAR.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 TPSM53602 TPSM53602RDAR.B Active Production B3QFN (RDA) | 15 1000 | LARGE T&R - Call TI Call TI -40 to 125 TPSM53602RDARG4 Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 TPSM53602 TPSM53602RDARG4.A Active Production B3QFN (RDA) | 15 1000 | LARGE T&R Yes NIPDAU Level-3-245C-168 HR -40 to 125 TPSM53602 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSM53602RDAR B3QFN RDA 15 1000 336.0 336.0 48.0 TPSM53602RDARG4 B3QFN RDA 15 1000 336.0 336.0 48.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 5.1 4.9 5.6 5.4

4.1 MAX

2.6 TYP

8X 0.65 2X 0.725 1.43 2X 0.975 2.5 0.05 2.5 0.05 4.6 0.05 1.5 0.05 3X 1.3 1.1 10X 0.6 0.4 1.3 1.1 4X 0.6 0.4 10X 0.45 0.25 (0.16) TYP B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PIN 1 INDEX AREA 0.08 C SEATING PLANE PKG PKG

0.1 C A B

0.05 C 0.05 C PIN 1 ID SCALE 1.800 AB C

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(4.7) 2X (4) (1) TYP (1) TYP (4.6) (2.5) (1.5) (2.5) 4X (1.4) 4X (0.5) 10X (0.7) 10X (0.35) 2X (1.43) 8X (0.65) 2X (0.725) 2X (0.975) (R0.05) TYP ( 0.2) VIA TYP B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 16X PKG PKG SCALE 30.000 SOLDER MASK DETAILS EXPOSED METAL METAL EDGESOLDER MASK OPENING EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.65) 10X (0.3) 4X (0.6) (0.65) (0.95) 4X (0.475) 2X (4) (4.7) 2X (0.975) 4X (1.35) 4X (0.45) 2X (1.43) 8X (0.65) 2X (0.725) (R0.05) TYP (1.15) 4X (0.425) 4X (1.675) 4X (0.625) B3QFN - 4.1 mm max heightRDA0015A PLASTIC QUAD FLATPACK - NO LEAD 4224086/C 03/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 15: 56% PRINTED SOLDER COVERAGE BY AREA SCALE: 16X PKG PKG

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

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