TPSM365R15FRDNR

TPSM365R15 TI | Alldatasheet

Document overview

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Technical content

TPSM365R1x 3-V to 65-V, 100-mA and 150-mA Wide VIN Synchronous Buck Converter Power Module Optimized for Size and Light Load Efficiency

1 Features

• Functional Safety-Capable – Documentation available to aid functional safety system design
• Versatile synchronous buck DC/DC module: – Integrated MOSFETs, inductor, and controller – 3-V to 65-V wide input voltage range – Up to 70-V input transient – –40°C to +125°C junction temperature range – 4.5-mm × 3.5-mm × 2-mm overmolded package – Frequency adjustable from 200 kHz to 2.2 MHz using the RT pin
• Optimized for ultra-low EMI requirements: – Pseudo-random spread spectrum reduces peak emissions – Pin selectable FPWM mode for constant frequency at light loads with MODE/SYNC pin – Frequency synchronization with MODE/SYNC pin – CISPR11 class B capable
• Designed for scalable industrial power supplies: – Pin compatible family with TPSM365R3 (65 V, 300 mA), TPSM365R6 (65 V, 600 mA), TPSM33615 (36 V, 1.5 A), and TPSM33625 (36 V, 2.5 A)
• Inherent protection features for robust design – Precision enable input and open-drain PGOOD indicator for control, sequencing, and VIN UVLO – Overcurrent and thermal shutdown protections
• Create a custom design using the TPSM365R15 with the WEBENCH® Power Designer

2 Applications

• Factory automation
• Building automation
• Appliances VIN GND VIN VOUT VOUT FB COUT SW EN VCC TPSM365R15 CIN CVCC RT BOOT PGOOD Simplified Schematic

3 Description

The TPSM365R1 and TPSM365R15 are 65-V, 100- mA, and 150-mA synchronous step-down DC/DC power modules that combine power MOSFETs, integrated inductor, and boot capacitor in a compact and easy-to-use 3.5-mm × 4.5-mm × 2-mm, 11-pin QFN package. The small HotRod™ QFN package technology enhances the thermal performance and results in low EMI. The device features ultra-low operating I Q of 4- μA at no load (24 V IN to 3.3 VOUT). The TPSM365R1x support fixed 3.3-V and 5-V outputs, as well as adjustable output voltages ranging from 1 V to 16 V. The TPSM365R1x use peak current mode control architecture with internal compensation to maintain stable operation with minimal output capacitance. With a resistor from the RT pin to ground, the switching frequency is programmed to operate at any desired point over a wide range from 200 kHz to 2.2 MHz. The precision EN/UVLO feature allows precise control of the device during the start-up and shutdown. The PGOOD flag, with built-in glitch filter and delayed release, offers a true indication of the system status, eliminating the requirement for an external voltage supervisor. The compact design size and rich feature set of TPSM365R1x simplifies implementation for a wide range of industrial applications.

Package Information

PART NUMBER PACKAGE (1) PACKAGE SIZE(2) TPSM365R15 RDN (QFN-HR, 11) 4.50 mm × 3.50 mm TPSM365R1(3) (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) Preview information (not Production Data). Device Information PART NUMBER RATED OUTPUT CURRENT (1) TPSM365R15 150 mA TPSM365R1(2) 100 mA (1) See the Device Comparison Table. (2) Preview information (not Production Data). TPSM365R15 SNVSCI1 – OCTOBER 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

10.3 Receiving Notification of Documentation Updates..41

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES October 2023 * Initial Release TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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5 Device Comparison Table

(1) RATED CURRENT OUTPUT VOLTAGE EXTERNAL SYNC FSW SPREAD SPECTRUM TPSM365R15RDNR 150 mA Fixed 3.3 V / Adjustable (1 V – 16 V) No (Default PFM at light load) Adjustable with RT resistor Yes TPSM365R15FRDNR(2) 150 mA Fixed 5 V / Adjustable (1 V – 16 V) Yes (PFM / FPWM Selectable) Fixed 1 MHz Yes TPSM365R1RDNR(2) 100 mA Fixed 3.3 V / Adjustable (1 V – 16 V) No (Default PFM at light load) Adjustable with RT resistor Yes TPSM365R1FRDNR(2) 100 mA Fixed 5-V / Adjustable (1 V – 16 V) Yes (PFM / FPWM Selectable) Fixed 1 MHz Yes (1) For more information on device orderable part numbers, see Device Nomenclature. Contact TI for details and availability of other device options. (2) Preview information (not Production Data). www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSM365R15

6 Pin Configuration and Functions

MODE/SYNC(A) RT(B) PGOOD EN VIN FB/ BIAS VCC BOOT SW GND 11 9 SWVOUT A. See Device Comparison Table for more details. Pin 11 trimmed and factory-set for externally adjustable switching frequency RT variants only B. Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only. Figure 6-1. RDN Package, 11-Pin QFN-FCMOD, Top View Table 6-1. Pin Functions PIN TYPE DESCRIPTION NO. NAME

1 PGOOD A

Open-drain power-good flag output. Connect to suitable voltage supply through a current limiting resistor. High = power OK, low = power bad. This pin goes low when EN = low. This pin can be open or grounded when not used. 2 EN A Enable input to regulator. High = ON, Low = OFF. Can be connected directly to VIN. Do not float this pin. 3 VIN P Input supply to regulator. Connect a high-quality bypass capacitor, CIN, or capacitors directly to this pin and GND. 4 VOUT P Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and connect external output capacitors between the pin and GND. 5, 6 SW P Power module switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.

7 BOOT P

Bootstrap pin for internal high-side driver circuitry. Do not place any external component on this pin or connect to any signal. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage.

8 VCC P

Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.

9 FB/BIAS A

Feedback input. When operating as an adjustable output device, connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to GND. When connecting to a feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See Output Voltage Selection for how to select feedback resistor divider values. Check Device Comparison Table for more details. When operating with a fixed output voltage, connect this pin directly to the VOUT rail. This connection sets the output voltage to a fixed value and biases the internal circuitry. Do not float this pin or connect to ground. 10 GND G Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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Table 6-1. Pin Functions (continued) PIN TYPE DESCRIPTION NO. NAME

11 RT or

As the RT variant, the switching frequency can be adjusted from 200 kHz to 2.2 MHz. As the MODE/SYNC variant, the part can operate in user-selectable PFM/FPWM mode and can be synchronized to an external clock. See Section 8.3.2 for details. Do not float this pin. A = Analog, P = Power, G = Ground www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSM365R15

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage VIN to GND –0.3 70 V EN to GND –0.3 70 V SW to GND –0.3 70.3 V RT to GND –0.3 5.5 V Voltage FB to GND –0.3 16 V Voltage PGOOD to GND 0 20 V BOOT to SW –0.3 5.5 V Voltage VCC to GND –0.3 5.5 V Voltage VOUT to GND –0.3 16 V Peak reflow case temperature 260 °C Maximum number of reflows allowed 3 Mechanical shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500 G Mechanical vibration Mil-STD-883D, Method 2007.2, 20 to 2000 Hz 20 G TJ Operating Junction Temperature –40 125 °C TA Operating Ambient temperature -40 105 °C Tstg Storage Temperature –55 125 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of -40°C to 125°C (unless otherwise noted). (1) (2) MIN NOM MAX UNIT Input voltage VIN Input voltage range after startup 3 65 V Output voltage VOUT Adjustable output voltage range 1 16 V Output current IOUT (TPSM365R15) Load current range (3) 0 0.15 A Output current IOUT (TPSM365R1) Load current range (3) 0 0.1 A Frequency setting RT Selectable Frequency range with RT 0.2 2.2 MHz Temperature TJ Operating Junction Temperature -40 125 ℃ Temperature TA Operating Ambient Temperature -40 105 ℃ (1) Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see the Electrical Characteristics table. (2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C. (3) Maximum continuous DC current may be de-rated when operating with high switching frequency or high ambient temperature. See Applications section for details. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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7.4 Thermal Information

THERMAL METRIC(1) TPSM365R15 / TPSM365R1 UNITRDN

11 PINS

RθJA Junction-to-ambient thermal resistance (TPSM365R15EVM) 56.4 °C/W RθJA Junction-to-ambient thermal resistance (2) 42.9 °C/W ψJT Junction-to-top characterization parameter (3) 4.4 °C/W ψJB Junction-to-board characterization parameter (4) 17.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The value of RθJA given in this table is valid for comparison with other packages and can not be used for design purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the performance obtained in an actual application. (3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT ∙ Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJB ∙ Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1-mm from the device.

7.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VIN_R Minimum operating input voltage (rising) Rising threshold 3.4 3.55 V VIN_F Minimum operating input voltage (falling) Once operating; Falling threshold 2.45 3.0 V ISD_13p5 Shutdown quiescent current; measured at VIN pin (2) VEN = 0 V; VIN = 13.5 V 0.55 1.1 µA ISD_24p0 Shutdown quiescent current; measured at VIN pin (2) VEN = 0 V; VIN = 24 V 1 1.7 µA IQ_13p5_Fixed Non-switching input current; measured at VIN pin (2) VIN = VEN = 13.5 V; VOUT/FB = 5.25 V, VMODE/ SYNC = 0 V; Fixed output 0.25 0.672 1.05 µA IQ_13p5_Adj Non-switching input current; measured at VIN pin (2) VIN = VEN = 13.5 V; VFB = 1.05 V, VMODE/SYNC = 0 V; Adjustable output 13 17 23 µA IQ_24p0_Fixed Non-switching input current; measured at VIN pin (2) VIN = VEN = 24 V; VOUT/FB = 5.25 V, VMODE/SYNC = 0 V; Fixed output 0.8 1.2 1.7 µA IQ_24p0_Adj Non-switching input current; measured at VIN pin (2) VIN = VEN = 24 V; VFB = 1.05 V, VMODE/SYNC = 0 V; Adjustable output 14 18 22 µA IB_13p5 Current into BIAS pin (not switching) (2) VIN = 13.5 V, VOUT/FB = 5.25 V, VRT = 0 V; Fixed output 12 17 24 µA IB_24p0 Current into BIAS pin (not switching) (2) VIN = 24 V, VOUT/FB = 5.25 V, VMODE/SYNC = 0 V; Fixed output 12 18 24 µA ENABLE (EN PIN) VEN-WAKE Enable wake-up threshold 0.4 V VEN-VOUT Precision enable high level 1.16 1.263 1.36 V VEN-HYST Enable threshold hysteresis 0.3 0.35 0.4 V ILKG-EN Enable input leakage current VEN = 3.3 V 0.7 8 nA INTERNAL LDO VCC Internal VCC voltage 3.6 V ≤ VIN ≤ 65 V; Adjustable output 3.1 3.15 3.26 V www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSM365R15

7.5 Electrical Characteristics (continued)

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ICC Bias regulator current limit 60 120 mA VCC-UVLO Internal VCC undervoltage lockout VCC rising under voltage threshold 3 3.3 3.65 V VCC-UVLO-HYST Internal VCC under voltage lock-out hysteresis Hysteresis below VCC-UVLO 0.3 0.8 1.2 V CURRENT LIMITS ISC-150mA Short circuit high side current limit (3) 150 mA version 210 250 298 mA ILS-LIMIT-150mA Low side current limit (3) 150 mA version 150 175 204 mA IPEAK-MIN-150mA Minimum Peak Inductor Current (3) PFM Operation, 150 mA version; Duty Cycle = 0% 55 70 85 mA IL-NEG-150mA Sink current limit (negative) (3) FPWM mode -200 -175 -150 mA IZC Zero cross current (3) Auto mode 0 2.5 5 mA MOSFETS RDSON-HS High-side MOSFET on-resistance Load = 100 mA 2.2 Ω RDSON-LS Low-side MOSFET on-resistance Load = 100 mA 1 Ω VBOOT-UVLO BOOT - SW UVLO threshold (4) 2.14 2.3 2.42 V OSCILLATOR (RT) fOSC_2p2MHz Internal oscillator frequency RT = GND 2.1 2.2 2.3 MHz fOSC_1p0MHz Internal oscillator frequency RT = VCC 0.93 1 1.05 MHz fADJ_400kHz Accuracy of external frequency, 400 kHz RT = 39.2 kΩ 0.34 0.4 0.46 MHz VOLTAGE FEEDBACK (VOUT/FB PIN) VOUT Output Voltage Accuracy for fixed VOUT VOUT = 5-V, VIN = 5.5 V to 65 V, FPWM 4.93 5 5.08 V VREF Internal reference voltage VIN = 3.6 V to 65 V, FPWM mode 0.985 1 1.01 V IFB FB input current Adjustable output, FB = 1 V 1 30 nA SOFT START tSS Time from first SW pulse to VFB at 90% of VREF VIN ≥ 3.6 V 1.85 2.58 3.2 ms POWER GOOD PG-OV PGOOD upper threshold - rising % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 106 107 110 % PG-UV PGOOD lower threshold - falling % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 93 94 96.5 % PG-HYS PGOOD hysteresis - rising/falling % of FB (Adjustable output) or % of VOUT/FB (Fixed output) 0.8 1.2 1.8 % VPG-VALID Minimum input voltage for proper PG function 0.7 0.9 2 V RPG-EN5p0 PGOOD pull down resistance VEN = 5.0 V, 1 mA pull-up current 20 40 70 Ω RPG-EN0 PGOOD pull down resistance VEN = 0 V, 1 mA pull-up current 15 24 46 Ω tRESET_FILTER Glitch filter time constant for PG function 15 25 40 µs tPGOOD_ACT Delay time to PG high signal 1.7 1.956 2.16 ms PWM LIMITS (SW) tON-MIN Minimum switch on-time VIN = 24 V, IOUT = 100 mA 40 57 80 ns tOFF-MIN Minimum switch off-time 40 58 77 ns TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 24 V. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tON-MAX Maximum switch on-time HS timeout in dropout 7.6 9 9.8 µs (1) MIN and MAX limits are 100% production tested at 25ºC. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation. (3) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application. (4) When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge the boot capacitor.

7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN) ISUPPLY Input supply current when in regulation VIN = 13.5 V, VBIAS = 3.3-V VOUT, IOUT = 0 A, PFM mode (fixed output voltage) 6.5 µA ISUPPLY Input supply current when in regulation VIN = 24 V, VBIAS = 3.3-V VOUT, IOUT = 0 A, PFM mode (fixed output voltage) 4 µA DMAX Maximum switch duty cycle (1) 98 % SPREAD SPECTRUM fSSS Frequency span of spread spectrum operation - largest deviation from center frequency (2) Spread spectrum active ±2 % fPSS Spread spectrum pseudo random pattern frequency (2) 0.98 1.5 Hz THERMAL SHUTDOWN TSD-R Thermal shutdown rising Shutdown threshold 158 168 180 °C TSD-HYS Thermal shutdown hysteresis 8 10 15 °C (1) In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: fMIN = 1 / (tON-MAX + TOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN). (2) Specified by design. Not production tested. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSM365R15

7.7 Typical Characteristics

Unless otherwise specified, the following conditions apply: TA = 25°C, VIN = 13.5 V. Ambient Temperature (°C) Shutdown Current (nA) -40 -20 0 20 40 60 80 100 120 140 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 VIN = 13.5 V VIN = 24 V Figure 7-1. Shutdown Supply Current vs Ambient Temperature Ambient Temperature (°C) Feedback Voltage (V) -40 -20 0 20 40 60 80 100 120 140 3.291 3.292 3.293 3.294 3.295 3.296 3.297 3.298 3.299 3.3 Figure 7-2. 3.3-V Feedback Voltage vs Temperature Ambient Temperature (°C) Resistance (Ohms) -40 -20 0 20 40 60 80 100 120 140 0.5 0.75 1.25 1.5 1.75 2.25 2.5 2.75 Low Side RDSON High Side RDSON Figure 7-3. HSFET and LSFET RDSON vs Temperature Ambient Temperature (°C) VEN-VOUT (V) -40 -20 0 20 40 60 80 100 120 140 1.254 1.2555 1.257 1.2585 1.26 1.2615 1.263 1.2645 1.266 1.2675 1.269 1.2705 1.272 1.2735 1.275 Figure 7-4. Precision Enable High Threshold vs Temperature Ambient Temperature (°C) Minimum On-Time (ns) -40 -20 0 20 40 60 80 100 120 140 Figure 7-5. Minimum On-Time vs Temperature Ambient Temperature (°C) Current Limit (mA) -40 -20 0 20 40 60 80 100 120 140 140 150 160 170 180 190 200 210 220 230 240 250 260 Low Side Limit High Side Limit Figure 7-6. High-Side (Peak) and Low-Side Valley Current Limits TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The TPSM365R1x is an easy-to-use, synchronous buck, DC/DC power module that operates from a 3-V to 65-V supply voltage. With an integrated power controller, inductor, and MOSFETs, the TPSM365R1x delivers up to 100-mA or 150-mA DC load current with high efficiency and ultra-low input quiescent current in a very compact design size. The TPSM365R1x can operate over a wide range of switching frequencies and duty ratios. If the minimum ON-time or OFF-time cannot support the desired duty ratio, the switching frequency is reduced automatically, maintaining the output voltage regulation. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. The TPSM365R1x module also includes inherent protection features for robust system requirements:

• An open-drain PGOOD indicator for power-rail sequencing and fault reporting
• Precision enable input with hysteresis, providing: – Programmable line undervoltage lockout (UVLO) – Remote ON and OFF capability
• Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
• Current limiting implemented by cycle-by-cycle peak and valley current limits
• Thermal shutdown with automatic recovery These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for a simple layout, requiring few external components. See Layout for a layout example. The TPSM365R1x incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design which enables a shielded switch-node layout that mitigates radiated EMI
• A programmable switching frequency from 200 kHz to 2.2 MHz enables optimization of external passives and promotes the avoidance of noise sensitive bands
• Pseudo-Random Spread Spectrum (PRSS) modulation reduces peak emissions
• Clock synchronization via the MODE/SYNC pin and FPWM mode enable constant switching frequency across the load current range Together, these features eliminate the need for any common-mode choke, shielding, and input filter inductor, greatly reducing the complexities and cost of the EMI/EMC mitigation measures. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSM365R15

8.2 Functional Block Diagram

/SYNC EN CONTROL LOGIC and DRIVER ENABLE GND VOUT VIN LDO MAX and MIN LIMITS ERROR AMPLIFIER + HS CURRENT SENSE SLOPE COMPENSATION VREF VCC HS CURRENT LIMIT CLOCK FSW FOLDBACK MIN LS CURRENT LIMIT THERMAL SHUTDOWN CLOCK COMP SOFT- START and BANDGAP SYS ENABLE VCC UVLO VCC UVLO GND VIN FPWM or AUTO RT LS CURRENT LIMIT SYS ENABLE TSD TSD TSD LS CURRENT SENSEVOUT UV/OV VOUT UV/OV RT VARIANTS MODE/SYNC VARIANTS ADJ. OUTPUT VOLTAGE CONFIGURATION FIXED OUTPUT VOLTAGE CONFIGURATION FIXED OUTPUT VOLTAGE CONFIGURATION ADJ. OUTPUT VOLTAGE CONFIGURATION FIXED OUTPUT VOLTAGE CONFIGURATION BIAS FB BIAS SYS ENABLE BOOT 47uH SW 0.1 μF TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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8.3 Feature Description

8.3.1 Enable, Shutdown, and Start-Up

The voltage at the EN/UVLO pin controls the startup voltage and shut-down voltage of the TPSM365R1x. There are three distinct modes set by the EN/UVLO pin; shutdown, standby, and active. As long as the EN/UVLO pin voltage is less than V EN-WAKE the device is shutdown mode. During shutdown mode, the input current drawn by the device typically is 0.55 µA (V IN = 13.5 V). The internal LDO regulator is not operational. When the voltage at the EN/UVLO pin is greater than the V EN-WAKE but less than V EN-VOUT the device enters the standby mode. In standby mode the internal LDO is enabled. As the EN/UVLO pin voltage increases above V EN-VOUT, the device enters active mode starting the feedback resistor detection. After feedback detect is completed, soft-start functionality is released to slowly increases the output voltage and switching starts. To stop switching and enter standby mode the EN/UVLO pin must fall below (V EN-VOUT – V EN-HYST). Any further decrease in the EN/UVLO pin voltage below V EN-WAKE the device is in shutdown. The various EN/UVLO threshold parameters and their shows the precision enable behavior. EN VCC VEN-VOUT 3.15 V VOUT VOUT VEN-WAKE VEN-HYST Figure 8-1. Precision Enable Behavior Remote precision undervoltage lockout can be implemented with this functionality as shown in Figure 8-2. See Section 9.2.2.8 for component selection. RENT RENB EN AGND VIN Figure 8-2. VIN Undervoltage Lockout Using the EN/UVLO Pin The high-voltage compliant EN/UVLO pin can be connected directly to the VIN input pin if remote precision control is not needed. The EN/UVLO pin must not be allowed to float. The various EN threshold parameters are listed in the Section 7.5. Figure 8-1 shows the precision enable behavior. After EN/UVLO goes above V EN-VOUT with a delay of about 1 ms, the output voltage begins to rise with a soft-start and reaches close to the final value in about 2.58 ms (t ss). After a delay of about 2 ms (t PGOOD_ACT), the PGOOD flag goes high. During startup, www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSM365R15

the device is not allowed to enter FPWM mode until the soft-start time has elapsed. Check Section 9.2.2.8 for component selection.

8.3.2 External CLK SYNC (With MODE/SYNC)

Synchronizing the operation of multiple regulators in a single system is often desirable, resulting in a well-defined system level performance. The select variants in the TPSM365R1x with the MODE/SYNC pin allow the power designer to synchronize the device to a common external clock. The rising edge of the clock signal, provided to the MODE/SYNC pin of the TPSM365R1x, corresponds to the turning on of the high-side device. The external clock synchronization is implemented using a phase locked loop (PLL) eliminating any large glitches. The external clock fed into the TPSM365R1x replaces the internal free-running clock, but does not affect any frequency foldback operation. Output voltage continues to be well-regulated. The device remains in FPWM mode and operates in CCM for light loads when synchronization input is provided. If no external clock pulses are applied the MODE/SYNC pin can set the mode of operation, AUTO Mode or FPWM Mode. The MODE/SYNC input pin of the TPSM365R1x can operate in one of three selectable modes:

• AUTO Mode: Pulse frequency modulation (PFM) operation is enabled during light load and diode emulation
• FPWM Mode: In FPWM mode, diode emulation is disabled, allowing current to flow backwards through the details.
• SYNC Mode: The internal clock locks to an external signal applied to the MODE/SYNC pin. As long as output voltage can be regulated at full frequency and is not limited by minimum off-time or minimum on-time, clock frequency is matched to the frequency of the signal applied to the MODE/SYNC pin. While the device is in SYNC mode, it operates as though in FPWM mode: diode emulation is disabled allowing the frequency applied to the MODE/SYNC pin to be matched without a load.

8.3.2.1 Pulse Dependent MODE/SYNC Pin Control

Most systems that require more than a single mode of operation from the TPSM365R1x are controlled by digital circuitry such as a microprocessor. These systems can generate dynamic signals easily but have difficulty generating multi-level signals. Pulse-Dependent MODE/SYNC pin control is useful with these systems. To initiate Pulse-Dependent MODE/SYNC pin control, a valid sync signal must be applied. Table 8-1 shows a summary of the pulse dependent mode selection settings. Table 8-1. Pulse-Dependent Mode Selection Settings MODE/SYNC INPUT MODE > VMODE_H FPWM with spread spectrum factory setting < VMODE_L AUTO Mode with spread spectrum factory setting Synchronization clock SYNC mode Figure 8-3 shows the transition between AUTO Mode and FPWM Mode while in Pulse-Dependent MODE/SYNC control. The TPSM365R1x transitions to a new mode of operation after the time, t MODE. Figure 8-3 and Figure 8-4 show the details. Transition to new mode of operation starts, spread spectrum turns on FPWM Mode Auto Mode > tMODE VMODE_H VMODE_L Figure 8-3. Transition from AUTO Mode and FPWM Mode If MODE/SYNC voltage remains constant longer than t MODE, the TPSM365R1x enters either AUTO mode or FPWM mode with spread spectrum turned on (if factory setting is enabled) and MODE/SYNC continues to operate in pulse-dependent scheme. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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Now Auto Mode, Spread Spectrum on tMODE VMODE_H VMODE_L > tPULSE_L < tSYNC > tPULSE_H Figure 8-4. Transition from SYNC Mode to AUTO Mode Now FPWM Mode, Spread Spectrum on tMODE VMODE_H VMODE_L > tPULSE_L < tSYNC > tPULSE_H < tSYNC > tPULSE_L Figure 8-5. Transition from SYNC Mode to FPWM Mode

8.3.3 Adjustable Switching Frequency (with RT)

The select variants in the TPSM365R1x family with the RT pin allow the power designers to set any desired operating frequency between 200 kHz and 2.2 MHz in their applications. See Figure 8-6 to determine the resistor value needed for the desired switching frequency. See Table 8-2 for selection on programming the RT pin. Table 8-2. RT Pin Setting RT INPUT SWITCHING FREQUENCY VCC 1 MHz GND 2.2 MHz RT to GND Adjustable according to Figure 8-6 Float (not recommended) No switching Equation 1 can be used to calculate the value of RT for a desired frequency. RT = 18286 Fsw1.021 (1) where

• RT is the frequency setting resistor value (kΩ).
• FSW is the switching frequency (kHz). Switching Frequency (kHz) RT resistor (k ) 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 Figure 8-6. RT Values vs Frequency

8.3.4 Power-Good Output Operation

The power-good feature using the PGOOD pin of the TPSM365R1x can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output remains low under www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSM365R15

device fault conditions, such as current limit and thermal shutdown, as well as during normal startup. A glitch filter prevents false flag operation for any short duration excursions in the output voltage, such as during line and load transients. Output voltage excursions lasting less than t RESET_FILTER do not trip the power-good flag. Power-good operation can best be understood in reference to Figure 8-7 . Table 8-3 gives a more detailed breakdown the PGOOD operation. Here, V PG-UV is defined as the PG-UV scaled version of the V OUT-Reg (target regulated output voltage) and V PG-HYS as the PG-HYS scaled version of the V OUT-Reg, where both PG-UV and PG-HYS are listed in Section 7.5. During the initial power up, a total delay of 5 ms (typical) is encountered from the time the VEN-VOUT is triggered to the time that the power-good is flagged high. This delay only occurs during the device startup and is not encountered during any other normal operation of the power-good function. When EN/UVLO is pulled low, the power-good flag output is also forced low. With EN/UVLO low, power-good remains valid as long as the input voltage (VPG-VALID is ≥ 0.9 V (typical)). The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup resistor connected to a suitable logic supply. It can also be pulled up to either V CC or V OUT through an appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit the current into this pin to ≤ 4 mA. Input Voltage Input Voltage Output Voltage VPG-UV (falling) VPG-HYS VIN_R (rising) VPG_VALID GND VOUT VIN_F (falling) PGOOD PGOOD may not be valid if input is below VPG-VALID Startup delay tRESET_FILTER PGOOD may not be valid if input is below VPG-VALID Small glitches do not reset tPGOOD_ACT timer Small glitches do not cause reset to signal a fault tPGOOD_ACT tRESET_FILTER tPGOOD_ACT tRESET_FILTER tRESET_FILTER Figure 8-7. Power-Good Operation (OV Events Not Included) Table 8-3. Fault Conditions for PGOOD (Pull Low) FAULT CONDITION INITIATED FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS BEFORE PGOOD OUTPUT IS RELEASED) VOUT < VPG-UV AND t > tRESET_FILTER Output voltage in regulation: VPG-UV + VPG-HYS < VOUT < VPG-OV - VPG-HYS VOUT > VPG-OV AND t > tRESET_FILTER Output voltage in regulation TJ > TSD-R TJ < TSD-F AND output voltage in regulation EN < VEN-VOUT - VEN-HYST EN > VEN-VOUT AND output voltage in regulation VCC < VCC-UVLO - VCC-UVLO-HYST VCC > VCC-UVLO AND output voltage in regulation

8.3.5 Internal LDO, VCC UVLO, and VOUT/FB Input

The TPSM365R1x uses the internal LDO output and the VCC pin for all internal power supply. The VCC pin draws power either from the VIN (in adjustable output variants) or the VOUT/FB depending on how the output voltage is configured. In the fixed output configuration, after the TPSM365R1x is active but has yet to regulate, the VCC rail continues to draw power from the VIN pin, until the VOUT/FB voltage reaches greater than 3.15 V (or when the device has reached steady-state regulation post the soft start). The VCC rail typically measures 3.15 V in both adjustable and fixed output variants. To prevent unsafe operation, VCC has an undervoltage TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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lockout, which prevents switching if the internal voltage is too low. See V VCC-UVLO and VVCC-UVLO-HYST in Section 7.5. During start-up, VCC momentarily exceeds the normal operating voltage until V VCC-UVLO is exceeded, then drops to the normal operating voltage. Note that these undervoltage lockout values, when combined with the LDO dropout, drives the minimum input voltage rising and falling thresholds.

8.3.6 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)

The high-side switch driver circuit requires a bias voltage higher than VIN to make sure the HS switch is turned on. The capacitor connected between BOOT and SW works as a charge pump to boost voltage on the BOOT terminal to (SW + VCC). A 100-nF boot capacitor is integrated in the TPSM365R1x to reduce overall external component count and minimize physical design size. The BOOT rail has an UVLO setting. This UVLO has a threshold of V BOOT-UVLO and is typically set at 2.3 V. If the C BOOT capacitor is not charged above this voltage with respect to the SW pin, then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-side device.

8.3.7 Output Voltage Selection

In the TPSM365R1x, each variant can be configured as a fixed output voltage or an adjustable output voltage. During device initialization the device configures the target output voltage to an internally selected value or an adjustable version by detecting if feedback resistors are present. When configuring the output voltage to be fixed value, simply connect the VOUT/FB pin to the system output voltage node. See Section 5 for the fixed output voltage setting of each variant. To configure an adjustable output voltage, external feedback resistors are required as shown in Figure 8-8. By connecting external feedback resistors with a parallel resistance greater than 5 kΩ but less than or equal to 10 kΩ (see Equation 2) the output voltage is set according as needed. The internal voltage reference is 1 V. Refer to Section 9.2.2.3 for more details on how to adjust the output voltage. RFBT RFBB FB AGND VOUT Figure 8-8. Setting Output Voltage for Adjustable Output Variant 5 k Ω < R FB T R F BB ≤ 10 k Ω (2)

• RFBT is the top resistor of the feedback divider
• RFBB is the bottom resistor of the feedback divider When configured in adjustable output voltage mode, an addition feed-forward capacitor, C FF, in parallel with the No additional resistor divider or feed-forward capacitor, CFF, is needed in fixed-output variants. Please refer to Table 8-4 for selecting passive component values for typical, output voltages. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSM365R15

Table 8-4. Standard RFBT Values, Recommended FSW and Minimum COUT VOUT (V) RFBT (kΩ) RFBB (kΩ) RECOMMENDED FSW (kHz) COUT(MIN) (µF) (EFFECTIVE) VOUT (V) RFBT (kΩ) RFBB (kΩ) RECOMMENDED FSW (kHz) COUT(MIN) (µF) (EFFECTIVE) 1.8 18.2 22.6 500 33 10 100 11 1800 2.2 2.0 20 20 500 22 12 121 10.7 2200 2.2 3.0 30 15 800 4.7 15 150 10.7 2200 2.2

8.3.8 Spread Spectrum

The purpose of spread spectrum is to reduce peak emissions at specific frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency operation. The TPSM365R1x implements a modulation pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching frequency can be easily filtered. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The TPSM365R1x uses a spread of frequencies, which can spread energy smoothly across the FM and TV bands, but is small enough to limit subharmonic emissions below the switching frequency of the part. Pseudo random frequency hopping allows the spread spectrum to be very effective at spreading the energy. The TPSM365R1x uses a cycle-to-cycle frequency hopping method based on a linear feedback shift register (LFSR). This intelligent pseudo-random generator limits cycle-to-cycle frequency changes to limit output ripple. The pseudo random pattern repeats at less than 1.5 Hz, which is below the audio band. The spread spectrum is only available while the clock of the device is free running at its natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

• The clock is slowed due to operation at low-input voltage – this is operation in dropout.
• The clock is slowed under light load in auto mode. Note that if you are operating in FPWM mode, spread spectrum can be active, even if there is no load.
• The clock is slowed due to high input to output voltage ratio. This mode of operation is expected if on time reaches minimum on time. See the Section 7.5.
• The clock is synchronized with an external clock.

8.3.9 Soft Start and Recovery from Dropout

When designing with the TPSM365R1x, both soft start and recovery from dropout can cause slow rise in output voltage and must be considered as a two separate operating conditions, as shown in Figure 8-9 and Figure 8-10. These features ramp the output voltage at a controlled rate, keeping the output voltage from overshooting. See

8.3.9.1 Soft Start

The soft-start feature allows the converter to gradually reach the steady state output voltage, reducing the startup stress in the system. Soft start is triggered by any of the following conditions:

• Appropriate voltage level is applied to the VIN pin of the device, releasing undervoltage lockout.
• EN/UVLO voltage is sufficient to enter active mode while the voltage on VIN pin is at least VIN_R.
• Recovery from shutdown due to overtemperature protection. After soft start is triggered, the internal reference is slowly ramped up. Assuming the output voltage is initially 0 V, the reference is ramped to 90% of the target output voltage in t SS. During the soft-start time, the switching mode is set to AUTO mode. AUTO mode activates diode emulation for the low-side MOSFET, not allowing TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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negative inductor current. This allows the output voltage to be pre-biased, voltage already present on the output, during start-up without discharging the output capacitor. Figure 8-9 shows the difference between a non biased soft start and a pre-biased soft start. VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS Triggering event If selected, FPWM is enabled only after completion of tSStEN VEN VOUT Set Point EN and Output Voltages Time t VOUT V 90% of VOUT Set Point 0 V tSS Triggering event tEN If selected, FPWM is enabled only after completion of tSS Figure 8-9. Soft Start With and Without Pre-biased Voltage

8.3.9.2 Recovery from Dropout

Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called graceful recovery, differs from soft start in two important ways:

• The reference voltage is set to approximately 1% above what is needed to achieve the existing output voltage.
• If the device mode is set to FPWM, it continues to operate in that mode during its recovery from dropout. If output voltage were to suddenly be pulled up by an external supply, the TPSM365R1x can pull down on the output. Note that all protections that are present during normal operation are in place, preventing any catastrophic failure if output is shorted to a high voltage or ground. Load current VOUT Set Point and max output current Output Voltage and Current Slope the same as during soft start Time t VOUT V Figure 8-10. Recovery from Dropout Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall below set point is removed, the output climbs at the same speed as during start-up.

8.3.10 Current Limit and Short Circuit

The TPSM365R1x are protected from overcurrent conditions by cycle-by-cycle current limiting on both high-side and low-side MOSFETs. High-side (HS) MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is compared to either the minimum of a fixed current set point or the output of the internal error amplifier loop minus the slope compensation every switching cycle. Because the output of the internal error amplifier loop has a maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased duty factor if duty factor is typically above 35%. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSM365R15

When the low-side (LS) switch is turned on, the current going through it is also sensed and monitored. Like the high-side device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the low-side device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be. This limit is called the low-side current limit, ILS-LIMIT in Figure 8-11. If the LS current limit is exceeded, the LS MOSFET stays on and the HS switch is not to be turned on. The LS switch is turned off after the LS current falls below this limit and the HS switch is turned on again as long as at least one clock period has passed because the last time the HS device has turned on. iL VSW IOUT Inductor Current t t SW Voltage VIN Typically, tSW > Clock setting tON < tON_MAX IPEAKMAX IVALMAX Figure 8-11. Current Limit Waveforms Because the current waveform assumes values between I SC and I LS-LIMIT, the maximum output current is very close to the average of these two values unless duty factor is very high. After operating in current limit, hysteretic control is used and current does not increase as output voltage approaches zero. If the duty factor is very high, current ripple must be very low to prevent instability. Because current ripple is low, the part is able to deliver full current. The current delivered is very close to ILS-LIMIT. VOUT

0 Output Voltage

VIN > 2 × VOUT Setting VIN ≅ VOUT Setting Figure 8-12. Output Voltage versus Output Current TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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8.3.11 Thermal Shutdown

Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to approximately 158°C (typical). When the junction temperature falls below 158°C (typical), the TPSM365R1x attempts another soft start. While the TPSM365R1x is shut down due to high junction temperature, power continues to be provided to VCC. To prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced current limit while the part is disabled due to high junction temperature. The LDO only provides a few milliamperes during thermal shutdown.

8.3.12 Input Supply Current

The TPSM365R1x is designed to have very low input supply current when regulating light loads. When configured as a fixed output voltage, the FB/BIAS pin is the input to the LDO that powers the majority of the control circuits. By connecting the FB/BIAS input pin to the output node of the regulator, a small amount of current is drawn from the output. This current is reduced at the input by the ratio of VOUT / VIN. When configured as an adjustable output voltage, the internal LDO is powered by VIN. This action results in higher power loss through the internal LDO which results in lower efficiency compared to a fixed output configuration.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN/UVLO pin provides electrical on and off control of the device. When the EN/UVLO pin voltage is below 0.4 V, the internal LDO is disabled and there is no switching of the internal power MOSFETs. In shutdown mode, the quiescent current drops to 0.55 µA (typical) when VIN is 13.5 V.

8.4.2 Standby Mode

When the EN/UVLO pin voltage is greater than the V EN-WAKE but less than V EN-VOUT, the internal LDO is enabled. The precision enable circuitry is enabled after VCC is above its undervoltage threshold (V CC-UVLO). The internal power MOSFETs remain off unless the voltage on EN/UVLO pin voltage goes above its precision enable threshold (VEN-VOUT) and the input voltage on VIN pin is greater than VIN_R.

8.4.3 Active Mode

The TPSM365R1x is in active mode whenever the EN/UVLO pin is above VEN-VOUT, VIN is high enough to satisfy VIN_R, and no other fault conditions are present. The simplest way to enable the operation is to connect the EN/UVLO pin to VIN, which allows self start-up when the applied input voltage exceeds the minimum VIN_R. In active mode, depending on the load current, input voltage, and output voltage, the TPSM365R1x is in one of five modes:

• Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the inductor current ripple
• AUTO Mode - Light Load Operation: PFM when switching frequency is decreased at very light load
• FPWM Mode - Light Load Operation: Continuous conduction mode (CCM) when the load current is lower than half of the inductor current ripple
• Minimum on-time: At high input voltage and low output voltages, the switching frequency is reduced to maintain regulation.
• Dropout mode: When switching frequency is reduced to minimize voltage dropout between input and output.

8.4.3.1 CCM Mode

The following operating description of the TPSM365R1x refers to Section 8.2 and to the waveforms in Figure 8-13. The TPSM365R1x has two behaviors while lightly loaded, AUTO mode and FPWM mode. Regardless of www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSM365R15

the light load operation configuration the converter operates in CCM when the load current is greater than half the inductor ripple current. In CCM, the TPSM365R1x supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS) switches with varying duty cycle (D). During the HS switch on-time, the SW pin voltage, V SW, swings up to approximately V IN, and the inductor current, i L, increases with a linear slope. The HS switch is turned off by the control logic. During the HS switch off-time, t OFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the V SW to swing below ground by the voltage drop across the LS switch. The converter loop adjusts the duty cycle to maintain a constant output voltage. Duty cycle is defined by the on-time of the HS switch over the switching period: D = TON / TSW (3) In an ideal buck converter where losses are ignored, duty cycle is proportional to the output voltage and inversely proportional to the input voltage: D = VOUT / VIN (4) iL VSW IPEAK IOUT Iripple Inductor Current - IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW tON tOFF VOUT VIN Figure 8-13. SW Voltage and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

8.4.3.2 AUTO Mode - Light Load Operation

AUTO mode operation, allows for seamless transition between normal current mode operation while heavily loaded and highly efficient light load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which mode the TPSM365R1x operates in depends on which variant from this family is selected. Note that variants with a MODE/SYNC pin operate in FPWM mode when synchronizing frequency to an external signal. The light load operation is employed in the TPSM365R1x only in the AUTO mode. The light load operation employs two techniques to improve efficiency:

• Diode emulation, which allows DCM operation. See Figure 8-14.
• Frequency reduction. See Figure 8-15. Note that while these two features operate together to improve light load efficiency, they operate independent of each other.

8.4.3.2.1 Diode Emulation

Diode emulation prevents reverse current through the inductor which requires a lower frequency needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is reduced. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero to maintain regulation. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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D = t t SW Voltage tON tSW VIN tSW tON tOFF tHIGHZ VOUT VIN In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of what inductor ripple can be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active. Figure 8-14. PFM Operation The TPSM365R1x has a minimum peak inductor current setting (see I PEAK-MIN in Section 7.5) while in auto mode. After current is reduced to a low value with fixed input voltage, on-time is held constant. Regulation is then achieved by adjusting frequency. This mode of operation is called Pulse Frequency Modulation (PFM) mode.

8.4.3.2.2 Frequency Reduction

The TPSM365R1x reduces frequency whenever output voltage is high. This function is enabled whenever the internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the regulation set point of FB and the voltage applied to FB. The net effect is that there is larger output impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1% high when the part is completely unloaded. 1% Above Set point VOUT Set Point Output Voltage Current Limit VOUT Output Current IOUT0 In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that output voltage is 1% high while the buck is completely unloaded. Figure 8-15. Steady State Output Voltage versus Output Current in Auto Mode In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a dummy load at VOUT or FPWM Mode can be used to reduce or eliminate this offset.

8.4.3.3 FPWM Mode - Light Load Operation

In FPWM Mode, frequency is maintained while lightly loaded. To maintain frequency, a limited reverse current is allowed to flow through the inductor. Reverse current is limited by reverse current limit circuitry, see Section 7.5 for reverse current limit values (IL-NEG). www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSM365R15

D = t t SW Voltage tON tSW VIN tSW tON tOFF VOUT VIN In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple. Figure 8-16. FPWM Mode Operation For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to command minimum on-time even while lightly loaded, allowing good behavior during faults which involve output being pulled up.

8.4.3.4 Minimum On-time Operation

The TPSM365R1x continue to regulate output voltage even if the input-to-output voltage ratio requires an on-time less than the minimum (t ON-MIN). This action is accomplished using valley current control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley current falls below that determined by the compensation circuit. If the converter is not operating in current limit, the maximum valley current is set above the peak inductor current, preventing valley control from being used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high, such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley current matches that being commanded by the compensation circuit. Under these conditions, the low-side device is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley current. Because on-time is fixed at its minimum value, this type of operation resembles that of a device using a Constant On-Time (COT) control scheme; see Figure 8-17. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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• IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW > Clock setting tON = tON_MIN tOFF VOUT VIN In valley control mode, minimum inductor current is regulated, not peak inductor current. Figure 8-17. Valley Current Mode Operation

8.4.3.5 Dropout

Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the required duty cycle. At a given clock frequency, duty cycle is limited by minimum off-time. After this limit is reached as shown in Figure 8-19 if clock frequency was to be maintained, the output voltage falls. Instead of allowing the output voltage to drop, the TPSM365R1x extends the high side switch on-time past the end of the clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after peak inductor current is achieved or after a pre-determined maximum on-time, t ON-MAX, of approximately 9 µs passes. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the existence of a minimum off-time, frequency drops to maintain regulation. As shown in Figure 8-18 if input voltage is low enough so that output voltage cannot be regulated even with an on-time of t ON-MAX, output voltage drops to slightly below the input voltage by V DROP. For additional information on recovery from dropout, refer back to Figure 8-10. VOUT Output Setting Output Voltage VIN0 Input Voltage FSW Switching Frequency VIN0 Input Voltage Input Voltage ≅ 110 kHz VDROP Output Voltage FSW-NOM Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz, input voltage tracks output voltage. Figure 8-18. Frequency and Output Voltage in Dropout www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSM365R15

• IOUT RDSON-LS D = t t SW Voltage tON tSWVIN tSW > Clock setting tOFF = tOFF_MIN tON < tON_MAX VOUT VIN IPEAK Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result, frequency drops. This frequency drop is limited by tON-MAX. Figure 8-19. Dropout Waveforms TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPSM365R15 only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. To expedite and streamline the process of designing of a TPSM365R15, WEBENCH online software is available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. The following section describes the design procedure to configure the TPSM365R15 power module. The TPSM365R15 integrates several optional features to meet system design requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below shows TPSM365R15 configuration options designed for several application use cases. Refer to the TPSM365R15EVM, TPSM365R15FEVM User's Guide for more detail. Note All of the capacitance values given in the following application information refer to effective values unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective capacitance up to the required value. This action can also ease the RMS current requirements on a single capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to make sure that the minimum value of effective capacitance is provided. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSM365R15

9.2 Typical Application

Figure 9-1 and Figure 9-2 show two typical application circuits for the TPSM365R15. Figure 9-1 switching frequency can be programmed from 200 kHz to 2.2 MHz with a RT resistor. Connecting RT to VCC or GND (or comparable source) programs the frequency for either 1 MHz or 2.2 MHz, respectfully. The output voltage can be configured for fixed, 3.3-V configuration by shorting VOUT to FB and depopulating RFBB. Figure 9-2 pin 11 definition changes to MODE/SYNC. This pin can be connected to VCC or GND (or comparable source) for FPWM or auto mode operation, respectfully. Both designs are capable of having an output voltage ranging from 1 V to 16 V. Detailed Design Procedure outlines the procedure to designing a 5-V output with TPSM365R15F. This design can be used in a factory automation, 4-20 mA loop design due to the low-noise, small design size, and modest efficiency over the entire load range. VIN EN VCC SW BOOT FB VIN VOUT COUT CIN CVCC 1 µF RT CHF RFBT RFBBGND PGOOD A = 200 kHz to 2.2 MHz or B = 2.2 MHz or C = 1 MHz A B C 2.2 µF VOUT TPSM365R15 * *For fixed, 3.3-V configuration: RFBT = 0 and RFBB = DNP Figure 9-1. Example Application Circuit (TPSM365R15) VIN EN VCC FB VIN CIN CVCC 1 µF MODE/SYNC CHF GND PGOO D A = SYNC or B = AUTO mode or C = FPWM mode A B C 2.2 µF VOUT COUT RFBT RFBB SW BOOT VOUT *For fixed, 5-V configuration: RFBT = 0 and RFBB = DNP TPSM365R15F Figure 9-2. Example Application Circuit (TPSM365R15F) TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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9.2.1 Design Requirements

Section 9.2.2 provides instructions to design and select components according to Table 9-1. Table 9-1. Detailed Design Parameters DESIGN PARAMETER EXAMPLE VALUE Input voltage 5.5 V to 65 V Output voltage 5 V Maximum output current 0 to 150 mA Switching frequency 1 MHz

9.2.2 Detailed Design Procedure

The design procedure that follows and the resulting component selection is illustrated in Figure 9-3. VIN EN VCC FB VIN CIN CVCC 1 µF MODE/SYNC GND PGOO D 2.2 µF COUT SW BOOT VOUT TPSM365R15F 10 µF Figure 9-3. 5-V Output Design Example

9.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM365R1x with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible devices from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

9.2.2.2 Choosing the Switching Frequency

The recommended switching frequency for standard output voltages can be found in Standard R FBT Values, Recommended FSW and Minimum C OUT . For a 5-V output, the recommended switching frequency is 1 MHz, which TPS365R15F operates at by default. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPSM365R15

9.2.2.3 Setting the Output Voltage

Fixed output configuration allows the feedback resistors to be eliminated and the layout to be simplified. TPSM365R15F can be configured for 5 V, fixed configuration by shorting V OUT to FB, for which this design does. See Device Comparison Table for the selection of fixed output voltage versions. The device can be configured for adjustable output voltage in the case a different output voltage is required, as example. For more information on how to choose the feedback resistor values, please see Section 8.3.7. The recommended value of R FBB is 10 k Ω. The value for R FBT can be selected from Standard R FBT Values, Recommended FSW and Minimum COUT or calculated using Equation 5: R FBT k Ω = R FBB k Ω × V OUT V 1V − 1 (5)

9.2.2.4 Input Capacitor Selection

The TPSM365R15(F) design uses a 2.2- μF input capacitor to keep the input, voltage ripple small. TI recommends an additional 0.1- μF capacitor in parallel for improved bypassing (lower noise). High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, a 2.2- μF, 100-V rated capacitor is used. Using an electrolytic capacitor on the input in parallel with the ceramics is often desirable. This fact is especially true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.

9.2.2.5 Output Capacitor Selection

For a 5-V output, the TPSM365R15(F) requires a minimum of 4.7-µF effective output capacitance for proper operation (see Standard R FBT Values, Recommended F SW and Minimum C OUT ). High-quality ceramic type capacitors with sufficient voltage and temperature rating are required. Additional output capacitance can be added to reduce ripple voltage or for applications with transient load requirements. In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed. This design uses a 10-μF, 10-V, 1206 capacitor which is approximately 5 µF at 5-V DC bias. A smaller case size capacitor, or lower DC rating, does not provide adequate, effective capacitance for this design.

9.2.2.6 VCC

The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general, this output must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the power-good function (see Power-Good Output Operation). A value in the range of 10 k Ω to 100 kΩ is a good choice in this case. The nominal output voltage on VCC is 3.3 V; see Section 7.5 for limits.

9.2.2.7 CFF Selection

In some cases, a feedforward capacitor can be used across R FBT to improve the load transient response or improve the loop-phase margin. Optimizing Transient Response of Internally Compensated DC-DC Converters with Feedforward Capacitor application report is helpful when experimenting with a feedforward capacitor. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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Due to the nature of the feedback detect circuitry, the value of C FF must be limited to make sure that the desired output voltage is established when configuring for adjustable output voltages. Equation 6 must be followed to make sure CFF remains below the maximum value. C FF < C OUT × V OUT 1.2 × 10 6 (6) www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPSM365R15

9.2.2.8 External UVLO

In some cases, an input UVLO level different than that provided internal to the device is needed. This need can be accomplished by using the circuit shown in Figure 9-4 . The input voltage at which the device turns on is designated as VON while the turn-off voltage is V OFF. First, a value for R ENB is chosen in the range of 10 k Ω to 100 kΩ, then Equation 7and Equation 8 are used to calculate RENT and VOFF, respectively. EN RENT RENB VIN Figure 9-4. Setup for External UVLO Application R EN T = V O N V EN − VO U T – 1 × R E NB (7) V O FF = V ON × 1 – V EN − HY S V E NV OU T (8) where

• VON is the VIN turn-on voltage.
• VOFF is the VIN turn-off voltage.

9.2.2.9 Power-Good Signal

Applications requiring a power-good signal to indicate that the output voltage is present and in regulation must use a pullup resistor between the PGOOD pin and a valid voltage source. This voltage source can be VCC or VOUT, as example.

9.2.2.10 Maximum Ambient Temperature

As with any power conversion device, the TPSM365R15(F) dissipates internal power while operating. The effect of this power dissipation is to raise the internal temperature of the power module above ambient. The internal die and inductor temperature (T J) is a function of the ambient temperature, the power loss, and the effective thermal resistance, R θJA, of the module and PCB combination. The maximum junction temperature for the TPSM365R15(F) must be limited to 125°C. This limit establishes a limit on the maximum module power dissipation and, therefore, the load current. Equation 9 shows the relationships between the important parameters. It is easy to see that larger ambient temperatures (T A) and larger values of R θJA reduce the maximum available output current. Being that the power dissipation is relatively low in this module, this device must be capable of supporting its max ambient temperature rating, across the majority of power conditions with a modest size 2 layer or 4 layer PCB. Further thermal analysis can be done by measuring the top case temperature on the EVM which is nearly equivalent to the junction due to its thin case. As stated in the Semiconductor and IC Package Thermal Metrics application report the values given in Section 7.4 section are not valid for design purposes and must not be used to estimate the thermal performance of the application. The values reported in that table were measured under a specific set of conditions that are rarely obtained in an actual application. I O UT , max = T J − T A R θ JA × η 1 − η × 1 η (9) TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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• η is the efficiency. The effective R θJA (TPSM365R15 approximately 56°C/W at 24 V IN, 5 V OUT, 150 mA, 1 MHz,) is a critical parameter and depends on many factors such as the following:
• Power dissipation
• Air temperature and flow
• PCB area
• Copper heat-sink area
• Number of thermal vias under the package
• Adjacent component placement The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition and temperature. Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given application environment:
• Thermal Design by Insight not Hindsight application report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application report
• Semiconductor and IC Package Thermal Metrics application report
• Thermal Design Made Simple with LM43603 and LM43602 application report
• PowerPAD™ Thermally Enhanced Package application report
• PowerPAD™ Made Easy application report
• Using New Thermal Metrics application report
• PCB Thermal Calculator

9.2.2.11 Other Connections

• The RT pin can be connected to AGND for a switching frequency of 2.2 MHz or tied to VCC for a switching frequency of 1 MHz. A resistor connected between the RT pin and GND can be used to set the desired operating frequency between 200 kHz and 2.2 MHz.
• For the MODE/SYNC pin variant, connecting this pin to an external clock forces the device into SYNC operation. Connecting the MODE/SYNC pin low allows the device to operate in PFM mode at light load. Connecting the MODE/SYNC pin high puts the device into FPWM mode and allows full frequency operation independent of load current.
• A resistor divider network on the EN pin can be added for a precision input undervoltage lockout (UVLO)
• Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
• A pullup resistor between the PGOOD pin and a valid voltage source to generate a power-good signal. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPSM365R15

9.2.3 Application Curves

Load Current (A) Efficiency (%) 5V (Fixed), 1MHz 3.3V (Fixed), 1MHz Figure 9-5. 12VIN Efficiency Load Current (A) Efficiency (%) 5V (Fixed), 1MHz, FPWM 2.5V, 500kHz 1.8V, 500kHz Figure 9-6. 12VIN Efficiency Load Current (A) Efficiency (%) 12V, 2.2MHz 5V (Fixed), 1MHz 3.3V (Fixed), 1MHz Figure 9-7. 24VIN Efficiency Load Current (A) Efficiency (%) 5V (Fixed), 1MHz, FPWM 2.5V, 500kHz 1.8V, 500kHz Figure 9-8. 24VIN Efficiency Figure 9-9. 48VIN Efficiency Load Current (A) Efficiency (%) 5V (Fixed), 1MHz, FPWM 2.5V, 500kHz 1.8V, 500kHz Figure 9-10. 48VIN Efficiency TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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9.2.3 Application Curves (continued)

VIN = 24 V VOUT = 3.3 V (Fixed) 2.2 MHz 75 mA to 150 mA, 50 mA/µs COUT = 1 × 10 uF (1206, 10VDC) Figure 9-11. Load Transient VIN = 24 V VOUT = 5 V 150 mA, 1 MHz Figure 9-12. EVM Thermal Performance Frequency (MHz) Amplitude (dBuV) CISPR 11/32 Class B Conducted Emmissions 0.15 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 3030 -10 Qpk Limit Average Limit Qpk Detect Average Detect VIN = 24 V VOUT = 5 V Fsw = 1 MHz Board = TPSM365R15EVM (Unmodified) Load = 150 mA Figure 9-13. CISPR 11, Class B, CE Scan 150 kHz – 30 MHz www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPSM365R15

VIN = 24 V VOUT = 5 V Fsw = 1 MHz Board = TPSM365R15EVM (Unmodified) Load =150 mA Figure 9-14. CISPR 11/32, Class B, RE, 10-Meter Scan 30 MHz – 1 GHz TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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9.3 Best Design Practices

• Do not exceed the Absolute Maximum Ratings.
• Do not exceed the Recommended Operating Conditions.
• Do not exceed the ESD Ratings.
• Do not allow the EN input to float.
• Do not allow the output voltage to exceed the input voltage, nor go below ground.
• Follow all the guidelines and suggestions found in this data sheet before committing the design to production. TI application engineers are ready to help critique your design and PCB layout to help make your project a success.

9.4 Power Supply Recommendations

The TPSM365R15 buck module is designed to operate over a wide input voltage range of 3 V to 65 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator circuit. Estimate the average input current with Equation 10. I IN = V O UT × I OUT V I N × η (10) where

• η is the efficiency If the module is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can cause false UVLO triggering and a system reset. The best way to solve such issues is to reduce the distance from the input supply to the module and use an electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range of 10 μF to 47 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit configurations.

9.5 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal thermal performance, and minimal generation of unwanted EMI.

9.5.1 Layout Guidelines

The PCB layout of any DC/DC module is critical to the optimal performance of the design. Poor PCB layout can disrupt the operation of an otherwise good schematic design. Even if the module regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter module, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground, as shown in Figure 9-15. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the power module. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Layout Example shows a recommended layout for the critical components of the TPSM365R15. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPSM365R15

1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are adjacent, simplifying the input capacitor placement. 2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and GND pins. 3. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if used, physically close to the device. The connections to FB and GND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator. 4. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat dissipation path. 5. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the power module and maximizes efficiency. 6. Provide enough PCB area for proper heat-sinking. Sufficient amount of copper area must be used to make sure of a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes. 7. Use multiple vias to connect the power planes to internal layers. See the following PCB layout resources for additional important guidelines:

• Layout Guidelines for Switching Power Supplies application report
• Simple Switcher PCB Layout Guidelines application report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report VIN SW GND Figure 9-15. Current Loops with Fast Edges TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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9.5.2 Layout Example

Keep FB, RT, VCC trace small Maintain continuous ground pours Large VOUT pour for cooling VIN VOUT VOUT FB GND VCC RT Mid layer Top Layer ~100nF, 0402/0603 capacitor nearest to Vin pin Figure 9-16. Example Layout www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPSM365R15

10 Device and Documentation Support

10.1 Device Support

10.1.1 Device Nomenclature

Figure 10-1 shows the device naming nomenclature of the TPSM365R1x. See Section 5 for the availability of each variant. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply. MODE/SYNC OR RT VARIANT Blank: 3.3-V ( xed/adj.) RT variant F: 5-V ( xed/adj.) MODE/SYNC variant PACKAGE RDNR = QFN-HR 11-pin large reel TPSM365R XX X RDNR OUTPUT CURRENT MAX 1: 100 mA 15: 150 mA Figure 10-1. Device Naming Nomenclature

10.1.2 Development Support

10.1.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM365R1x with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible devices from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following:

• For TI's WEBENCH Power Designer environment, visit the WEBENCH design center
• Texas Instruments, Thermal Design by Insight not Hindsight application report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, Layout Guidelines for Switching Power Supplies application report
• Texas Instruments, Simple Switcher PCB Layout Guidelines application report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x application report
• Texas Instruments, Optimizing Transient Response of Internally Compensated DC-DC Converters with Feed forward Capacitor application report TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. www.ti.com TPSM365R15 SNVSCI1 – OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPSM365R15

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. TPSM365R15 SNVSCI1 – OCTOBER 2023 www.ti.com

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www.ti.com 28-Oct-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPSM365R15RDNR ACTIVE QFN-FCMOD RDN 11 3000 RoHS (In Work) & Green (In Work) NIPDAU Level-3-260C-168 HR -40 to 125 365R15 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com QFN-FCMOD - 2.1 mm max height PLASTIC QUAD FLAT PACK- NO LEAD RDN0011A A 0.08 C SEATING PLANE PIN 1 INDEX AREA C

0.1 C A B

0.05 C B NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PKG SYMM 3.6 3.4 4.6 4.4 2.1 1.9 0.05 (0.2) TYP 4 5 11 9 (0.2) 2X 1.15 1.05 2X 2.1 8X (0.25) 6X 0.5 2X 1.025 0.825 2X 0.65 0.55 1.4 1.3 2X 0.3 2X 0.65 2X 1.15 2X 1.9 6X 0.35 0.15 0.4 0.2 0.05 C 2X 0.425 0.325 2X 0.5 3 6 0.05 C 4X 1 0.8

www.ti.com QFN-FCMOD - 2.1 mm max heightRDN0011A PLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. (0.37) 4X (1.1)6X (0.25) (0.8) 2X (1.1) (1.52) 2X (0.5) (0.5) (R0.05) TYP SOLDER MASK DETAILS

0.05 MAX

0.05 MIN

(PREFERRED) SOLDER MASK DEFINED (2.23) 2X (2.06) 2X (1.96) (1.23) 2X (1.15) (0.23) 2X (0.3) (0.77) (1.77) 2X (0.78) 2X (1.55) 2X (1.05) 2X (1.41) 2X (0.59) (1.4) (1.69) (0.56) 2X (0.55) (Ø0.2) TYP (1.48)(1.48) 4X(0.65)

0.000 PKG

(2.05) (0.385) TYP (0.25) 2X (0.2) (1.75) 3X (1.73) (0.9) (1.729) (1.05) 0.000 SYMM 3 6 (0.3) (1.3875) 2X (1.125)

www.ti.com QFN-FCMOD - 2.1 mm max heightRDN0011A PLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL PIN 4 & 5: 72% SOLDER COVERAGE BY AREA SCALE: 20X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11 9 (0.37) 4X (1.1) 6X (0.25) (0.8) 2X (2.05) 8X (0.375) (1.52) 2X (0.5) (0.25) 2X (0.2) 2X (1.75) (R0.05) TYP 2X (2.06) 2X (1.96) 2X (1.15) (0.65) 2X (0.3) (1.4) (1.69) 6X (0.5) 6X (0.93) 3X (0.91) 2X (1.77) 2X (1) 2X (0.23) (0.51) (0.62) (0.3) 4X (1.76) 0.000 SYMM (1.3875) 2X (1.125)

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