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TPSI3123

Texas Instruments

TPSI3100 Isolated Switch Driver With 17V Gate Drive, Integrated Bias Supply, and Dual Isolated Comparators NOVEMBER 2024

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TPSI3100 Isolated Switch Driver With 17V Gate Drive, Integrated Bias Supply, and Dual Isolated Comparators

1 Features

Drives external power switches (MOSFETs, IGBTs, SiC FETs, SCRs)
Integrated bias supply, no isolated secondary supply required
17V gate drive, 1.5A and 2.5A peak source and sink current
3kVRMS basic isolation
Up to 25mW, 5V supply for external auxiliary circuitry
Dual isolated high-speed comparators with integrated voltage reference ±1.5%
Open-drain outputs for fault and alarm indicators
–40°C to +125°C, TA
Functional Safety-Capable – Documentation available to aid functional safety system design
Safety-related certifications – Planned: 4243VPK basic isolation per DIN EN IEC 60747-17 (VDE 0884-17) – Planned: 3kVRMS isolation for 1 minute per UL 1577

2 Applications

Solid state relays
Building automation
Factory automation and control

3 Description

The TPSI3100 is a fully integrated isolated switch driver, which when combined with an external power switch, forms a complete isolated solid state relay solution. With a gate drive voltage of 17V with 1.5A and 2.5A peak source and sink current, a large availability of power switches can be used to meet many application needs. The TPSI3100 generates its own secondary bias supply from power received on its primary side, so no isolated secondary supply bias is required. The TPSI3100 provides additional power via the nominal 5V rail (VDDM) for use by auxiliary circuits to perform various function such as current and voltage monitoring or remote temperature detection. The TPSI3100 isolation is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than those found using traditional mechanical relays and optocouplers. The TPSI3100 integrates a communication back- channel that transfers status information from the secondary side to the primary side via open-drain outputs, PGOOD (Power Good), FLT1 (Fault 1), and ALM1 (Alarm 1). Dual high-speed comparators with an integrated shared voltage reference are used to assert FLT1 and ALM1. When the comparator input, FLT1_CMP, exceeds the voltage reference, the driver is immediately asserted low and FLT1 is also driven low, indicating to the system that a fault has occurred. This is useful for disabling the external switch with low latency on critical events, such as overcurrent detection. When the comparator input, ALM1_CMP, exceeds the voltage reference, ALM1 signal is asserted low, but no action is taken by the driver. This may be useful as an alarm or warning indicator for overtemperature or overvoltage events. The TPSI310xL series offers a latch based fault indicator. When a fault is detected, the driver and the fault indicator are asserted low and remain latched, until EN is asserted low. The TPSI310x series has a non-latched fault indicator. If the fault event is no longer present, FLT1 deasserts and the driver, after a specified recovery period, follows the state of the EN pin. If the fault event still remains, both the fault indicator and the driver remain asserted low. Device Information PART NUMBER REF(2) COMPARATORS(2) PACKAGE(1) TPSI3100 0.31V 1 fault, 1 alarm DVX (SSOP, 16) TPSI3100L 0.31V 1 latched fault, 1 alarm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) See Device Comparison Table. VDD GPIO GPIO GND uC GPIO SIGNAL Control VDRV VDDH VDDM VSSS FLT1_CMP ALM1_CMP EN CE PGOOD VSSP VDDP ALM1 VSSP VSSS Control & Power Transfer SIGNAL POWER ISOLATION TPSI310x FLT1 – RESP LOAD RSHUNT TPSI3100 Simplified Schematic TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.2 Receiving Notification of Documentation Updates..43

12 Mechanical, Packaging, and Orderable

SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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4 Device Comparison Table

VARIANT REF COMPARATORS LATCHED FAULT TPSI3100 0.31V 1 fault, 1 alarm No TPSI3103 (3) 1.23V TPSI3100L 0.31V Yes TPSI3103L (3) 1.23V TPSI3110 (3) 0.31V 2 faults No TPSI3113 (3) 1.23V TPSI3110L (3) 0.31V Yes TPSI3113L (3) 1.23V TPSI3120 (3) 0.31V 2 alarms N/A(2) TPSI3123 (3) 1.23V TPSI3133 (3) 1.23V 1 fault(1), 1 alarm No (1) FLT1_CMP input is actively pulled down when EN is low. These devices are useful for overcurrent detection using DESAT techniques primarily with IGBT power transistors. (2) Non-applicable. (3) Product preview. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSI3100

5 Pin Configuration and Functions

15 VDDH

ALM1_CMP PGOOD FLT1_CMP ALM1 FLT1 Figure 5-1. TPSI310x and TPSI310xL DVX Package, 16-Pin SSOP (Top View) PIN I/O TYPE(1) DESCRIPTION NO. NAME 1 EN I — Active high driver enable. Internal 500kΩ pull-down to VSSP. 2 CE I — Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP. 3 VSSP — GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground. 4 VDDP — P Power supply for the primary side. 5 PGOOD O — Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 6 FLT1 O — Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 7 ALM1 O — Alarm 1 indicator. Open-drain output. When being used, requires external pull- up to VDDP. Float or tie to VSSP when not used. 8 VSSP — GND Ground supply for the primary side. All VSSP must be connected to the primary side ground. 9 VSSS — GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground.

10 RESP O — Used in conjunction with an external resistor connected to VSSS to adjust

comparator response time. When not being used, tie to VSSS.

11 ALM1_CMP I —

Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.

12 FLT1_CMP I —

Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS. 13 VDDM — P Generated mid-supply, nominal 5V. 14 VSSS — GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground. 15 VDDH — P Generated high supply, nominal 17V. 16 VDRV O — Active high driver output. (1) P = power, GND = ground, NC = no connect TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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FLT2_CMP PGOOD FLT1_CMP FLT2 FLT1 Figure 5-2. TPSI311x and TPSI311xL DVX Package, 16-Pin SSOP (Top View) PIN I/O TYPE(1) DESCRIPTION NO. NAME 1 EN I — Active high driver enable. Internal 500kΩ pull-down to VSSP. 2 CE I — Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP. 3 VSSP — GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground. 4 VDDP — P Power supply for the primary side. 5 PGOOD O — Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 6 FLT1 O — Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 7 FLT2 O — Fault 2 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 8 VSSP — GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground. 9 VSSS — GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground. comparator response time. When not being used, tie to VSSS.

11 FLT2_CMP I —

Analog comparator input. When FLT2_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT2 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS. Analog comparator input. When FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low regardless of EN state and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS. 13 VDDM — P Generated mid-supply, nominal 5V. 14 VSSS — GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground. 15 VDDH — P Generated high supply, nominal 17V. 16 VDRV O — Active high driver output. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSI3100

ALM2_CMP PGOOD ALM1_CMP ALM2 ALM1 Figure 5-3. TPSI312x DVX Package, 16-Pin SSOP (Top View) PIN I/O TYPE(1) DESCRIPTION NO. NAME 1 EN I — Active high driver enable. Internal 500kΩ pull-down to VSSP. 2 CE I — Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP. 3 VSSP — GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground. 4 VDDP — P Power supply for the primary side. 5 PGOOD O — Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 6 ALM1 O — Alarm 1 indicator. Open-drain output. When being used, requires external pull- up to VDDP. Float or tie to VSSP when not used. 7 ALM2 O — Alarm 2 indicator. Open-drain output. When being used, requires external pull- up to VDDP. Float or tie to VSSP when not used. 8 VSSP — GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground. 9 VSSS — GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground. comparator response time. When not being used, tie to VSSS.

11 ALM2_CMP I —

Analog comparator input. When ALM2_CMP voltage exceeds internal reference voltage, ALM2 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.

12 ALM1_CMP I —

Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS. 13 VDDM — P Generated mid-supply, nominal 5V. 14 VSSS — GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground. 15 VDDH — P Generated high supply, nominal 17V. 16 VDRV O — Active high driver output. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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ALM1_CMP PGOOD FLT1_CMP ALM1 FLT1 Figure 5-4. TPSI3133 DVX Package, 16-Pin SSOP (Top View) PIN I/O TYPE(1) DESCRIPTION NO. NAME 1 EN I — Active high driver enable. Internal 500kΩ pull-down to VSSP. 2 CE I — Active high input. When asserted low, device is disabled. Tie to VDDP when not used. Internal 500kΩ pull-down to VSSP. 3 VSSP — GND Ground supply for primary side. All VSSP pins must be connected to the primary side ground. 4 VDDP — P Power supply for the primary side. 5 PGOOD O — Power good indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 6 FLT1 O — Fault 1 indicator. Open-drain output. When being used, requires external pull-up to VDDP. Float or tie to VSSP when not used. 7 ALM1 O — Alarm 1 indicator. Open-drain output. When being used, requires external pull- up to VDDP. Float or tie to VSSP when not used. 8 VSSP — GND Ground supply for the primary side. All VSSP pins must be connected to the primary side ground. 9 VSSS — GND Ground supply for the secondary side. All VSSS pins must be connected to the secondary side ground. comparator response time. When not being used, tie to VSSS. Analog comparator input. When ALM1_CMP voltage exceeds internal reference voltage, ALM1 is asserted low within tALM_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS.

12 FLT1_CMP I/O —

Analog comparator input/output. When EN state is low, FLT1_CMP is actively pulled low. If EN state is high and FLT1_CMP voltage exceeds internal reference voltage, VDRV is automatically asserted low and FLT1 asserted low within tFLT_LATENCY. Internal 2.8MΩ pull-down to VSSS. When not being used, tie to VSSS. 13 VDDM — P Generated mid-supply, nominal 5V. 14 VSSS — GND Ground supply for secondary side. All VSSS pins must be connected to the secondary side ground. 15 VDDH — P Generated high supply, nominal 17V. 16 VDRV O — Active high driver output. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPSI3100

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) PARAMETER(1) MIN MAX UNIT Primary side supply(2) VDDP, EN, CE, PGOOD, FLT1 (TPSI310x, TPSI311x, TPSI3133), FLT2 (TPSI311x), ALM1 (TPSI310x, TPSI312x, TPSI3133), ALM2 (TPSI312x) –0.3 6 V Secondary side supply(3) FLT1_CMP (TPSI310x, TPSI311x, TPSI3133), FLT2_CMP (TPSI311x), ALM1_CMP (TPSI310x, TPSI312x, TPSI3133), ALM2_CMP (TPSI312x) –3 6 V Secondary side supply(3) VDRV –0.3 18 V VDDH –0.3 18 V VDDM –0.3 6 V VDDH-VDDM –0.3 13 V Secondary side supply(3) RESP –0.3 6 V Junction temperature, TJ Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to VSSP. Not all signals listed may be present pending device variant. (3) All voltage values are with respect to VSSS. Not all signals listed may be present pending device variant.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged device model (CDM), per ANSI/ ESDA/JEDEC JS-002(2) Corner pins (1, 8, 9, and 16) ±750 Other pins ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDDP Primary side supply voltage(1) 4.5 5.5 V EN Enable VDRV(1) (1) 0 5.5 V CE Chip enable(1) 0 5.5 V PGOOD Power good indicator(4) (1) 0 5.5 V FLTn Fault indicator(s).(4) (1) FLT1 (TPSI310x, TPSI311x, TPSI3133) FLT2 (TPSI311x) 0 5.5 V ALMn Alarm indicator(s).(4) (1) ALM1 (TPSI310x, TPSI311x, TPSI3133) ALM2 (TPSI312x) 0 5.5 V TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT CVDDP Decoupling capacitance on VDDP and VSSP(3) 1 20 µF CDIV1 (2) Decoupling capacitance across VDDH and VDDM(3) 0.003 15 µF CDIV2 (2) Decoupling capacitance across VDDM and VSSS(3) 0.1 40 µF QTOTAL Total charge to be driven by VDRV. 2500 nC RRESP Comparator response resistor from RESP to VSSS. 0 1000 kΩ IAUX Auxiliary current sourced from VDDM. 0 5 mA TA Ambient operating temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) All voltage values are with respect to VSSP. (2) CDIV1 and CDIV2 should be of same type and tolerance. CDIV2 capacitance value should be at least three times the capacitance value of CDIV1 i.e. CDIV2 ≥ 3 × CDIV1. (3) All capacitance values are absolute. Derating should be applied where necessary. (4) Open-drain fail-safe output. When being used, an external pull-up resistor greater than 20kΩ to VDDP is recommended. When not being used, float pin or connect to VSSP.

6.4 Thermal Information

THERMAL METRIC(1) DEVICE UNITDVX (SSOP)

16 PINS

RϴJA Junction-to-ambient thermal resistance 82.5 °C/W RϴJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RΘJB Junction-to-board thermal resistance 42.3 °C/W ψJT Junction-to-top characterization parameter 14.7 °C/W ΨJB Junction-to-board characterization parameter 41.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PD Maximum power dissipation, VDDP. TA = 25℃, VVDDP = 5.0V, fEN = 1kHz square wave, CVDRV = 1nF 250 mW

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT CREEPAGE AND TRACKING CLR External clearance(1) Shortest terminal-to-terminal distance through air ≥ 8 mm CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface ≥ 8 mm DTI Distance through the insulation Minimum internal gap (internal clearance) > 120 µm CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600VRMS I-IV Rated mains voltage ≤ 1000VRMS I-III www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSI3100

6.6 Insulation Specifications (continued)

PARAMETER TEST CONDITIONS VALUE UNIT DIN EN IEC 60747-17 (VDE 0884-17) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1697 VPK VIOWM Maximum isolation working voltage AC voltage (sine wave) 1200 VRMS DC voltage 1697 VDC VIOTM Maximum transient isolation voltage VTEST = VIOTM; t = 60s (qualification test) 4243 VPK VTEST = 1.2 × VIOTM; t = 1s (100% production test) 5091 VPK VIMP Maximum impulse voltage(2) Tested in air; 1.2/50µs waveform per IEC 62638-1 4500 VPK VIOSM Maximum surge isolation voltage(3) Tested in oil (qualification test); 1.2/50µs waveform per IEC 62638-1 5850 VPK qpd Apparent charge(4) Method a: After input-output safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM = 2036VPK, tm = 10s. ≤ 5 pCMethod a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s; Vpd(m) = 1.3 × VIORM = 2206VPK, tm = 10s. ≤ 5 Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1s; Vpd(m) = 1.5 × VIORM = 2546VPK, tm = 1s. ≤ 5 CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1MHz 3 pF RIO Insulation resistance, input to output(5) VIO = 500V, TA = 25°C > 1012 ΩVIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 VIO = 500V at TS =150°C > 109 Pollution degree 2 Climatic category 40/125/21 UL 1577 VISO Withstand isolation voltage VTEST = VISO = 3000VRMS, t = 60s (qualification), VTEST = 1.2 × VISO = 3600VRMS, t = 1s (100% production)

3000 VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications. (2) Testing is carried out in air to determine the intrinsic surge immunity of the package. (3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier. (4) Apparent charge is electrical discharge caused by a partial discharge (pd). (5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

Plan to certify according to DIN EN IEC 60747-17 (VDE 0884-17) Plan to certify under UL 1577 Component Recognition Program Basic insulation; Maximum transient isolation voltage, 4243VPK; Maximum repetitive peak isolation voltage, 1414VPK; Maximum surge isolation voltage, 5850VPK Single protection, 3000VRMS Certificate planned Certificate planned TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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6.8 Safety Limiting Values

PARAMETER(1) (2) TEST CONDITIONS MIN TYP MAX UNIT IS Safety input, output, or supply current RθJA = 82.5°C/W, VVDDP = 5.5V, TJ = 150°C, TA = 25°C 275 mA PS Safety input, output, or total power RθJA =82.5°C/W, TJ = 150°C, TA = 25°C 1.52 W TS Maximum safety temperature 150 °C (1) Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. (2) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction- to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF, CVDRV = 1nF, IAUX = 0mA. 50kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100kΩ to VSSS. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT COMMON CMTI Common-mode transient immunity, static. |VCM| = 1000V, VEN = 0V or VEN = 5V. 100 V/ns TSD Temperature shutdown VVDDP = 5V 173 ℃ TSDH Temperature shutdown hysteresis VVDDP = 5V 32 ℃ SUPPLY IVDDP_STBY VDDP current in standby VVDDP = 5V, EN = 0V, CE = 0V. Measure average current. 25 45 µA IVDDP_LOW VDDP average current in steady state VVDDP = 5V, EN = CE = 5V. Fault and alarm inputs tied to VSSP (device specific). IAUX = 0mA. Lowest power regulation. VVDDH in steady state, measure IVDDP. 5.3 mA IVDDP_HIGH VDDP average current in steady state VVDDP = 5V, EN = CE = 5V. Fault and alarm inputs tied to VSSS (device specific). Highest power regulation. VVDDH in steady state, measure IVDDP. 37 mA VVDDH VDDH output voltage VVDDP = 5V, EN = CE = 5V. Fault and alarm inputs tied to VSSS (device specific). 16 17 18 V VVDDM Average VDDM voltage when not sourcing current. VVDDP = 5V, EN = CE = 5V. Fault and alarm inputs tied to VSSS (device specific). 4.8 5.0 5.2 V IVDDH_STBY Average standby current of VDDH supply. VVDDP = 5V, EN = 0V, CE = 5V. Fault and alarm inputs tied to VSSS (device specific). 48 µA IVDDM_STBY Average standby current of VDDM supply. VVDDP = 5V, EN = 0V, CE = 5V. Fault and alarm inputs tied to VSSS (device specific). 105 µA POUT_VDDH Maximum power transfer to VDDH. VVDDP = 5V, EN = 0V, CE = 5V. 42 72.8 mW www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSI3100

6.9 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF, CVDRV = 1nF, IAUX = 0mA. 50kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100kΩ to VSSS. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDDM_IAUX Average VDDM voltage when sourcing external current. VVDDP = 5V, EN = 0V, steady state. Fault and alarm inputs tied to VSSS (device specific). Source IAUX = 5mA from VDDM, measure VVDDM. CDIV2 = 1µF 4.7 5.5 V SUPERVISORY VVDDP_UV_R VDDP undervoltage threshold rising VDDP rising. 3.9 4.1 4.35 V VVDDP_UV_F VDDP undervoltage threshold falling VDDP falling 3.8 3.9 4.25 V VVDDP_UV_HYS VDDP undervoltage threshold hysteresis 170 mV VVDDH_UV_R VDDH undervoltage threshold rising VDDH rising. 11.9 13 14.2 V VVDDH_UV_F VDDH undervoltage threshold falling. VDDH falling. 9.6 10.4 11.5 V VVDDH_UV_HYS VDDH undervoltage threshold hysteresis. 2.5 V VVDDM_UV_R VDDM undervoltage threshold rising VDDM rising. 3.4 3.7 3.9 V VVDDM_UV_F VDDM undervoltage threshold falling. VDDM falling. 3.1 3.4 3.7 V VVDDM_UV_HYS VDDM undervoltage threshold hysteresis. 0.3 V DRIVER VVDRV_H VDRV output voltage driven high VVDDP = 5V, EN = 5V. VVDDH in steady state, no DC loading. Fault and alarm inputs tied to VSSS (device specific). 16 17 18 V VVDRV_L VDRV output voltage driven low VVDDP = 5V, EN = 0V, VVDDH in steady state, VDRV sinking 10mA. Fault and alarm inputs tied to VSSS (device specific). 0.1 V IVDRV_PEAK VDRV peak output current during rise VVDDP = 5V, EN = 0V → 5V, VVDDH in steady state, measure peak current. Fault and alarm inputs tied to VSSS (device specific). 1.5 A VDRV peak output current during fall VVDDP = 5V, EN = 5V → 0V, VVDDH in steady state, measure peak current. Fault and alarm inputs tied to VSSS (device specific). 2.5 A RDSON_VDRV Driver on resistance in low state. Fault and alarm inputs tied to VSSS (device specific). 1.5 Ω Driver on resistance in high state. Fault and alarm inputs tied to VSSS (device specific). 3.5 Ω TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF, CVDRV = 1nF, IAUX = 0mA. 50kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100kΩ to VSSS. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VACT_CLAMP Active clamp voltage when engaged. VVDDP = 0V. Sink IVDRV = 300mA. Measure VDRV. 1.9 2.5 V DIGITAL INPUT/OUTPUT VIT_+(EN) Input threshold voltage rising on EN. VVDDP = 5V 2.3 2.5 2.7 V VIT_-(EN) Input threshold voltage falling on EN. VVDDP = 5V 1.7 1.9 2.0 V VIT_HYS(EN) Input threshold voltage hysteresis on EN. VVDDP = 5V 0.5 V VIT_+(CE) Input threshold voltage rising on CE. VVDDP = 5V 2.3 2.5 2.7 V VIT_-(CE) Input threshold voltage falling on CE. VVDDP = 5V 1.7 1.9 2.0 V VIT_HYS(CE) Input threshold voltage hysteresis on CE. VVDDP = 5V 0.5 V VOL Low level output voltage. PGOOD FLT1 (TPSI310x, TPSI311x, TPSI3133) FLT2 (TPSI311x) ALM1 (TPSI310x, TPSI312x, TPSI3133) ALM2 (TPSI32x) VVDDP = 4.5V to 5.5V, IOL = 2mA. Outputs enabled. 0.4 V IOL Low level output current. PGOOD FLT1 (TPSI310x, TPSI311x, TPSI3133) FLT2 (TPSI311x) ALM1 (TPSI310x, TPSI312x, TPSI3133) ALM2 (TPSI312x) VVDDP = 4.5V to 5.5V, VOL = 0.4V. Outputs enabled. -2 mA VOL_FLT_CMP Open-drain output, low level output voltage. FLT_CMP1 (TPSI3133) VVDDP = 4.5V to 5.5V, IOL = 2mA, CE = 1, EN = 0. 0.1 V IOL_FLT_CMP Open-drain output, low level output current. FLT_CMP1 (TPSI3133) VVDDP = 4.5V to 5.5V, VOL = 0.4V, CE = 1, EN = 0. -2 mA ILKG Leakage current. PGOOD FLT1 (TPSI310x, TPSI311x, TPSI3133) FLT2 (TPSI311x) ALM1 (TPSI310x, TPSI312x, TPSI3133) ALM2 (TPSI312x) VVDDP = 4.5V to 5.5V, Outputs disabled. 2 µA REN_PULLDOWN Internal resistor pull-down on EN. VVDDP = 5V 390 500 640 kΩ RCE_PULLDOWN Internal resistor pull-down on CE. VVDDP = 5V 390 500 640 kΩ REFERENCE www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSI3100

6.10 Switching Characteristics

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6.10 Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted). Typicals at TA = 25℃. CVDDP = 1µF, CDIV1 = 47nF, CDIV2 = 220nF, CVDRV = 1nF, IAUX = 0mA. 50kΩ pull-ups from FLT1, ALM1, PGOOD to VDDP. RRESP = 100kΩ to VSSS. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tR_VDRV VDRV rise time from EN rising to VDRV from 15% to 85% level VVDDP = 5V, VVDDH, VVDDM = steady state, EN = 0V → 5V, VVDRV = 2.25V to 12.75V. 10 ns tF_VDRV VDRV fall time from EN falling to VDRV from 85% to 15% level VVDDP = xV, VVDDH, VVDDM = steady state, EN = xV → 0V, VVDRV = 12.75V to 2.25V. 10 ns tREC_VDRV (1) Time VDRV remains low upon detection of a fault condition. VVDDP = 5V, VVDDH and VVDRV in steady state, EN = 5V, FLTn_CMP positive-pulse of 3V, 50µs pulse-width. Measure from FLTn_CMP going low (1.5V) to VVDRV = 7.5V. 165 270 µs COMPARATORS tPD_CMP_VDRV_DIS Propagation delay time, fault comparator output rising to VDRV asserted low. EN = CE = VDDP RRESP ≤ 10kΩ VUD = 100mV VOD = 30mV Measure VFLT_CMP crossing VREF to 50% VVDRV. 320 385 460 ns EN = CE = VDDP RRESP = 100kΩ. VUD = 100mV VOD = 30mV Measure VFLT_CMP crossing VREF to 50% VVDRV. 630 715 830 ns EN = CE = VDDP RRESP = 300kΩ. VUD = 100mV VOD = 30mV Measure VFLT_CMP crossing VREF to 50% VVDRV. 890 1375 1970 ns EN = CE = VDDP RRESP = 500kΩ. VUD = 100mV VOD = 30mV Measure VFLT_CMP crossing VREF to 50% VVDRV. 1275 2020 2950 ns tDEGLITCH_CMP_F Fault comparator falling output de- glitch. 4.2 5.7 8 µs tFLT_LATENCY Delay from rising or falling event detected by fault comparator and indicated on FLT1 output. EN = CE = VDDP RRESP = 500kΩ. VUD = 100mV VOD = 30mV Measure VFLT1_CMP rising or falling and crossing VREF to 50% FLT1. 30 µs tALM_LATENCY Delay from rising or falling event detected by alarm comparator and indicated on ALM1 output. EN = CE = VDDP RRESP = 500kΩ. VUD = 100mV VOD = 30mV Measure VALM1_CMP rising or falling and crossing VREF to 50% ALM1. 30 µs (1) On latched based devices, recovery timer is still in effect even though VDRV is latched low. If the fault condition is removed and EN is asserted low and then high to clear the fault, VDRV will remain asserted low until the recovery timer has elapsed. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSI3100

6.11 Insulation Characteristic Curves

T A (  C ) IS(mA) 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 0 2 2 0 2 4 0 2 6 0 2 8 0 3 0 0 Figure 6-1. Thermal Derating Curve for Limiting Current per VDE and IEC T A (  C ) PS(mW) 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 1 1 0 0 1 2 0 0 1 3 0 0 1 4 0 0 1 5 0 0 1 6 0 0 Figure 6-2. Thermal Derating Curve for Limiting Power per VDE and IEC TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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6.12 Typical Characteristics

T i m e (  s ) VVDRV, VVDDH, VVDDM, VEN(V) - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 - 2 . 5 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 V V D R V V E N V V D D M V V D D H VDDP = 5.0V TA = 25°C CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-3. tLH_VDRV T i m e (  s ) VVDRV, VVDDH, VVDDM, VEN(V) - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 - 2 . 5 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 V D R V E N V D D M V D D H VDDP = 5.0V TA = 25°C CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-4. tHL_VDRV C V D R V ( n F ) TLH_VDRV(s) 1 . 5 1 . 7 5 2 . 2 5 2 . 5 2 . 7 5 3 . 2 5 3 . 5 3 . 7 5 1 1 0 2 0 5 0 1 0 0 - 4 0  C 2 5  C 1 2 5  C VDDP = 5.0V CDIV1 = 3.3μF CDIV2 = 10μF Figure 6-5. tLH_VDRV versus CVDRV C V D R V ( n F ) THL_VDRV(s) 1 . 5 1 . 7 5 2 . 2 5 2 . 5 2 . 7 5 3 . 2 5 3 . 5 3 . 7 5 1 1 0 2 0 5 0 1 0 0 - 4 0  C 2 5  C 1 2 5  C VDDP = 5.0V CDIV1 = 3.3μF CDIV2 = 10μF Figure 6-6. tHL_VDRV versus CVDRV T i m e (  s ) VVDRV, VVDDH, VVDDM, VCE(V) - 2 0 0 - 1 2 0 - 4 0 4 0 1 2 0 2 0 0 2 8 0 3 6 0 4 4 0 5 2 0 6 0 0 - 5 - 2 . 5 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 2 0 V V D R V V C E V V D D M V V D D H VDDP = 5.0V TA = 25°C RRESP = 100kΩ CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-7. tLH_VDRV_CE T i m e (  s ) VVDRV, VVDDH, VVDDM, VCE(V) - 1 0 0 - 7 5 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 - 5 - 2 . 5 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 2 0 V V D R V V C E V V D D M V V D D H VDDP = 5.0V TA = 25°C RRESP = 100kΩ CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-8. tHL_VDRV_CE(zoomed in) www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSI3100

6.12 Typical Characteristics (continued)

T i m e ( m s ) VVDRV, VVDDH, VVDDM, VCE(V) - 2 - 1 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 - 5 - 2 . 5 2 . 5 7 . 5 1 0 1 2 . 5 1 5 1 7 . 5 2 0 V V D R V V C E V V D D M V V D D H VDDP = 5.0V TA = 25°C RRESP = 100kΩ CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-9. tHL_VDRV_CE(zoomed out) VDDP = 5.0V CDIV1 = 47nF CDIV2 = 220nF Figure 6-10. VVDDM versus IAUX T i m e (  s ) VVDRV, VFLT1_CMP, VFLT1B(V) - 2 - 1 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 V V D R V V F L T 1 _ C M P V F L T 1 B VDDP = 5.0V TA = 25°C RRESP = 100kΩ CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-11. tPD_CMP_VDRV_DIS, tFLT_LATENCY T i m e (  s ) VVDRV, VFLT1_CMP, VFLT1B(V) - 1 0 - 6 - 2 2 6 1 0 1 4 1 8 2 2 2 6 3 0 - 4 - 2 1 0 1 2 1 4 1 6 1 8 2 0 V D R V F L T 1 _ C M P F L T 1 VDDP = 5.0V TA = 25°C RRESP = 500kΩ CDIV1 = 47nF CDIV2 = 220nF CVDRV = 1nF Figure 6-12. tPD_CMP_VDRV_DIS, tFLT_LATENCY TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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7 Parameter Measurement Information

50% 50% tLH_VDRV tHL_VDRV VDDP VDDH 50% 50% tLH_VDDH tHL_VDRV_PD tR_VDRV tF_VDRV 85% 15% 90% 85% 15% tHL_VDDH 50%50% 10% 10% tHI_EN tLO_EN 50% tPER_EN Figure 7-1. VDRV Timing, (CE = 1 or CE = VDDP, FLTn_CMP = ALMn_CMP = 0) VDRV CE VDDH 50% 50% tLH_VDRV_CE tHL_VDRV_CE 10% 10% tLO_CE 50% Figure 7-2. VDRV Timing, (VDDP present, FLTn_CMP = ALMn_CMP = 0) FLTn_CMP EN VDRV tREC_VDRV tPD_CMP_VDRV_DIS tREC_VDRV tREC_VDRV tPD_CMP_VDRV_DIS FLTn tFLT_LATENCY tFLT_LATENCY Figure 7-3. VDRV Auto-Recovery Timing (CE = 1 or CE = VDDP) www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSI3100

+ VCM - VVDRV Pass/Fail criteria: Output must remain stable. CDIV2 CDIV1 GNDO GNDI 10k SIGNAL Control VDRV VDDH VDDM VSSS FLT1_CMP ALM1_CMP EN CE PGOOD VSSP VDDP ALM1 VSSP VSSS Control & Power Transfer SIGNAL POWER ISOLATION TPSI310x FLT1 – RESP 10k 10k Figure 7-4. Common-Mode Transient Immunity Test Circuit TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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8 Detailed Description

8.1 Overview

The TPSI3100 is a fully integrated isolated switch driver, which when combined with an external power switch, forms a complete isolated solid state relay solution. With a gate drive voltage of 17V with 1.5 and 2.5A peak source and sink current, a large availability of power switches can be used to meet many application needs. The TPSI3100 generates its own secondary bias supply from power received on its primary side, so no isolated secondary supply bias is required. The TPSI3100 provides additional power via the nominal 5V rail (VDDM) for use by auxiliary circuits to perform various function such as current and voltage monitoring or remote temperature detection. The TPSI3100 isolation is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than those found using traditional mechanical relays and optocouplers. The TPSI3100 integrates a communication back-channel that transfers status information from the secondary side to the primary side via open-drain outputs, PGOOD (Power Good), FLT1 (Fault 1), and ALM1 (Alarm 1). Dual high-speed comparators with an integrated shared voltage reference are used to assert FLT1 and ALM1. When the comparator input, FLT1_CMP, exceeds the voltage reference, the driver is immediately asserted low and FLT1 is also driven low, indicating to the system that a fault has occurred. This is useful for disabling the external switch with low latency on critical events, such as overcurrent detection. When the comparator input, ALM1_CMP, exceeds the voltage reference, ALM1 signal is asserted low, but no action is taken by the driver. This may be useful as an alarm or warning indicator for overtemperature or overvoltage events. The TPSI310xL series offers a latch based fault indicator. When a fault is detected, the driver and the fault indicator are asserted low and remain latched, until EN is asserted low. The TPSI310x series has a non-latched fault indicator. If the fault event is no longer present, FLT1 deasserts and the driver, after a specified recovery period, follows the state of the EN pin. If the fault event still remains, both the fault indicator and the driver remain asserted low. The TPSI310x and TPSI310xL device family has two voltage options for the integrated reference to meet a wide range of application needs. The Functional Block Diagram shows the primary side includes a transmitter that drives an alternating current into the primary winding of an integrated transformer which transfers power from the primary side to the secondary side. The transmitter operates at high frequency (80MHz, nominal) to optimally drive the transformer to its peak efficiency. In addition, the transmitter utilizes spread spectrum techniques to greatly improve EMI performance allowing many applications to achieve CISPR 25 - Class 5. During transmission, data information is transferred to the secondary side alongside with the power. On the secondary side, the voltage induced on the secondary winding of the transformer, is rectified and multiplied, and is regulated to the voltage level of VDDH. Lastly, the demodulator decodes the received data information and drives VDRV high or low, respective of the logic state of the EN pin. During each transfer of power from the primary side to the secondary side, back-channel state information is automatically sampled, encoded, and sent from the secondary side back to the primary side where it is decoded. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSI3100

8.2 Functional Block Diagram

ALM1_CMP FLT1_CMP Power Data FLT1 RESP VSSP VSSS Data VREF Figure 8-1. TPSI310x, TPSI310xL Rectifier Isolation Barrier Demodulator VSENSE VDDM VDDH VDRV VSSP Control VSSS Modulator EN VDDP Control Modulator Encoder Demodulator DecoderFLT2 CE PGOOD FLT2_CMP FLT1_CMP Power Data FLT1 RESP VSSP VSSS Data Figure 8-2. TPSI311x, TPSI311xL TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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ALM2_CMP ALM1_CMP Power Data ALM1 RESP VSSP VSSS Data Figure 8-3. TPSI312x Rectifier Isolation Barrier Demodulator VSENSE VDDM VDDH VDRV VSSP Control VSSS Modulator EN VDDP Control Modulator Encoder Demodulator DecoderALM1 CE PGOOD ALM1_CMP FLT1_CMP Power Data FLT1 RESP VSSP VSSS Data VREF Figure 8-4. TPSI3133

8.3 Feature Description

8.3.1 Transmission of the Enable State

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family uses a modulation scheme to transmit the switch enable (EN) state information across the isolation barrier. The transmitter modulates the EN signal with an internally generated, high frequency carrier, and differentially drives the primary winding of the isolation transformer. The receiver on the secondary side demodulates the received signal and asserts VDRV high or low based on the state information received.

8.3.2 Power Transmission

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family does not utilize a secondary side isolated bias supply for its power. The secondary side power is obtained by the transferring of the primary side input power from VDDP across the isolation transformer. The modulation scheme uses spread spectrum techniques to improve EMI performance assisting applications in meeting the CISPR 25 Class 5 standards. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSI3100

8.3.3 Gate Driver

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family has an integrated gate driver that provides a nominal 17V with 1.5 and 2.5A peak source and sink current sufficient for driving many power transistors. When driving external power transistors, TI recommends bypass capacitors (C DIV2 ≥ 3 * C DIV1) from VDDH to VDDM and VDDM to VSSS with an equivalent series capacitance of minimum of 30 times the equivalent gate capacitance. If optional auxiliary circuitry requires power, additional capacitance may be required.

8.3.4 Chip Enable (CE)

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family has an active high chip enable, CE. When CE is asserted high and VDDP is present, the device enters its active mode of operation and power transfer occurs from the primary side to the secondary side. When CE is asserted low while VDDP is present, the device enters standby and no power transfer occurs from primary side to the secondary side and VDRV will be asserted low. Over time, VDDH and VDDM fully discharge depending on the amount of loading present on these rails.

8.3.5 Comparators

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family devices include two identical isolated comparators. A simplified block diagram is shown in Figure 8-5. The function of the comparator, fault or alarm, depends on the device orderable in the family. The positive inputs (FLTn_CMP or ALMn_CMP) of each comparator monitor the voltage on these inputs referenced to VSSS. Both comparators share a single integrated voltage reference, VREF, with an accuracy of ±1.5% over voltage and temperature and is connected internally to the negative inputs of each comparator. The reference voltage is internal to the device and not available externally. The reference voltage level depends on the device orderable in the family. FLT1_CMP or ALM1_CMPCMP1_OUT CMP2_OUT VSSS FLT2_CMP or ALM1_CMP or ALM2_CMP VREF ± 1.5% Figure 8-5. Comparator Block Diagram

8.3.5.1 Fault Comparator

The TPSI310x and TPSI3133 devices include one fault comparator that is used to quickly assert the output driver, VDRV, low to allow for the fastest disable time of the external power switch. This is useful for critical events such as overcurrent protection (OCP) to protect the external power switch and downstream circuitry. The block diagram of the fault comparator is shown in Figure 8-6 . The TPSI311x devices have two fault comparators. This can be useful for applications such as bi-directional OCP or whenever there are two independent critical events required to protect the external power switch. The TPSI312x device does not support any fault comparators, only alarm comparators. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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SampleFLTn_BCC RRESP FLTn_CMP VREF ±1.5% RESP VSSS Filter Figure 8-6. Fault Comparator Block Diagram If the input voltage of the fault comparator, FLTn_CMP, exceeds the internal reference voltage, VREF, the comparator output asserts high. The comparator output is filtered and is adjustable via an external 1% resistor, RRESP, connected from RESP to VSSS. The filtering of low-to-high transitions of the comparator output is adjustable by RRESP. High-to-low transitions of the comparator output are filtered at a fixed setting. Filtering the comparator output allows for flexibility and application tradeoffs to help minimize false trigger events while still providing adequate protection. The filtered comparator output is then fed into the driver logic. If the comparator output low-to-high event passes through the filter, VDRV is immediately asserted low regardless of the state of EN. The TPSI310x, TPSI311x, and TPSI3133 fault comparators are not latched. Upon a fault condition, VDRV has a recovery timer that keeps VDRV low for a minimum time, t REC_VDRV. If a fault condition is removed (FLTn_CMP voltage falls below the internal reference voltage and passes through the filter), VDRV is held low until the recovery timer has elapsed. Once the recovery timer has elapsed, VDRV follows the state of EN. If a fault condition occurs before the recovery timer has elapsed, the recovery timer is restarted. The comparator output information is transferred to the primary side of the device via back-channel communication (BCC) over the isolation barrier. As shown in Figure 8-6 , any low-to-high transition of the comparator output (fault event) that passes through the filter is extended to make sure the event is captured by the sample logic. Any high-to-low transition of the comparator output (recovery event) that passes through the filter are not extended. A recovery event can be missed by the sample logic if the event does not last longer than the sample period. Therefore, priority is given to fault events over recovery events. FLTn open-drain output is asserted low upon the fault event. If a recovery event occurs and is captured by the sample logic, FLTn open-drain output is set to high-impedance, but VDRV remains asserted low until the recovery timer elapses. The TPSI310xL and TPSI311xL devices have latched fault comparators as shown in Figure 8-7. Fault events are latched and held until EN is asserted low. Upon a fault event, VDRV asserts low and is held until EN is asserted low and the recovery timer elapses. FLTn is also asserted low and held until EN is asserted low. If the fault event has recovered, FLTn is asserted high even if the recovery timer has not elapsed. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSI3100

SampleFLTn_BCC RRESP Filter FLTn_CMP VREF ±1.5% RESP VSSS Latch Recovery mer/logic Figure 8-7. Latched Fault Comparator Block Diagram

8.3.5.2 Alarm Comparator

The TPSI310x and TPSI3133 devices include one alarm comparator. The TPSI312x devices include two alarm comparators. An alarm comparator differs from the fault comparator in that the output state of the comparator has no direct control of the VDRV output driver. The block diagram of the alarm comparator is shown in Figure 8-8. Rising edge extensionSampleALM1_BCC RRESP Filter ALM1_CMP VREF ±1.5% RESP VSSS Figure 8-8. Alarm Comparator Block Diagram If the input voltage of the alarm comparator, ALM1_CMP, exceeds the internal reference voltage, VREF, the comparator output asserts high. The comparator output is filtered and is adjustable via an external 1% resistor, RRESP, connected from RESP to VSSS. The filtering of low-to-high transitions of the comparator output is adjustable by R RESP. High-to-low transitions of the comparator output are filtered at a fixed setting. The filter setting is shared by both the fault and alarm comparators and cannot be set independently. In addition, the alarm comparator is not latched. Similar to the fault comparator, the alarm comparator output information is transferred to the primary side of the device via back-channel communication (BCC) over the isolation barrier. As shown in Figure 8-8, any low-to-high TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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transition of the comparator output (alarm event) that passes through the filter is extended to make sure the event is captured by the sample logic. Any high-to-low transition of the comparator output (recovery event) that passes through the filter are not extended. A recovery event can be missed by the sample logic if the event does not last longer than the sample period. Therefore, priority is given to alarm events over recovery events. ALM1 open-drain output is asserted low upon the alarm event. If a recovery event occurs and is captured by the sample logic, ALM1 open-drain output is set to high-impedance.

8.3.5.3 Comparator De-glitch

For many applications, there is a tradeoff between detecting critical events and the false triggering of a non- critical events. The RESP pin allows for adjustment of the response time of the comparator based on the application needs. Selection of a 1% resistor from the RESP pin to VSSS allows for filtering of the comparator response. The amount of typical de-glitch, tDEGLITCH_CMP_R, on the comparator output high assertion is estimated using Equation 1, where tDEGLITCH_CMP_R units is nanoseconds and RRESP units is kilo-ohm. t DE G LI TC H _ C MP _ R n s = ma x 3.55 × R RE SP kΩ + 153 , 235 (1) If the comparator output high assertion exceeds the duration of t DEGLITCH_R, the comparator output is propagated. Comparator output low assertions are filtered at a fixed setting, tDEGLITCH_CMP_F.

8.3.6 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family implements an internal UVLO protection feature for both input (VDDP) and output power supplies (VDDM and VDDH). The device remains disabled until VDDP exceeds its rising UVLO threshold. When the VDDP supply voltage falls below its falling threshold voltage, the device attempts to send data information to quickly assert VDRV low, regardless of the state of EN. This depends on the rate of VDDP loss. If VDDP collapses too fast to send the information, a timeout mechanism ensures VDRV is asserted low within t HL_VDRV_PD. A VDDP ULVO event causes PGOOD, FLT1, and ALM1 to assert low. VDDH and VDDM UVLO circuits monitor the voltage on VDDH and VDDM, respectively. VDRV is only asserted high if both the VDDH and VDDM UVLO rising thresholds are surpassed. If either VDDH or VDDM fall below their respective UVLO falling thresholds, VDRV is immediately asserted low. The UVLO protection blocks feature hysteresis, which helps to improve immunity of VDRV to noise present on the VDDM and VDDH rails. During turn on and turn off, the driver sources and sinks a peak transient current, which can result in voltage drop of the VDDH and VDDM power supplies. The UVLO protection circuits ignores the associated noise during these normal switching transients.

8.3.7 Keep-Off Circuitry

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family contains keep-off circuitry on the output driver. The purpose of the keep-off circuitry is to clamp the gate voltage below an acceptable level to prevent the external power switch from turning on when no power is present on the secondary rails. The keep-off circuitry can be used to replace or greatly reduce the requirements of an external bleed-off resistor on the external power switch. Figure 8-9 shows a simplified schematic of the keep-off circuitry. Transistors MP1 and MN1 form the driver that provides the gate current to drive the external power switch (M1). When no power is available on the secondary, the 1M Ω resistor, is connected from the drain to gate of MN1, forming an NMOS diode configuration. Any external coupling into the VDRV signal, via the M1 parasitic gate-to-drain and gate-to-source capacitances, can cause the VDRV signal to rise. The diode configuration of MN1 sinks this current to keep VDRV from rising too high, clamping VDRV to VACT_CLAMP . This is sufficient to keep most power switches off. If desired, an additional resistance can also be placed (on the order of 250k Ω or higher) across the gate-to-source of M1. Note that any resistance applied requires power from the secondary supply in normal operation and must be accounted for in the overall power budget. In addition to the MN1 diode clamp, the body diode of MP1 can also help absorb any coupling into VDRV. The equivalent capacitance, C eq, which is the series combination of C DIV1 and C DIV2 is typically on the order of hundreds of nanofarads for most applications. If power transfer has ceased for some time, this capacitance www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPSI3100

is fully discharged to VSSS and clamps VDRV a diode above VSSS via the body diode of MP1 connected to VDDH. Any external coupling into the VDRV signal, via the M1 parasitic gate-to-drain and gate-to-source capacitances, is absorbed by Ceq, minimizing the voltage rise on VDRV. Ceq Cgd VDDH VDRV Cgs VSSS MP1 MN1 VS Figure 8-9. Keep-Off Circuitry

8.3.8 Thermal Shutdown

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family has an integrated temperature sensor. The sensor monitors its local temperature. When the sensor reaches its threshold, it automatically disables power transfer from the primary side to the secondary side, and sends data information to disable the driver, VDRV. The power transfer is disabled and VDRV is asserted low until the local temperature reduces enough to re-engage.

8.4 Device Operation

VDDP must be supplied independently by a low impedance external supply that can deliver the required power. When VDDP power is present and CE is a logic high, power transfers from the primary side to the secondary side. Setting the EN pin logic high or low asserts or deasserts VDRV, thereby enabling or disabling the external switch, respectively. Figure 8-10 shows the basic set-up required for proper operation which requires EN, VDDP, and VSSP signals. EN may be driven up to 5.5V which is normally driven from circuitry on the same rail as VDDP. In this example, the TPSI310x is being used to drive back-to-back MOSFETs in a common-source configuration. Driving back-to-back MOSFETs is required for AC switching applications or DC switching where reverse blocking is required. C VDDP provides the required decoupling capacitance for the VDDP supply. C DIV1 and CDIV2 provide the required decoupling capacitance of the VDDH/VDDM supply rails to provide peak current to drive the external MOSFETs. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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VDDP, CE VDDH VDRV EN VDDM PGOOD FLTn ALMn 4 x Burst Period (~100 µs) Figure 8-11. TPSI310x Typical Start-up (CE = VDDP, FLTn_CMP = 0, ALMn_CMP = 0) Figure 8-12 shows start up sequence where VDDP, CE, and EN signals are tied together.

At T1: VDDP powers up the device. FLTn, ALMn, and PGOOD are asserted low.
At T2 and T3: TPSI310x begins to transfer power from VDDP to the secondary side for a fixed burst period (25μs typical), which begins to charge up the VDDH and VDDM secondary side rails.
At T4: VDRV asserts high when both VDDH and VDDM are above their UVLO thresholds.
At T5, T6, and T7: After four burst periods, the FLTn, ALMn, and PGOOD are released and begin to reflect their respective status. In this specific example, it is assumed that VDDH and VDDM rails have charged up beyond their UVLO thresholds under the four burst periods (100μs). In this case, due to the PGOOD latency, PGOOD is asserted high after VDRV is asserted high. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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VDDP, CE, EN VDDH VDRV VDDM PGOOD FLTn ALMn 4 x Burst Period (~100 µs) Figure 8-12. TPSI310x Typical Start-up (CE = EN = VDDP, FLTn_CMP = 0, ALMn_CMP = 0) To reduce average power, the TPSI310x transfers power from the primary side to the secondary side in a burst fashion. The period of the burst is fixed while the burst on time is determined internally by the control loop regulating the VDDM voltage. The burst on time is automatically adjusted thereby optimizing power transfer for a given load condition. During power up, the device operates at the highest power setting which helps to quickly charge up the VDDM and VDDH rails. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPSI3100

8.5 Device Functional Modes

Table 8-1 summarizes the functional modes for the TPSI310x and TPSI310xL. Table 8-1. TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family, Functional Modes (1) (2) CE VDDP VDDH, VDDM EN VDRV PGOOD COMMENTS X Powered Down(4) Powered Down(6) X L Hi-Z Powered Down: VDRV output disabled, keep off circuitry applied. L Powered Up(3) Powered Down(6) X L L Disabled Operation: When CE is asserted low, power transfer to the secondary ceases. VDDH and VDDM rails discharge pending loading. VDRV output disabled, keep off circuitry applied. H Powered Up(3) Powered Up(5) L L H Normal Operation: VDRV output state follows logic state of EN logic state.H H H X Powered Down(4) Powered Up(5) X L L Disabled Operation: When VDDP is powered down, output driver is disabled automatically. If sufficient VDDP power is available, VDRV is disabled within the propagation delay, otherwise after the timeout duration. Keep off circuitry applied. (1) No alarm or fault conditions present (FLTn_CMP = ALMn_CMP = 0). (2) X: do-not-care. (3) VVDDP ≥ VDDP_UVLO threshold. (4) VVDDP < VDDP_UVLO threshold. (5) VVDDH ≥ VDDH_UVLO threshold and VVDDM ≥ VDDM_UVLO threshold. (6) VVDDH <VDDH_UVLO threshold or VVDDM < VDDM_UVLO threshold. Table 8-2 summarizes fault and comparator functional behavior. Table 8-2. FLTn, ALMn Functional Behavior (1) CE(2) FLTn_CMP(3) ALMn_CMP(4) FLTn (5) ALMn (5) COMMENTS L X X L L VDRV output disabled, keep off circuitry applied. H L L Hi-Z Hi-Z VDRV output follows state of EN pin. H L H Hi-Z L Fault detected. VDRV output asserted low until recovery timer elapses. On latched fault devices, VDRV asserts low and remains low until EN asserts low then high and recovery timer elapses. H H L L Hi-Z Alarm detected. VDRV output unchanged. H H H L L Fault and alarm detected. VDRV output asserted low until recovery timer elapses. On latched fault devices, VDRV asserts low and remains low until EN asserts low then high and recovery timer elapses. (1) Assumes VVDDP ≥ VDDP_UVLO threshold and device is fully powered in steady state conditions. (2) L: VCE < VIT_-(CE), H: VCE ≥ VIT_+(CE). (3) L: VFLTn_CMP < VREF, H: VFLTn_CMP ≥ VREF. (4) L: VALMn_CMP < VREF, H: VALMn_CMP ≥ VREF. (5) Hi-Z: Open-drain output disabled, L: Open-drain output enabled. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPSI310x is a fully integrated, isolated switch driver with integrated bias, which when combined with an external power switch, forms a complete isolated solid state relay solution. With a nominal gate drive voltage of 17V with 1.5A and 3.0A peak source and sink current, a large variety of external power switches such as MOSFETs, IGBTs, or SCRs can be chosen to meet a wide range of applications. The TPSI310x generates its own secondary bias supply from the power received from its primary side, so no isolated secondary supply bias is required. The secondary side provides a regulated, floating supply rail of 17V for driving a large variety of power switches with no need for a secondary bias supply. The TPSI310x can support driving single power switch, dual back- to-back, parallel power switches for a variety of AC or DC applications. The TPSI310x integrated isolation protection is extremely robust with much higher reliability, lower power consumption, and increased temperature ranges than those found using traditional mechanical relays and optocouplers. The TPSI310x integrates a communication back-channel that transfers various status information from the secondary side to the primary side via open-drain outputs, PGOOD (Power Good), FLT1 (Fault 1), and ALM1 (Alarm 1). Two high-speed comparators with an integrated shared voltage reference are used to assert FLT1 and ALM1. When the comparator input, FLT1_CMP, exceeds the voltage reference, the driver is immediately asserted low and FLT1 on the primary side is driven low after some latency, indicating a fault has occurred. This is useful for directly disabling the external switch from the secondary on critical events with low latency, such as short circuit detection. When the comparator input, ALM1_CMP, exceeds the voltage reference, ALM1 signal is asserted low on the primary side, but no action is taken by the driver. This may be useful as an alarm or warning indicator. The various devices offered in the family can be used in a broad range of applications, with just some examples shown here. Figure 9-1 shows a simplified schematic of a shunt based overcurrent protection for DC applications. As the voltage increases across R SHUNT, an alarm event is triggered upon crossing the VREF threshold of the alarm comparator and ALM1 asserts low notifying the system of the event. As the voltage increases further, a fault event is triggered upon crossing the VREF threshold of the fault comparator, which immediately asserts VDRV low to protect the FET and the downstream load. FLT1 asserts low notifying the system of the event. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPSI3100

FLT1_CMP ALM1_CMPFLT1 ALM1 EN VDDP RESP VDDH PGOOD VSSSVSSP CE CDIV1 CDIV2 RRESP VDC I/O I/O CVDDP Figure 9-1. TPSI3100 overcurrent protection with fault and alarm indicators Figure 9-2 shows a simplified schematic of a shunt based overcurrent protection using a current sense amplifier for DC applications. The current sense amplifier, with its low input offset, allows for using smaller value R SHUNT values for lower power losses for larger current ranges. As the voltage increases across R SHUNT, after being amplified by the current sense amplifier, an alarm event is triggered upon crossing the VREF threshold of the alarm comparator and ALM1 asserts low notifying the system of the event. As the voltage increases further, a fault event is triggered upon crossing the VREF threshold of the fault comparator, which immediately asserts VDRV low to protect the FET and the downstream load. FLT1 asserts low notifying the system of the event. VDD I/O I/O GND uC I/O LOAD TPSI310x VDRV VDDM FLT1_CMP ALM1_CMPFLT1 ALM1 EN VDDP RESP VDDH PGOOD VSSSVSSP CE CDIV1 CDIV2 RRESP – VDC I/O I/O CVDDP + RSHUNT Figure 9-2. TPSI310x overcurrent protection with current sense amplifier, fault and alarm indicators Figure 9-3 shows a simplified schematic of a shunt based overcurrent protection for AC applications. As the positive AC voltage increases across R SHUNT1, a fault event is triggered upon crossing the VREF threshold of the first fault comparator, which immediately asserts VDRV low to protect the back-to-back FETs and the downstream load. FLT1 asserts low notifying the system of the event. Similarly, as the negative AC voltage TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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FLT1_CMP FLT2_CMPFLT1 FLT2 EN VDDP RESP VDDH PGOOD VSSSVSSP CE CDIV1 CDIV2 RRESP I/O I/O CVDDP LOAD IN+ IN- GND VS GND RSHUNT IN+ IN- GND VS GND VAC Figure 9-4. TPSI311x Bi-directional overcurrent protection with current sense amplifiers, fault indicators Figure 9-5 shows a simplified schematic of overcurrent protection using DESAT protection for DC applications. This method is commonly used with IGBT power transistors. When the IGBT is off, FLT1_CMP is driven low internally by the TPSI3133. When the driver is being enabled, the voltage on FLT1_CMP begins to rise. As the IGBT turns on, under normal load conditions, its V CE drops quickly which causes the voltage on FLT1_CMP to remain below the fault comparator threshold. The time for when FLT1_CMP is released and V CE has dropped enough to keep a false fault event from being detected, is known as the blanking time. Adjusting RESP value can help increase the required blanking time or some capacitance may be added to FLT1_CMP. If overcurrent conditions occur, V CE begins to rise until the voltage on FLT1_CMP reaches the VREF threshold of the fault comparator. VDRV is asserted low to protect the IGBT and the downstream load. FLT1 asserts low notifying the system of the event. VDD I/O I/O GND uC I/O LOAD TPSI3133 VDRV VDDM FLT1_CMP ALM1_CMPFLT1 ALM1 EN VDDP RESP VDDH PGOOD VSSSVSSP CE CDIV1 CDIV2 RRESP VDC I/O I/O CVDDP Figure 9-5. TPSI3133 DESAT protection with fault indicator TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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9.2 Typical Application

The simplified circuit diagram shown in Figure 9-6 is a typical overcurrent protection application using the TPSI3100. The circuit uses the alarm comparator to signal a warning to the system via the ALM1 status indicator. The current is sensed by the voltage formed across the shunt resistor, R SHUNT, during load conditions. ALM1 asserts low when the alarm threshold is exceeded. The fault comparator is used to detect an overcurrent event and disables the driver at the set overcurrent threshold. The system is notified via the FLT1 status indicator asserting low. VDD GPIO GPIO GND uC GPIO SIGNAL Control VDRV VDDH VDDM VSSS FLT1_CMP ALM1_CMP EN CE PGOOD VSSP VDDP ALM1 VSSP VSSS Control & Power Transfer SIGNAL POWER ISOLATION TPSI310x FLT1 – RESP LOAD RSHUNT Figure 9-6. Typical Overcurrent Protection Application

9.2.1 Design Requirements

Table 9-1 lists the design requirements of the TPSI310x gate driver. The application requires driving external FETs. It includes circuitry for a two-level overcurrent protection that sends an alarm when the load current exceeds its threshold, and a fault when the load current exceeds its overcurrent threshold. Upon a fault, the driver is immediately disabled to protect the external FET and load. The TPSI3100 used in this example includes a 0.31V voltage reference. Table 9-1. TPSI310x Design Requirements DESIGN PARAMETERS Total gate capacitance 120nC FET turn-off time upon fault detection < 0.5µs Supply voltage (VDDP) 5V ±5% Overcurrent fault 8A ±10% Overcurrent alarm 4A ±10% Shunt resistor tolerance ±1%

9.2.2 Detailed Design Procedure

9.2.2.1 CDIV1, CDIV2 Capacitance

The CDIV1 and CDIV2 capacitors required depends on the amount of drop that can be tolerated on the VDDH rail during switching of the external load. The charge stored on the C DIV1 and CDIV2 capacitors is used to provide the current to the load during switching. During switching, charge sharing occurs and the voltage on VDDH drops. At a minimum, TI recommends that the total capacitance formed by the series combination of C DIV1 and C DIV2 be sized to be at least 30 times the total gate capacitance to be switched. This sizing results in an approximate 0.5V www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPSI3100

drop of the VDDH supply rail that is used to supply power to the VDRV signal. Equation 2 and Equation 3 can be to used to calculate the amount of capacitance required for a specified voltage drop. CDIV1 and CDIV2 must be of the same type and tolerance. C DI V 1 = n + 1 n × Q L O AD ∆ V , n ≥ 3.0 (2) C DI V 2 = n × C DI V 1 , n ≥ 3.0 (3) where

n is a real number greater than or equal to 3.0.
CDIV1 is the external capacitor from VDDH to VDDM.
CDIV2 is the external capacitor from VDDM to VSSS.
QLOAD is the total charge of the load from VDRV to VSSS.
ΔV is the voltage drop on VDDH when switching the load. Note CDIV1 and C DIV2 represent absolute capacitor and components selected must be adjusted for tolerances and any derating necessary to achieve the required capacitance. Larger values of ΔV can be used in the application, but excessive droop can cause the VDDH undervoltage lockout falling threshold (V VDDH_UVLO_F) to be reached and cause VDRV to be asserted low. Note that as the series combination of C DIV1 and C DIV2 capacitance increases relative to Q LOAD, the VDDH supply voltage drop decreases, but the initial charging of the VDDH supply voltage during power up increases. For this design, assuming n = 3 and ΔV = 0.5V, then C DI V 1 = 3 + 1 3 × 120 n C

0.5 V = 320 n F (4)

C DI V 2 = 3 × 320 n F = 960 nF (5)

9.2.2.2 Start-up Time and Recovery Time

As described in the Section 9.2.2.1 section, the start-up time of the fully discharged VDDH and VDDM rails depends on the amount of capacitance present on the VDDH and VDDM pins, as well as, power being used from VDDM for any auxiliary circuitry. The rate at which this capacitance is charged depends on the amount of power transferred from the primary side to the secondary side. At start up, the power regulation loop transfers more power until the VDDH and VDDM rails reach their steady state values.

9.2.2.3 RSHUNT, R1, and R2 Selection

The TPSI3100 has an internal nominal voltage reference (V REF) of 0.31V. This reference is shared by the fault and alarm comparator negative inputs. The alarm event should be detected when the load current, I LOAD, reaches 4A nominal. The required shunt resistor can be computed as: R SHU N T = V RE F I L O AD = 0.31 V 4 A = 77.5 m Ω (6) For this design, RSHUNT = 75mΩ, is used. From this, the nominal alarm current, IALM, detected can be computed: I AL M = V REF R S HU NT = 0.31 V 75 m Ω = 4.13 A (7) The fault event should be detected when the load current, I LOAD, reaches 8A nominal. This corresponds to a voltage drop across the shunt resistor of VSENSE_FLT: TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

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V SEN SE _ F L T = R SHU NT × I OC P = 75 m Ω × 8 A = 600 m V (8) Since the fault comparator threshold of the TPSI3100 is also the nominal voltage reference (V REF) of 0.31V, a resistor divider is required to scale the V SENSE_FLT voltage to the comparator input threshold (V REF). The divider ratio (DIV) required can be calculated from: DI V = V R EF V S EN SE _ F L T = 0.31 V 0.6 V = 0.517 (9) DI V = R 2 R 1 + R 2 (10) For this design, the divider (DIV) was selected as 0.5. Therefore, R1 = R2. This leads to a nominal overcurrent of: I OC P = V RE F D I V × R SHU NT = 0.31 V 0.5 × 75 mΩ = 8.27 A (11) The power dissipated in the shunt resistor while remaining at the alarm condition can be computed as: P SHU NT _ AL M = I AL M 2 × R S HU NT = 4.13 A 2 × 75 mΩ = 1.28 W (12) Similarly, the power dissipated in the shunt resistor at the overcurrent condition can be computed as: P SHU NT _ O CP = I OC P 2 × R S HU NT = 8.27 A 2 × 75 mΩ = 5.13 W (13) A power rating for the shunt resistor should be chosen that is sufficient to handle these power conditions compared to those experienced during normal loading. If the system can take necessary action in a timely manner upon an alarm condition, a 2W power rated resistor is deemed sufficient. An overcurrent event causes the driver to be disabled quickly by the TPSI3100, and the overload current exists for short duration. A more conservative approach is to select a 5W power rated resistor.

9.2.2.4 Overcurrent Fault Error

There are several sources of error that contribute to total error in the overcurrent detection accuracy. These include: 1. Voltage reference tolerance (includes comparator offset) 2. Shunt resistor tolerance 3. Divider resistor tolerances For this design, an overcurrent protection accuracy of ±10% is required. The voltage reference tolerance of the TPSI3100 can be found in the Electrical Characteristics section of the data sheet and includes the comparator offset error. The resistor tolerances of the resistor divider are chosen as 1%. The reference voltage tolerance is ±1.5%. Lastly, the selected shunt resistor tolerance is ±1%. It is assumed that all error contributors are independent variables, so that the total expected error adds in a root mean squared fashion as follows: % Er r OC P _ TOT AL = % Er r VR EF 2 + % Er r R 1 2 + % Er r R 2 2 + % E rr R SHU NT 2 0.5 (14) % Er r OC P _ TOT AL = 1.5% 2 + 1 % 2 + 1% 2 + 1% 2 0.5 = 2.3 % (15) www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: TPSI3100

9.2.2.5 Overcurrent Alarm Error

The total error for the alarm or warning indicator is similar to the overcurrent protection total error except the error contribution due to the resistor divider does not affect the total error. As before, it is assumed that all error contributors are independent variables, so that the total expected error adds in a root mean squared fashion as follows: % Er r AL M _ TOT AL = % E rr V RE F 2 + % E rr RSHU N T 2 0.5 (16) % Er r AL M _ TOT AL = 1.5 % 2 + 1% 2 0.5 = 1.8% (17)

9.2.2.6 VDDP Capacitance, CVDDP

For this design, 1μF in parallel with 100nF is used.

9.2.3 Application Curves

ALM1_CMP FLT1_CMP ALM1 FLT1 tALM_LATENCY tFLT_LATENCY tALM_LATENCY tFLT_LATENCY ILOAD tPD_CMP_VDRV_DIS tREC_VDRV0.6 V 0.3 V 0 V 0.3 V0.15 V 0 V 0 A 5 A 10 A t0 t1 t2 t3 t4 Figure 9-7. Overcurrent Protection Typical Timing and Behavior

At t0: VDRV is asserted high and the external FETs are supplying load current, ILOAD. ILOAD is in its normal operating range and is below the alarm level setting of 4A, nominal. ALM1_CMP and FLT1_CMP comparator input voltages are below the comparator threshold set by VREF of the TPSI3100 of 0.31V,nominal). ALM1 and FLT1 faults are asserted high pulled-up by external resistor pull-ups to VDDP.
At t1: ILOAD current increases and reaches the alarm level setting of 4A, nominal. ALM1_CMP comparator input voltage reaches its threshold of 0.31V and ALM1 asserts low within tALM_LATENCY. VDRV remains asserted high since the FLT1_CMP comparator input threshold has not been reached. FLT1 remains asserted high pulled-up by the external resistor pull-up to VDDP.
At t2: ILOAD current continues to increases and reaches the fault level setting of 8A, nominal. FLT1_CMP comparator input voltage reaches its threshold of 0.31V and VDRV is quickly asserted low to disable the external FETs. FLT1 asserts low within tFLT_LATENCY. ALM1 remains asserted low since the ALM1_CMP comparator input exceeds its threshold.
At t3: Since the FETs have been turned off, ILOAD, is removed. FLT1_CMP and ALM1_CMP comparator inputs drop below their thresholds, settling to VSSS. VDRV remains asserted low keeping the external FETs off for tREC_VDRV. FLT1 and ALM1 assert high within tFLT_LATENCY and tALM_LATENCY, respectively indicating to the system that fault and alarm conditions have been removed.
At t4: VDRV asserts high again since EN remains high, tREC_VDRV time has elapsed, and the fault condition is no longer present. The external FETs are enabled and supply ILOAD in its normal operating range. TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

Product Folder Links: TPSI3100

Figure 9-8 shows a typical waveform capture. At time 0 μs, a load current (I LOAD) pulse of over 5A is applied. Since this is above the alarm comparator threshold of 4.13A, ALM1 indicator is asserted low within tALM_LATENCY, in this case, near time 5 μs. Approximately at time 15µs, a load current pulse of over 10A is applied. Since this is above the fault comparator threshold of 8.27A, VDRV is quickly asserted low to protect the power FET, and ILOAD drops to 0A. FLT1 is asserted low within tFLT_LATENCY, in this case, near time 30μs. Both the fault and alarm comparator thresholds are exceeded on the second load current pulse. After I LOAD falls below both the fault and alarm comparator thresholds, ALM1 and FLT1 assert high near time 55μs, indicating no alarm or fault is present. VDRV remains asserted low until tREC_VDRV time elapses, near time 180μs. T i m e (  s ) VVDRV, VALM1B, VFLT1B(V) ILOAD(A) - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 1 7 5 2 0 0 - 2 . 5 - 5 0 - 2 . 5 2 . 5 0 5 2 . 5 7 . 5 5 1 0 7 . 5 1 2 . 5 1 0 1 5 1 2 . 5 1 7 . 5 1 5 2 0 1 7 . 5 V A L M 1 B V F L T 1 B I L O A D V V D R V Figure 9-8. Overcurrent Protection and VDRV Auto-recovery

9.3 Power Supply Recommendations

To help ensure a reliable supply voltage, TI recommends that the C VDDP capacitance from VDDP to VSSP consists of a 0.1 μF bypass capacitor for high frequency decoupling in parallel with a 1 μF for low frequency decoupling. Low-ESR and low-ESL capacitors must be connected close to the device between the VDDP and VSSP pins.

9.4 Layout

9.4.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family. Some key guidelines are:

Component placement: – Place the driver as close as possible to the power semiconductor to reduce the parasitic inductance of the gate loop on the PCB traces. – Connect low-ESR and low-ESL capacitors close to the device between the VDDH and VDDM pins and the VDDM and VSSS pins to bypass noise and to support high peak currents when turning on the external power transistor. – Connect low-ESR and low-ESL capacitors close to the device between the VDDP and VSSP pins. – Minimize parasitic capacitance on the RESP pin.
Grounding considerations: – Limit the high peak currents that charge and discharge the transistor gates to a minimal physical area. This limitation decreases the loop inductance and minimizes noise on the gate terminals of the transistors. Place the gate driver as close as possible to the transistors. – Connect the driver VSSS to the Kelvin connection of MOSFET source or IGBT emitter. If the power device does not have a split Kelvin source or emitter, connect the VSSS pin as close as possible to the source or emitter terminal of the power device package to separate the gate loop from the high power switching loop.

The TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family employs spread spectrum modulation (SSM) for optimized EMI performance. Depending on the system requirements and safety preferences of the system designer, additional measures to minimize EMI can be takes as follows: – Inductive components: A pair of ferrite beads or a common mode choke can be placed in series with VDDP supply and VSSP ground to increase the common mode loop impedance. – Capacitive components: Most designs already employ discrete Y capacitors or include parasitic Y capacitance between the high voltage and low voltage domains. Incorporating this Y capacitance on the same board as the TPSI310x, TPSI311x, TPSI312x, and TPSI3133 family, provides a capacitive return path from the secondary side to the primary side.

High-voltage considerations: – To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the driver device. TI recommends a PCB cutout or groove to prevent contamination that can compromise the isolation performance.
Thermal considerations: – Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-board thermal impedance (θJB). – If the system has multiple layers, TI also recommends connecting the VDDH and VSSS pins to internal ground or power planes through multiple vias of adequate size. These vias must be located close to the IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different high voltage planes are overlapping.

9.4.2 Layout Example

Figure 9-9 shows a PCB layout example with the signals and key components labeled. VDDP EN VSSP VSSP CE VDRV VDDH VDDM VSSS VSSS RESP ALM1_CMP PGOOD FLT1_CMP FLT ALM C CC RRR VDDP EN CE RSENSE R R C G K S D ... Secondary Side Ground Plane Primary Side Ground Plane R Figure 9-9. Layout example TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 www.ti.com

Product Folder Links: TPSI3100

10 Device and Documentation Support

10.1 Documentation Support

10.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, Isolation Glossary

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (December 2023) to Revision A (November 2024) Page

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPSI3100 SLVSHN4A – DECEMBER 2023 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TPSI3100

www.ti.com 8-Mar-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPSI3100LDVXR ACTIVE SO-MOD DVX 16 1000 TBD Call TI Call TI -40 to 125 Samples TPSI3100DVXR ACTIVE SO-MOD DVX 16 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 TI3100 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 8-Mar-2025 OTHER QUALIFIED VERSIONS OF TPSI3100 :

Automotive : TPSI3100-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Mar-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Mar-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSI3100DVXR SO-MOD DVX 16 1000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 0.275 GAGE PLANE 10.63

9.97 TYP

5.95 5.75 NOTE 3 7.6 7.4 NOTE 4 2X 4.55 14X 0.65 16X 0.354 0.154 2.6 MAX 0.33

0.13 TYP

2.286 0.3 0.1 0 -8 1.27 0.40 (1.4) SSOP - 2.6 mm max heightDVX0016A SMALL OUTLINE PACKAGE 4229509/B 09/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

0.25 C A B

A14.000 DETAIL A TYPICAL SCALE 2.000 A B C

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

16X (1.7) 16X (0.41) 14X (0.65) (9.7) SSOP - 2.6 mm max heightDVX0016A SMALL OUTLINE PACKAGE 4229509/B 09/2023 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SOLDER MASK DETAILS LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM SYMM 8 9 SEE SOLDER MASK DETAILS METAL EDGE SOLDER MASK OPENINGEXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.7) 16X (0.41) 14X (0.65) (9.7) SSOP - 2.6 mm max heightDVX0016A SMALL OUTLINE PACKAGE DWG_NO:3/REV:3 MM_YYYY:3 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 8X SYMM SYMM 8 9

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

TPSI3123 specifications and overview.

Summary

TPSI3100 Isolated Switch Driver With 17V Gate Drive, Integrated Bias Supply, and Dual Isolated Comparators NOVEMBER 2024

Description

TPSI3100 Isolated Switch Driver With 17V Gate Drive, Integrated Bias Supply, and Dual Isolated Comparators NOVEMBER 2024

Source title TPSI3123 Datasheet(PDF) - Texas Instruments

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