TPSF12C1QDYYRQ1

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TPSF12C1 Standalone Active EMI Filter for Common-mode Noise Mitigation in Single- Phase AC Power Systems MARCH 2023

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TPSF12C1 Standalone Active EMI Filter for Common-mode Noise Mitigation in Single- Phase AC Power Systems

1 Features

Functional Safety-Capable – Documentation available to aid functional safety system design
Voltage-sense, current-inject active EMI filter – Optimized for CISPR 11 and CISPR 32 Class B conducted EMI requirements – Low impedance for common-mode emissions over the applicable EMI frequency range (150 kHz to 3 MHz) – 50%+ reduction in choke size, weight and cost – Peak inject current of ±80 mA (typical) – Amplifier with unity gain bandwidth of 113 MHz
Wide supply voltage range of 8 V to 16 V
Junction temperature range of –40°C to 150°C
Simple external configuration for single-phase AC power systems – Integrated sensing filter and summing network – Low leakage current at line frequency – Simplified compensation network
Inherent protection features for robust design – Withstands surge of 5 kV (IEC 61000-4-5) with minimal external component count – Enable pin for remote ON and OFF control – VDD voltage UVLO protection with hysteresis – Thermal shutdown protection with hysteresis
4.2-mm × 2-mm SOT-23 14-pin (DYY) package

2 Applications

Power delivery – high-density server PSUs
HVAC motor control, aerospace and defense
Welders, inverters and other industrial systems
Telecom AC/DC rectifiers

3 Description

The TPSF12C1 is an active filter IC designed to reduce common-mode (CM) electromagnetic interference (EMI) in single-phase AC power systems. The active EMI filter (AEF) configured with voltage sense and current inject (VSCI) uses a capacitive multiplier circuit to emulate the Y-capacitors in a conventional passive filter design. The device senses the high-frequency noise on each power line using a set of sense capacitors and injects noise-canceling currents back into the power lines using an injection capacitor. The effective active capacitance is set by the circuit gain and the injection capacitance. The AEF sensing and injection impedances use relatively low capacitance values with small component footprints. The device includes integrated filtering, compensation and protection circuitry, and an enable input. The TPSF12C1 provides a very low impedance path for CM noise in the frequency range of interest for EMI measurement. Enabling up to 30 dB of CM noise reduction at the lower end of specified frequency ranges (for example, 150 kHz to 3 MHz) significantly reduces the size, weight and cost of the CM filter implementation.

Package Information

PART NUMBER PACKAGE(1) BODY SIZE (NOM) TPSF12C1 DYY (SOT-23-THIN, 14) 4.20 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Chassis (PE) IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJCSEN1CSEN2 SENSE1B SENSE2B TPSF12C1 L N 12 V AC/DC regulator Chassis Simplified Schematic EMI Mitigation Result ADVANCE INFORMATION TPSF12C1 SNVSCB9 – MARCH 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.3 Receiving Notification of Documentation Updates..20

11 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2023 * Initial Release TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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5 Device Comparison Table

DEVICE ORDERABLE PART NUMBER PHASES GRADE JUNCTION TEMPERATURE RANGE TPSF12C1 TPSF12C1DYYR 1 Commercial –40°C to 150°C TPSF12C3 TPSF12C3DYYR 3 Commerical –40°C to 150°C TPSF12C1-Q1 TPSF12C1QDYYRQ1 1 Automotive –40°C to 150°C TPSF12C3-Q1 TPSF12C3QDYYRQ1 3 Automotive –40°C to 150°C

6 Pin Configuration and Functions

Figure 6-1. 14-Pin SOT-23-THIN DYY Package (Top View) Table 6-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1, 3, 12 NC – No internal connection. Tie to the GND plane on the PCB. 2 VDD P Power supply for IC. Bypass to IGND with a 1-µF X7R ceramic capacitor.

4 SENSE1A I Sense input (power line or neutral)

5 SENSE1B I Sense input (power line or neutral)

6 SENSE2A I Sense input (power line or neutral)

7 SENSE2B I Sense input (power line or neutral)

8 EN I Enable signal to activate noise cancellation

9 REFGND G Reference ground (Kelvin connected to IGND)

10 COMP1 I Connection 1 for external compensation circuit

11 COMP2 I Connection 2 for external compensation circuit

13 INJ O Injection signal output

14 IGND G Injection ground

(1) P = Power, G = Ground, I = Input, O = Output www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPSF12C1

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) (1) MIN MAX UNIT Pin voltage VDD to IGND and REFGND –0.3 18 V Pin voltage SENSE1A, SENSE1B, SENSE2A, SENSE2B to REFGND –5.5 5.5 V Pin voltage COMP1 to IGND and REFGND –0.3 5.5 V Pin voltage COMP2 to IGND and REFGND –0.3 15 V Pin voltage INJ to IGND –0.3 VVDD + 0.3 V Pin voltage EN to IGND and REFGND –0.3 18 V Pin voltage IGND to REFGND –0.3 0.3 V Sink current INJ 150 mA Source current INJ 150 mA TJ Operating junction temperature –40 150 °C Tstg Storage temperature –55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted) MIN NOM MAX UNIT VVDD VDD voltage range 8 12 16 V VINJ Output voltage range 2 VVDD – 2 V VSENSE Sense voltage range –5 5 V VEN Pin voltage 0 16 V IINJ Output current range Source and sink magnitude 80 mA TA Operating ambient temperature –40 105 °C TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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7.4 Thermal Information

THERMAL METRIC(1) DYY (SOT-23-THIN) UNIT

14 PINS

RθJA Junction-to-ambient thermal resistance 94 °C/W RθJC(top) Junction-to-case (top) thermal resistance 43 °C/W RθJB Junction-to-board thermal resistance 30 °C/W ψJT Junction-to-top characterization parameter 1.3 °C/W ψJB Junction-to-board characterization parameter 28 °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics

Limits apply over the junction temperature (TJ) range of –40°C to 150°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VVDD = 12 V(1). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ VDD quiescent current SENSE1A, SENSE1B, SENSE2A, and SENSE2B grounded, VEN = 5 V, 8 V ≤ VVDD ≤ 16 V 6.25 12.5 23.5 mA ISD VDD shutdown supply current VEN = 0 V 50 µA SUPPLY VOLTAGE UVLO VVDD-UV-R UVLO rising threshold VVDD rising 7.5 7.7 7.95 V VVDD-UV-F UVLO falling threshold VVDD falling 6.4 6.7 7.0 V VVDD-UV-HYS UVLO hysteresis 0.96 V ENABLE VEN-H EN voltage high 2.2 V VEN-L EN voltage low 0.8 V REN EN pin pull-up resistance to VDD VEN = 0 V 900 kΩ IEN-LKG EN input leakage current VEN = 12 V 850 nA INPUT FILTER NETWORK ACM Gain from shorted power lines through single sense cap, CSEN, to COMP1 vs. REFGND CSEN = 2 µF, 60 Hz –42 dB CSEN = 2 µF, 50 kHz –4 CSEN = 2 µF, 500 kHz(2) –1.5 CSEN = 2 µF, 1 MHz(2) –1 ADM Gain from differential signal applied to SENSE lines to COMP1 vs. REFGND SENSE1A shorted to SENSE1B, SENSE2A shorted to SENSE2B, CSEN1 = CSEN2 = 1 µF, 60 Hz –78 dB SENSE1A shorted to SENSE1B, SENSE2A shorted to SENSE2B, CSEN1 = CSEN2 = 1 µF, 1 kHz –59 SENSE1A shorted to SENSE1B, SENSE2A shorted to SENSE2B, CSEN1 = CSEN2 = 1 µF, 500 kHz(2) –35 SENSE1A shorted to SENSE1B, SENSE2A shorted to SENSE2B, CSEN1 = CSEN2 = 1 µF, 1 MHz(2) –36 SENSE1A shorted to SENSE1B, SENSE2A shorted to SENSE2B, CSEN1 = CSEN2 = 1 µF, 10 MHz(2) –35 www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPSF12C1

7.5 Electrical Characteristics (continued)

8 V ≤ VVDD ≤ 16 V, See recommended

feedback network, 10 kHz 0 dB PSRR100 feedback network, 100 kHz 6 STARTUP tW Startup delay Period from VDD = EN applied until output valid 43 ms tSU EN high to valid output 12 ms tSD EN low to stop output signal 55 µs THERMAL SHUTDOWN TJ-SHD Thermal shutdown threshold(2) Temperature rising 175 °C TJ-HYS Thermal shutdown hysteresis(2) 20 °C (1) MIN and MAX limits are 100% production tested at 25ºC unless otherwise specified. Limits over the operating temperature range verified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). (2) Parameter specified by design, statistical analysis and production testing of correlated parameters.

7.6 System Characteristics

The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the typical (TYP) column apply to TJ = 25°C and VVDD = 12 V only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case of typical components over the temperature range of TJ = –40°C to 150°C. These specifications are not ensured by production testing. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY ISUPPLY Input supply current with INJ loaded 15 mA TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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8 Detailed Description

8.1 Overview

The TPSF12C1 is an active electromagnetic interference (EMI) filter controller that is designed to reduce common-mode (CM) conducted emissions in off-line power converter systems. The device senses the high- frequency noise on each power line using a set of Y-rated capacitors, CSEN1 and C SEN2, then injects noise- canceling currents back into the power lines using a Y-rated capacitor C INJ along with damping circuitry that ensures stability. The device includes integrated filtering, compensation and protection circuitry. The TPSF12C1 provides a very low impedance path for CM noise in the frequency range of interest for EMI measurement. This feature can achieve approximately 15 to 30 dB of CM noise reduction over the frequency range of interest, for example, 100 kHz to 3 MHz, helping to reduce the size of common-mode chokes. The TPSF12C1 operates over a supply voltage range of 8 V to 16 V and can withstand 18 V. The device features include:

Internal circuitry that simplifies compensation and design
Built-in supply voltage UVLO to ensure proper operation
Built-in thermal shutdown protection
An EN input that allows power saving when the system is idling The active EMI feature significantly reduces EMI filtering cost, size, and weight, while helping to meet CISPR 11 and CISPR 32 Class B EMI limits for conducted and radiated emissions. Leveraging a pin arrangement designed for simple layout that requires relatively few external components, the TPSF12C1 is specified for maximum ambient and junction temperatures of 105°C and 150°C, respectively.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Integrated Line Filter

The TPSF12C1 has a built-in input line filter. Because the entire filter is integrated in the device, matching is better than what can be achieved using discrete components. This filter not only removes virtually all input at line frequency, it also sums the signals from the sense inputs to create a signal that represents the common-mode noise signature without line-frequency components.

8.3.2 Compensation

The TPSF12C1 contains partial internal compensation that, when combined with two capacitors and a resistor between COMP1 and COMP2, forms a lead-lag network. This internal network allows fewer external components to be used.

8.3.3 Enable

The TPSF12C1 has an enable input, EN, that allows the device to be shut down, drastically reducing power consumption during intervals when EMI mitigation is not required. The typical quiescent current consumption is 12.5 mA and 50 μA when the device is enabled and disabled, respectively. Because many designs do not use this feature, a 900-k Ω pull up resistor connects internally between VDD and EN, allowing the EN pin to be left open. In addition, INJ is pulled low when the device is disabled to reduce the parasitic resistance in series with CINJ.

8.3.4 Supply Voltage UVLO Protection

To ensure that the TPSF12C1 operates safely while VDD is powered on and off as well as during brownout conditions, this device has a built-in UVLO protection to provide predictable behavior while VDD is below its operating voltage. UVLO releases when the VDD voltage exceeds 7.95 V, allowing normal operation. UVLO engages if the VDD voltage falls below approximately 6.6 V. There is approximately 1 V of UVLO hysteresis.

8.3.5 Thermal Shutdown Protection

The TPSF12C1 provides built-in overtemperature protection that shuts down the device if the junction temperature exceeds approximately 175°C. After junction temperature drops by approximately 20°C, the device restarts. This process is repeated until the ambient temperature or power dissipation is reduced.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides ON and OFF control for the TPSF12C1. When the EN voltage is below approximately 0.8 V, the device is in shutdown mode. Most internal circuitry is shutdown. The quiescent current in shutdown mode drops to 50 µA (typical). The TPSF12C1 also employs VDD internal undervoltage protection. If the VDD voltage is below its UV threshold, the IC remains off. The INJ output pulls to ground while in shutdown mode.

8.4.2 Active Mode

The TPSF12C1 is in active mode when V VDD is above its UVLO threshold, EN is high, and there is no overtemperature fault. The simplest way to enable operation is to connect EN to VDD, which allows startup when the applied supply voltage exceeds the UVLO threshold voltage. In this mode, the device amplifies signals on COMP2 and outputs the amplified signal on the INJ pin. TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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9 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The TPSF12C1 common-mode AEF IC helps to improve the CM EMI signature of single-phase power systems. The device provides a very low impedance path for CM noise in the frequency range of interest for EMI measurement and helps to meet prescribed limits for EMI standards, such as:

CISPR 11, EN 55011 – Industrial, Scientific and Medical (ISM) applications
CISPR 25, EN 55025 – Automotive applications
CISPR 32, EN 55032 – Multimedia applications To expedite and streamline the process of designing of a TPSF12C1-based solution, a comprehensive TPSF12C1 quickstart calculator is available by download to assist the system designer with component selection for a given application.

9.2 Typical Applications

For the circuit schematic, bill of materials, PCB layout files, and test results of a TPSF12C1-powered implementation, see the TPSF12C1 EVM.

9.2.1 Design 1 – AEF Circuit for High-Density 3-kW Server Power Supply

Figure 9-1 shows a schematic diagram of a 3-kW high-density server power supply with conventional two-stage passive EMI filter. The CM chokes and Y-capacitors provide CM filtering, whereas the leakage inductance of the CM chokes and the X-capacitors provide DM filtering. Similar to TI reference designs PMP23069 and PMP41006, the circuit uses a single-phase bridgeless power-factor correction (PFC) front-end. The DC/DC stage, which provides galvanic isolation and step-down voltage regulation, is a phase-shift full-bridge (PSFB) topology with center-tapped secondary-side rectifier. The TTPL PFC stage and isolated DC/DC stage run at fixed switching freqeuncies of 65 kHz and 200 kHz, respectively. Even though the use of LMG3522-Q1 GaN switches with top-side cooling enables a high power density, the conventional passive EMI filter still occupies at least 20% of the total solution size. AC mains Chassis (PE) CY1 CY2 CX2 CX3CX1 LCM1 LCM2 CY3 CY4 = Single-phase TTPL PFC stage = PSFB DC/DC stage Figure 9-1. Simplified Circuit Schematic of a Server Power Supply With a Conventional Two-Stage EMI Filter www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: TPSF12C1

Note that the DC/DC stage in particular increases the CM EMI signature based on the high dv/dt of the GaN switches, the transformer interwinding capacitance as well as the various switch-node parasitic capacitances to chassis ground. This application example replaces the two Y-capacitors, designated as CY3 and C Y4 in Figure 9-1 , with a single-phase AEF circuit using the TPSF12C1. See Figure 9-2. The AEF circuit provides capacitive multiplication of the inject capacitor, which reduces the inductance value and thus the size, weight, and cost of the CM chokes, now designated as L CM1-AEF and L CM2-AEF. The total capacitance of the sense and inject capacitors is kept similar to that of the replaced Y-capacitors, which results in the the line-frequency leakage current remaining effectively unchanged. AC mains Chassis (PE) CX2 CX3CX1 LCM1-AEF LCM2-AEF RGCG1 IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJCSEN1CSEN2 Server power supply Chassis CG2 CD1 RD2 CD2 RD3CD3 CVDD Chassis-referred power supply RD1 RD1A SENSE1B SENSE2B TPSF12C1 L N = PFC + isolated DC/DC = Single-phase AEF IC DINJ From MCU = Sense, inject capacitors CY1 CY2 Figure 9-2. Circuit Schematic of a Single-phase Server Power Supply With AEF Circuit Connected

9.2.1.1 Design Requirements

Table 9-1 shows the intended operating parameters for this application example. Table 9-1. Design Parameters DESIGN PARAMETER VALUE AC input voltage range 85 V to 265 V RMS AC input line frequency 47 Hz to 63 Hz Input RMS current (maximum) 16 A DC output voltage 48 V Rated output power at high line 3 kW Rated output power at low line 1.5 kW AC/DC stage switching frequency 65 kHz DC/DC stage switching frequency 200 kHz TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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9.2.1.2 Detailed Design Procedure

Table 9-2 gives the selected component values, which are the same as those used in the TPSF12C1 EVM. This design uses a TVS diode placed at the low-voltage side of the inject capacitor for clamping during input surge conditions. Table 9-2. AEF Circuit Components for Application Circuit 1 REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER(1) PART NUMBER CSEN1, CSEN2 2 Capacitor, ceramic, 680 pF, 300 VAC, Y2 MuRata DE2B3SA681KN3AX02F CINJ 1 Capacitor, ceramic, 4.7 nF, 300 VAC, Y2 MuRata DE2E3SA472MA3BX02F CD1 1 Capacitor, ceramic, 4.7 nF, 50 V, 0603 Various – CD2 1 Capacitor, ceramic, 22 nF, 50 V, 0603 Various – CD3 1 Capacitor, ceramic, 4.7 nF, 50 V, 0603 Various – CG1 1 Capacitor, ceramic, 10 nF, 50 V, 0603 Various – CG2 1 Capacitor, ceramic, 10 pF, 50 V, 0603 Various – CVDD 1 Capacitor, ceramic, 1 µF, 25 V, X7R, 0603 Various – DINJ 1 TVS diode, bidirectional, 24 V, SOD-323 Eaton STS321240B301 RD1 1 Resistor, 1 kΩ, 0.1 W, 0603 Various – RD1A 1 Resistor, 50 Ω, 0.1 W, 0603 Various – RD2 1 Resistor, 200 Ω, 0.1 W, 0603 Various – RD3 1 Resistor, 698 Ω, 0.1 W, 0603 Various – RG 1 Resistor, 1.5 kΩ, 0.1 W, 0603 Various – U1 1 TPSF12C1 common-mode AEF IC for single-phase power systems Texas Instruments TPSF12C1DYYR (1) See the Third-Party Products Disclaimer. More generally, the TPSF12C1 AEF IC is designed to operate with a wide range of passive filter components and system parameters.

9.2.1.2.1 Sense Capacitors

The sense pins of the TPSF12C1 feed into a second-order high-pass filter and signal combiner within the IC, which rejects the line-frequency and DM components of the power line voltages, extracting the high-frequency CM component. These sense pins operate in pairs: SENSE1A and SENSE2A connect to SENSE1B and SENSE2B, respectively. The sense pins externally interface to the power lines using Y-rated capacitors, designated as CSEN1 and CSEN2 in Figure 9-2. Choose Y2-rated sense capacitors of 680 pF, 300 VAC in this application to establish voltages at the SENSE pins of 3-V peak-to-peak when operating at maximum line voltage.

9.2.1.2.2 Inject Capacitor

The INJ node interfaces to a power line using a Y-rated capacitor, designated as C INJ in Figure 9-2. Choose a Y2-rated inject capacitor of 4.7 nF, 300 VAC in this design to accommodate an AC swing at INJ with at least a 2-V margin of headroom from the positive and negative supply rails. The INJ pin biases at half the VDD supply voltage. Assuming a 12-V supply rail and allowing 2 V of upper and lower headroom, this implies that a swing of ±4 V is available around the DC operating point.

9.2.1.2.3 Compensation Network

The CM noise signal derived from the internal sensing filter and summation network of the TPSF12C1 is internally inverted and amplified by a gain stage. The components between the COMP1 and COMP2 pins of the IC, designated as as RG, CG1 and CG2 in Figure 9-2, set the gain characteristic. More specifically, resistor RG establishes a high midband AEF gain at frequencies where EMI filtering is required. Capacitor CG1 increases the impedance of that branch at low frequencies, which sets a lower AEF amplifer gain www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPSF12C1

to further reject line-frequency components appearing at the INJ output. Capacitor C G2 preserves gain at high frequencies, which extends the AEF bandwidth. Choose a value for R G between 1 kΩ and 2 kΩ. A resistance of 1.5 k Ω is a common choice and selected in this example to set a midband gain of 50 dB. Choose capacitances for CG1 and CG2 of 10 nF and 10 pF, respectively, which establishes a gain rolloff below approximately 10 kHz for line-and low-frequency attenuation.

9.2.1.2.4 Injection Network

The components connected between the INJ pin and inject capacitor establish a damped injection network. Damping is specifically required to manage resonance between the CM choke inductance and inject capacitance, which manifests in the AEF loop gain as a pair of complex zeros. Figure 9-3 highlights three specific RC branches: R D1, RD1A and CD1 form one branch from the INJ pin; R D2 and CD2 in series connect to GND; RD3 and CD3 in parallel connect to the inject capacitor. AC mains Chassis (PE) CY1 CY2 CX2 CX3CX1 LCM1-AEF LCM2-AEF RGCG1 IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJCSEN1CSEN2 AC/DC regulator Chassis CG2 CD1 RD2 CD2 RD3 CD3 CVDD 12 V RD1 RD1A SENSE1B SENSE2B TPSF12C1 L N = ZD1 branch = ZD2 branch DINJ = ZD3 branch ZD1 ZD3 ZD2 Figure 9-3. Injection Network Based on the sensing and injection mechanism, the AEF circuit presents a very low impedance to CM noise. Given the three damping impedance branches highlighted in Figure 9-3 , Equation 1 approximates the AEF impedance as: (1) where the term G AEF is the gain from the power lines to the INJ node (see the TPSF12C1 quickstart calculator for related detail). Equation 1 shows that the impedance ZINJ appears in series with ZD3 and a parallel combination of ZD1 and ZD2. Furthermore, the gain GAEF is reduced by the voltage divider ratio between Z D2 and ZD1. These effects combine to increase the effective impedance of the AEF and hence reduce its attenuation performance, thus illustrating a trade-off between performance and stability. TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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So while an injection network is needed for stability, it also adds impedance in series with inject capacitor, thus compromising EMI mitigation. As shown below, the user can minimize the impact on performance with careful and appropriate design. Illustrated in Figure 9-4, at low frequencies in the range of 5 kHz to 50 kHz, components R D1 and C D2 provide compensation and RD3 damps the effects of LC resonance. At higher frequencies (above 10 kHz), the dominant component impedance of each branch transitions to enable better attenuation performance:

RD1 transitions to CD1
CD2 transitions to RD2
RD3 transitions to CD3 Finally, CD1 transitions to R D1A if needed for phase margin of the AEF loop at high frequencies, typically above 100 kHz. When viewed in a clockwise direction, Figure 9-4 shows these transitions in sequence as frequency increases. CG1 IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJ CSEN1CSEN2 CD2 RD3 12 V RD1SENSE1B SENSE2B TPSF12C1 Low-frequency equivalent circuit RD3 in series with inject capacitor CINJ provides damping at low frequency RC filter (RD1, CD2) provides compensation at low frequency for stability RG IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJCSEN1CSEN2 CD1 CD2 RD3 12 V SENSE1B SENSE2B TPSF12C1 Mid-frequency equivalent circuit The impedance of CD1 shunts that of RD1 as frequency increases. Lower impedance in series with CINJ helps AEF performance. CD2 > CD1 Increasing frequency RG IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJCSEN1CSEN2 CD1 12 V SENSE1B SENSE2B TPSF12C1 High-frequency equivalent circuit As frequency increases, the impedance of CD3 shunts that of RD3, which helps attenuation performance. CD3 CINJ Increasing frequency CD3 RD2 IGND VDD INJ EN COMP1 SENSE1A SENSE2A COMP2 REFGND CINJ CSEN1CSEN2 12 V SENSE1B SENSE2B TPSF12C1 Highest-frequency equivalent circuit At high frequencies, the impedance of RD1A exceeds that of CD1. RD1A provides damping and improves the phase margin of the AEF loop CD3 RD2 Increasing frequency RD1A CG2 At higher frequency, the impedance of RD2 exceeds that of CD2, resulting in RD2 and CD1 forming a high- pass filter, which maximizes VINJD VINJD Figure 9-4. Dominant Components of the Injection Network vs Frequency www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPSF12C1

Below are basic guidelines to select the component values for the injection network: 1. The undamped loop gain characteristic is likely to be unstable within the range of 5 kHz to 50 kHz, which, as mentioned previously, relates to an LC resonance between CM choke inductance and inject capacitance. Observe from circuit simulation – or by using the TPSF12C1 quickstart calculator – the frequency, fLFstability, at which the phase crosses –180° with positive gain, indicating negative gain margin. 2. Choose a corner frequency with RD1 and CD2 equal to one fifth of the instability frequency: (2) Assigning RD1 = 1 kΩ and assuming instablity at 35 kHz, use Equation 3 to find a value for the capacitance of CD2: (3) 3. Select CD1 < CD2, where a typical choice is CD1 = CD2/5 = 4.7 nF. 4. Choose the resistance of RD2 such that the RD2, CD2 corner frequency is equal to that of RD1, CD1: (4) 5. Select the resistance of RD3 to damp the resonance around the instability frequency, fLFstability.

A typical choice for RD3 is 500 Ω to 1 kΩ.
Assign CD3 equal to CINJ or a suitable value such that the RD3, CD3 corner frequency is less than switching frequency.
A lower resistance for RD3 results in more damping but at the penalty of reduced high-frequency attenuation (or forces a higher value for CD3 to maintain the applicable corner frequency below the switching frequency). 6. Select a resistance for RD1A of 50 Ω to improve the phase margin of the AEF loop (if needed).

9.2.1.2.5 Surge Protection

While the sense pins have internal clamp protection, the higher value of inject capacitance produces larger currents during surge events and thus requires external protection. Place a bidirectional TVS diode on the low-voltage side of the inject capacitor with standoff voltage of 24 V. Using the SOD-323 packaged device given in Table 9-2, clamping occurs at 40 V and 50 V with surge currents of 1 A and 8 A, respectively. TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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9.2.1.3 Application Curves

Unless otherwise indicated, VVDD = VEN = 12 V. AEF disabled AEF enabled –29dB Figure 9-5. EMI Mitigation Result with AEF On and Off (EN Tied High and Low) VLINE 500 V/DIV VSENSE1A 10 V/DIV ISENSE1A,1B 2 A/DIV VINJ-C 20 V/DIV 1 µs/DIV INJ TVS diode clamps SENSE internal protection clamps VLINE 500 V/DIV VSENSE1A 10 V/DIV ISENSE1A,1B 2 A/DIV VINJ-C 20 V/DIV 200 µs/DIV Negative undershoot eventually decays INJ TVS diode clamps SENSE internal protection clamps (a) (b) Figure 9-6. IEC 61000-4-5 Positive Surge, 5-kV Single Strike – 1 µs/div (a), 200 µs/div (b) (a) (b) INJ TVS diode clamps SENSE internal protection clamps INJ TVS diode clamps SENSE internal protection clamps Positive overshoot eventually decaysVLINE 500 V/DIV VINJ-C 20 V/DIV VSENSE1A 10 V/DIV ISENSE1A,1B 2 A/DIV 1 s/DIV VLINE 500 V/DIV VINJ-C 20 V/DIV VSENSE1A 10 V/DIV ISENSE1A,1B 2 A/DIV 200 s/DIV Figure 9-7. IEC 61000-4-5 Negative Surge, 5-kV Single Strike – 1 µs/div (a), 200 µs/div (b) www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPSF12C1

ISEN1A,1B 2 A/DIV IINJ 10 A/DIV VSENSE1A 10 V/DIV 10 s/DIV (a) (b) VLINE 500 V/DIV ISEN1A,1B 2 A/DIV IINJ 10 A/DIV VSENSE1A 10 V/DIV 10 s/DIV Figure 9-8. IEC 61000-4-5 Surge, 5-kV Repetitive Strike at 10-Second Intervals – Positive (a), Negative (b)

9.3 Power Supply Recommendations

The TPSF12C1 AEF IC operates over a wide supply voltage range of 8 V to 16 V (typically 12 V) and is referenced to chassis ground of the system. The characteristics of this VDD bias supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the VDD supply must be capable of delivering the required supply current to the loaded AEF circuit. The supply rail can already be present in the system or can be derived using a low-cost solution with an auxiliary winding from an isolated flyback regulator. Connect a 1-µF ceramic capacitor close to the VDD and IGND pins of the TPSF12C1. Ensure that the VDD ripple voltage is less than 50 mV peak-to-peak.

9.4 Layout

Proper PCB design and layout is important in active EMI circuits (where high regulator voltage and current slew rates exist) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of the design depends to a large extent on PCB layout.

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze AEF performance. Figure 9-9 and Figure 9-10 show a recommended layout for the TPSF12C1 with optimized placement and routing of the IC and small-signal components. Figure 9-11 shows an example filter board design with CM chokes, X-capacitors and Y-capacitors along with a receptacle for easy connection of an AEF daughterboard.

Route the sense lines S1 and S2 away from the INJ line. Avoid coupling between sense and inject traces.
Place a ceramic capacitor close to the VDD and IGND pins. Minimize the area of the loop to the VDD and IGND pins.
Place the compensation network copnponents close to the COMP1 and COMP2 pins. Reduce noise sensitivity of the feedback compensation network path by placing components RG, CG1 and CG2 close to the COMP pins. COMP2 is the inverting input to the AEF anplifier and represents a high-impedance node sensitive to noise.
Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal impedance. Provide adequate heatsinking for the TPSF12C1 to keep the junction temperature below 150°C. A top-side ground plane is an important heat-dissipating area. Use several heat-sinking vias to connect IGND (pin 14) and REFGND (pin 9) to the PCB ground plane. TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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9.4.2 Layout Example

Figure 9-9. Typical Layout Keep the VDD capacitor close to the VDD pin Route sense traces S1, S2, S3 and S4 away from the INJ trace Keep the damping network close to the INJ pin Place the compensation network close to the COMP1 and COMP2 pins INJ pin probe point Top layer copper Legend Layer-2 GND plane Top solder Figure 9-10. Typical Top-Layer Design www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPSF12C1

Figure 9-11. Typical Filter Board Design TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

10.1.2 Development Support

All AEF devices from the family shown in Table 10-1 are rated for an ambient temperature up to 105°C and are functional safety capable. Table 10-1. Common-mode AEF IC Family DEVICE ORDERABLE PART NUMBER PHASES GRADE JUNCTION TEMPERATURE RANGE TPSF12C1 TPSF12C1DYYR 1 Commercial –40°C to 150°C TPSF12C3 TPSF12C3DYYR 3 Commercial –40°C to 150°C TPSF12C1-Q1 TPSF12C1QDYYRQ1 1 Automotive –40°C to 150°C TPSF12C3-Q1 TPSF12C3QDYYRQ1 3 Automotive –40°C to 150°C For development support see the following:

TPSF12C1 quickstart calculator
TPSF12C1 EVM Altium layout source files
TPSF12C1 PSPICE for TI and SIMPLIS simulation models
TPSF12C1 EVM user's guide
For TI's reference design library, visit TI Reference Design library
To design a low-EMI power supply, review TI's comprehensive EMI Training Series
TI Reference Designs: – 3-kW, 180-W/in3 single-phase totem-pole bridgeless PFC reference design with 16-A max input – 1-kW reference design with CCM totem pole PFC and current-mode LLC realized by C2000™ and GaN – 7.4-kW on-board charger reference design with CCM totem pole PFC and CLLLC DC/DC using C2000™ MCU – GaN-based, 6.6-kW, bidirectional, onboard charger reference design – 10-kW, bidirectional three-phase three-level (T-type) inverter and PFC reference design
Technical Articles: – Texas Instruments, How a stand-alone active EMI filter IC shrinks common-mode filter size – Texas Instruments, How to reduce EMI and shrink power-supply size with an integrated active EMI filter – Texas Instruments, How device-level features and package options can help minimize EMI In automotive designs – Texas Instruments, How to use slew rate for EMI control
White Papers: – Texas Instruments, How Active EMI Filter ICs Mitigate Common-Mode Emissions and Save PCB Space in Single- and Three-Phase Systems – Texas Instruments, An Overview of Conducted EMI Specifications for Power Supplies – Texas Instruments, An Overview of Radiated EMI Specifications for Power Supplies
To view a related device of this product, see the TPSF12C3 three-phase active EMI filter for common-mode EMI mitigation

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation, see the following: www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPSF12C1

Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics ADJ article
Texas Instruments, Designing High Performance, Low-EMI, Automotive Power Supplies application report
Texas Instruments, EMI Filter Components And Their Nonidealities For Automotive DC/DC Regulators technical brief

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this datasheet, refer to the left-hand navigation. TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPSF12C1

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPSF12C1DYYR SOT-23- www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPSF12C1

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSF12C1DYYR SOT-23-THIN DYY 14 3000 336.6 336.6 31.8 TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

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NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead ﬂash. Interlead ﬂash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/B 07/2021 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.31 0.11 0.1 C A B 1.1 MAX C SEATING PLANE 0.2

0.08 TYP

0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5 www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPSF12C1

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. EXAMPLE BOARD LAYOUT 4224643/B 07/2021 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 METAL SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK NON- SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS TPSF12C1 SNVSCB9 – MARCH 2023 www.ti.com ADVANCE INFORMATION

Product Folder Links: TPSF12C1

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have diﬀerent recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/B 07/2021 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8 www.ti.com TPSF12C1 SNVSCB9 – MARCH 2023 ADVANCE INFORMATION Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPSF12C1

www.ti.com 30-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples P12C1DYYR ACTIVE SOT-23-THIN DYY 14 3000 TBD Call TI Call TI -40 to 150 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPSF12C1 : Addendum-Page 1

www.ti.com 30-Mar-2023

Automotive : TPSF12C1-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side. 5. Reference JEDEC Registration MO-345, Variation AB PACKAGE OUTLINE 4224643/B 07/2021 www.ti.com SOT-23-THIN - 1.1 mm max height PLASTIC SMALL OUTLINE DYY0014A A 0.1 C B PIN 1 INDEX AREA 4.3 4.1 NOTE 3 2.1 1.9 3.36 3.16 14X 0.31 0.11 0.1 C A B 1.1 MAX C SEATING PLANE 0.2 0.1 0.0 0.25 GAUGE PLANE 0°- 8° 0.63 0.33 DETAIL A TYP 12X 0.5

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. EXAMPLE STENCIL DESIGN 4224643/B 07/2021 www.ti.com SOT-23-THIN - 1.1 mm max heightDYY0014A PLASTIC SMALL OUTLINE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 20X SYMM SYMM 14X (0.3) 14X (1.05) (3) 12X (0.5) (R0.05) TYP 7 8

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