TPS92075 TI | Alldatasheet

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A B Buck A B Buck-Boost EMI Filter TPS92075 www.ti.com SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 Non-Isolated,PhaseDimmable,BuckPFCLEDDriver withDigitalReferenceControl Check for Samples: TPS92075 1FEATURES DESCRIPTION The TPS92075 is a hybrid power factor controller• Controlled Reference Derived PFC (PFC) with a built-in phase dimming decoder. The• Integrated Digital Phase-Angle Decoder device analyzes line cycles continuously using an

  • Digital 50/60 Hz Synchronization internal, low-power, digital controller for shape and symmetry. The power converter stage generates an• Phase-Symmetry Balancing analog current reference and uses it to regulate the• Constant LED current operation output current. The device uses control algorithms to
  • Fast Start-up manipulate the analog reference. These algorithms optimize dimmer compatibility, power factor and total• Dimming Implemented Via Analog Reference harmonic distortion (THD).Control
  • Smooth Dimming Transitions Using a constant off-time control, the solution achieves low component count, high efficiency and• Overvoltage Protection inherently provides variation in the switching• Feedback Short-Circuit Protection frequency. This variation creates an emulated spread
  • Leading and Trailing Edge Dimmer spectrum effect easing the converters EMI signature Compatibility and allowing a smaller input filter.
  • Low BOM Cost and Small PCB Footprint The TPS92075 also includes standard features: current limit, overvoltage protection, thermal shut-• Patent Pending Digital Architecture down, and VCC undervoltage lockout, all in packages• Available in 8-Pin SOIC and 6-Pin TSOT utilizing only 6 pins.

APPLICATIONS

  • Bulb Replacement
  • Area Lighting
  • Dimmable and Non-Dimmable LED Lamps SIMPLIFIED APPLICATION DIAGRAM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2012–2014, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) ORDERABLE TRANSPORTTEMPERATURE RANGE (TJ) PACKAGE(2) PINS QUANTITYDEVICE NUMBER MEDIUM TPS92075D Rail 95 –40 to 125°C SOIC 8 TPS92075DR Tape and Reel 2500 TPS92075DDC Tape and Mini-Reel 1000 –40 to 125°C TSOT 6 TPS92075DDCR Tape and Reel 3000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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Product Folder Links: TPS92075

www.ti.com SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 ABSOLUTE MAXIMUM RATINGS(1) All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE UNIT MIN MAX Input voltage range VCC –0.3 22 V ASNS, COFF –0.3 6.0 Bias and ISNS IQ bias current (non-switching) 2.5 mA ISNS(2) to Ground –0.3 2.5 V Gate GATE - continuous –0.3 18 V GATE - 100 ns –2.5 20.5 V Continuous power dissipation Internally Limited Electrostatic discharge Human Body Model (HBM) 2 kV Field Induced Charged Device Model (FICDM) 750 V Operating junction temperature, TJ(3) 160 °C Storage temperature range, Tstg –65 150 °C Lead temperature, soldering, 10s 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) ISNS can sustain –2 V for 100 ns without damage. (3) Maximum junction temperature is internally limited. THERMAL INFORMATION TPS92075 SOIC TSOTTHERMAL METRIC(1) UNITS(D) (DDC)

8 PINS 6 PINS

θJA Junction-to-ambient thermal resistance(2) 112.3 165.5 θJCtop Junction-to-case (top) thermal resistance(3) 58.4 28.8 θJB Junction-to-board thermal resistance(4) 52.5 24.6 °C/W ψJT Junction-to-top characterization parameter(5) 12.5 0.3 ψJB Junction-to-board characterization parameter(6) 51.9 23.8 θJCbot Junction-to-case (bottom) thermal resistance(7) NA NA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS92075

SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com RECOMMENDED OPERATING CONDITIONS(1) Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C. MIN TYP MAX UNIT Supply input voltage range VCC 11 18 V Operating junction temperature –40 125 °C (1) Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics table.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified –40°C ≤ TJ = TA ≤ 125°C, VCC = 14 V, CVCC = 10 µF CGATE = 2.2 nF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE INPUT (VCC) IQ VCC quiescent current Not switching 1.3 2.5 mA IQ_SD VCC low power mode current VCC < VCC(UVLO) 120 250 µA VVCC Input range VCC ≤ VCC(OVP) 18 V VCC(OVP) Overvoltage protection threshold VCC > VCC(OVP) 18.0 20.0 V VCC rising 9.8 10.5 V VCC(UVLO) VCC UVLO threshold VCC falling 5.75 6.40 V VCC(HYS) VCC UVLO hysteresis 3.3 V ANGLE DEMODULATION ASNSTH-Hi Angle detect rising threshold 0.9 1.0 1.1 V ASNSTH-Low Angle detect falling threshold 0.465 0.500 0.540 V OFF-TIME CONTROL VCOFF OFF capacitor threshold 1.14 1.20 1.285 V RCOFF OFF capacitor pull-down resistance 33 60 Ω tOFF-max Maximum off-time 280 μs GATE DRIVER OUTPUT (GATE) RGATE(H) Gate sourcing resistance 3 8 Ω RGATE(L) Gate sinking resistance 3 8 Ω CURRENT SENSE VISNS Average ISNS limit threshold DAC: 63/127 445 500 555 mV VCL Current Limit 1.2 V Leading edge blanking 240 ns tISNS Current limit reset delay 280 µs ISNS limit to GATE delay 33 ns tCOFF_DLY OFF capacitor limit to GATE delay 33 ns THERMAL SHUTDOWN TSD Thermal limit threshold 160 °C THYS Thermal limit hysteresis 20 °C

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1.2 V Control

1.2 V 0V to 1V (Analog) UDG-12177 TPS92075 DAC TPS92075 www.ti.com SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS92075

SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com SOIC (D) PACKAGE

8 PINS

(TOP VIEW) TSOT (DDC) PACKAGE

6 PINS

(TOP VIEW) PIN DESCRIPTIONS PIN NUMBERS NAME SIOC TSOT I/O DESCRIPTION(D) (DDC) The phase of the TRIAC is detected through this pin and is then fed to the digital decoder.ASNS 8 1 I Sensing thresholds are 1V rising and 0.5V falling – nominal. Used to set the converter constant off-time. A current and capacitor connected from the outputCOFF 2 6 I to this pin sets the constant off-time of the switching controller. Power MOSFET driver pin. This output provides the gate drive for the power switchingGATE 4 4 O MOSFET. GND 1 2 — Circuit ground connection LED current sense pin. Connect a resistor from main switching MOSFET source to GND to setISNS 5 3 I the maximum switching cycle LED current. Connect ISNS to the switching FET source. Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. VCC undervoltage lockout has been implemented with a wide range: 10V rising, 6V falling toVCC 3 5 — ensure operation with start-up methods that allow elimination of the linear pass device. This includes using a coupled inductor with resistive start-up.

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/c27iL-PP (A) Peak Inductor Current iL UDG-12176 (constant) (B) COFF VCC GATE ASNS GND ISNS TPS92075 UDG-12180 A B Buck A B Buck-Boost C8 D2 Rectified AC Vcc TPS92075 SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com

APPLICATION INFORMATION

The TPS92075 is an AC-DC power factor correction (PFC) controller for phase-cut dimmer-compatible, LED lighting applications. A hysteretic, peak current, constant off-time approach implements the conversion. Figure 6. Simplified TPS92075 Schematic The cycle off-time. The following items summarize the basics of the switch operation in this hysteretic controller.

  • The main switch Q2 turns on and current ramps in the inductor.
  • The Q2 current flows through the sense resistor R7. The R7 voltage is compared to a reference voltage at ISNS. The Q2 on-time ends when the voltage on R7 is equal to a controlled reference voltage and the inductor current has reached its set peak current level for that switching cycle.
  • Q2 is turned off and a constant off-time timer begins. Voltage begins ramping on C8.
  • The next cycle begins when the voltage on C8 reaches 1.2 V. This ends the constant off-time and discharges C8.
  • Capacitor C3 eliminates most of the ripple current seen in the LEDs.

Figure 7. Current Regulation Method depending on the mode of operation. Each mode controls the peak current level using a different methodology.

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  • allows the use of inexpensive off-the-shelf inductors as the main magnetic
  • speeds start-up time under deep dimming conditions
  • can reduce the size of the required VCC capacitor
  • the extra current draw when dimming can improve dimming compatibility Another consideration when selecting a bias method involves the OVP configuration. Because the feature is enabled via the VCC pin, an auxiliary winding provides the simplest implementation of output over-voltage protection. A typical start-up sequence begins with VCC input voltage below the UVLO threshold and the device operating in low-power, shut-down mode. The VCC input voltage increases to the UVLO threshold of 9.8V typical. At this point all of the device features are enabled. The device loads the initial start-up value as the output reference and switching begins. The device operates until the VCC level falls below the VCC(UVLO) falling threshold. (6.4V typical) When VCC is below this threshold, the device enters low-power shut-down mode. Angle Sense Operation The ASNS (angle sense) pin is the only input to the digital controller. The time between the rising edge and the falling edge of the signal determines converter functions. The pin incorporates internal analog and digital filtering so that any transition that remains beyond the threshold for more than approximately 150 µs will cause the device to record a change-of-state.

Figure 8. Angle Sense Operation

  • Start-up
  • Non-Dimming
  • Dimming
  • ASNS signal lost With the exception of start-up, the controller can enter any of the states at any time as conditions demand. The two primary modes of controlling the converter reference are:
  • DC mode
  • Ramp mode During active dimming, a DC control reference increases or decreases depending on the input AC duty cycle derived from the ASNS signal. The relationship follows the algorithm: (ASNS Length + Fixed Offset) = Output Set point. When the conduction angle is long enough, the converter reference is changed to a triangular ramp to achieve a high power factor. The ramp is generated gradually over several cycles ensuring the implementation is undetectable. The controller maintains the ramp between the rising and falling ASNS signals. The controller also sets DC reference levels during start-up and when the ASNS signal is lost. Active states in the controller and controlled ranges are shown in Table 1.

Table 1. Control States and Controlled Reference Values 65Hz. After determining frequency and duty cycle, the controller enters the appropriate control state.

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Figure 11. Transition Stages of the Controlled Reference operation, the TPS92075 implements a translation that shifts output demand higher, lower in the dimming range. cycles. The amount of variation between each cycle varies greatly between dimmer brands, makes and models. and if there is a difference in TRIAC conduction angles, the result is a difference in light output for each cycle. between cycles that have a conduction angle difference greater than 20%. Figure 12. LED current variation, Constant Figure 13. LED current variation, TPS92075 with balancing feature the peaks in the LED current have been equalized and flicker cannot be seen (Figure 13).

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/c40 /c41 IN BULK L LED LED LED ripple PC 4 f R V I/c179 /c112 /c180 /c180 /c180 /c180 TPS92075 SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com Loss of Angle Sense When using a dimmer that can control the phase angle to very short conduction times (< 250 µs), the ASNS signal may become so narrow that the controller cannot determine its length. When this occurs the controller simply sets the reference to a default value 0.33V (42/127) and waits for the ASNS signal to return. A simplified version of the TPS92075 circuit can be implemented by grounding the ASNS signal if minimum component count and size are essential design criteria. In this configuration balancing, ramp mode and active hold are not implemented. The output is controlled with a default, static reference of 0.394V (50/127). If used in conjunction with an on-time clamp, good dimming and power factors (>0.9) can still be achieved. Thermal Shutdown The TPS92075 includes thermal shutdown protection. If the die temperature reaches approximately 160°C the device stops switching (GATE pin low). When the die temperature cools to approximately 140°C, the device resumes normal operation. If thermal fold back is desired at levels below the IC thermal shut down, application circuits have been created to implement this feature. The simplest of these is the addition of a thermistor in the off-time circuitry. Thermal Foldback To implement thermal foldback, adjust the resistance of an existing circuit resistor with the use of an NTC (negative temperature coefficient) thermistor. For example, a resistor combination creating a dominant effect when the thermistor reaches the desired temperature and resistance can be incorporated by paralleling a thermistor and another resistor with R10 (Figure 17). This circuit option creates a shorter on-time as the temperature increases, reducing the output current. The use of a thermistor in these types of circuit implementations is simple and saves costly added circuitry and additional device pins. Overvoltage Protection (OVP) The implementation of overvoltage protection is simple and built-in if using a two-coil magnetic (coupled inductor) to derive VCC. If the LED string is opened the auxiliary VCC rises and reaches the VCC(OVP) trip point. This action disables and grounds the gate pin, preventing the converter from switching. The converter remains disabled until VCC drops 0.5V after a 1 second time-out. If an inductor is used, implement other discrete circuits to disable the converter. Output Bulk Capacitor The required output bulk capacitor, CBULK, stores energy during the input voltage zero crossing interval and limits twice the line frequency ripple component flowing through the LEDs. Equation 1 describes the calculation of the of output capacitor value. where

  • RLED is the dynamic resistance of LED string
  • ILED(ripple) is the peak to peak LED ripple current
  • and fL is line frequency (1) RLED is found by computing the difference in LED forward voltage divided by the difference in LED current for a given LED using the manufacturer’s VF vs. IF curve. For a rough initial estimate a typical value of 0.25Ω per LED can be used. More detail can be found in Application Note 1656. In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve the desired operating lifetime. It should also be a consideration to provide a minimum load at the output of the driver to discharge the capacitor after the power is switched off or during LED open circuit failures.

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1 LED

2 V 3CF 1 90 2

assumes the use of an on-time clamp in the design. Figure 16. TPS92075 Output Current Control reference is a triangular waveform. TPS92075 Design Spreadsheet. To calculate RSENSE, use Equation 2. To calculate the conversion factor, use Equation 3. To calculate inductance ripple, use Equation 4.

To calculate the average switching frequency, use Equation 6. cycle. It also adds a means to control the energy in these conversion areas to optimize dimming performance. critical TRIAC regions, but is not high enough to excite circuit resonances. Figure 17. On-time Clamp Circuitry VCC, R10 (Rton(max)) is calculated in Equation 7.

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Figure 21. TPS92075 Application Circuit for Buck Topology with AC Side Filter Figure 22. TPS92075 Application Circuit for Buck-Boost Topology with DC Side Filter

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Figure 23. TPS92075 Application Circuit for Buck-Boost with Resistive Start-up and AUX Supply

SLUSB88B –DECEMBER 2012–REVISED JANUARY 2014 www.ti.com

REVISION HISTORY

Changes from Revision A (JANUARY 2013) to Revision B Page Changes from Original (DECEMBER 2012) to Revision A Page

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS92075D/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 T92075 TPS92075D/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 T92075 TPS92075DDC/NOPB Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DDC/NOPB.A Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DDCR/NOPB Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DDCR/NOPB.A Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 SN8B TPS92075DR/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 T92075 TPS92075DR/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 T92075 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS92075DDC/NOPB SOT-23- THIN TPS92075DDCR/NOPB SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92075DDC/NOPB SOT-23-THIN DDC 6 1000 208.0 191.0 35.0 TPS92075DDCR/NOPB SOT-23-THIN DDC 6 3000 208.0 191.0 35.0 TPS92075DR/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS92075D/NOPB D SOIC 8 95 495 8 4064 3.05 TPS92075D/NOPB.A D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 0.20

0.12 TYP

0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1

0.0 TYP

6X 0.5 0.3 0.6

0.3 TYP

1.9 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/E 08/2024 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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