TPS92074D.A

TPS92074 TI | Alldatasheet

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www.ti.com SLUSBO7 –AUGUST 2013 Non-Isolated,BuckPFCLEDDriverwithDigitalReferenceControl Check for Samples: TPS92074 1FEATURES DESCRIPTION The TPS92074 is a hybrid power factor controller• Controlled Reference Derived PFC (PFC) optimized for driving LED lighting solutions that• Digital 50/60 Hz Synchronization do not require phase dimming compatibility. The

• Constant LED current operation device monitors the converter rectified AC waveform using an internal, low-power, digital controller. The• Single Winding Magnetic Configurations controller and DAC generate a synchronized• Low Typical Operating Current triangular reference to regulate the output current. By
• Fast Start-up allowing for some variation in the LED current over a line cycle and maintaining a regulated overall average• Overvoltage Protection current, high power factor solutions can be achieved.• Feedback Short-Circuit Protection Using a constant off-time control, the solution• Wide Temperature Operation Range achieves low component count, high efficiency and• Low BOM Cost and Small PCB Footprint inherently provides variation in the switching
• Patent Pending Digital Architecture frequency. This variation creates an emulated spread spectrum effect easing the converters EMI signature• 8-Pin SOIC and 6-Pin TSOT Available and allowing a smaller input filter. APPLICATIONS The TPS92074 also includes standard features: current limit, overvoltage protection, thermal shut-• Non Phase Dimmable LED Lamps down, and VCC undervoltage lockout, all in packages• Bulb Replacement utilizing only 6 pins.
• Area Lighting SIMPLIFIED APPLICATION DIAGRAM Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SLUSBO7 –AUGUST 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS(1) All voltages are with respect to GND, –40°C < TJ = TA < 125°C, all currents are positive into and negative out of the specified terminal (unless otherwise noted) VALUE UNIT MIN MAX Input voltage range VCC –0.3 22 V VSEN, COFF –0.3 6.0 Bias and ISNS IQ bias current (non-switching) 2.5 mA ISNS(2) to Ground –0.3 2.5 V Gate GATE - continuous –0.3 18 V GATE - 100 ns –2.5 20.5 V Continuous power dissipation Internally Limited Electrostatic discharge Human Body Model (HBM) 2 kV Field Induced Charged Device Model (FICDM) 750 V Operating junction temperature, TJ (3) 160 °C Storage temperature range, Tstg –65 150 °C Lead temperature, soldering, 10s 260 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) ISNS can sustain –2 V for 100 ns without damage. (3) Maximum junction temperature is internally limited. THERMAL INFORMATION TPS92074 SOIC TSOTTHERMAL METRIC(1) UNITS(D) (DDC)

8 PINS 6 PINS

θJA Junction-to-ambient thermal resistance(2) 112.3 165.5 θJCtop Junction-to-case (top) thermal resistance(3) 58.4 28.8 θJB Junction-to-board thermal resistance(4) 52.5 24.6 °C/W ψJT Junction-to-top characterization parameter(5) 12.5 0.3 ψJB Junction-to-board characterization parameter(6) 51.9 23.8 θJCbot Junction-to-case (bottom) thermal resistance(7) NA NA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer

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Product Folder Links: TPS92074

www.ti.com SLUSBO7 –AUGUST 2013 RECOMMENDED OPERATING CONDITIONS(1) Unless otherwise noted, all voltages are with respect to GND, –40°C < TJ = TA < 125°C. MIN TYP MAX UNIT Supply input voltage range VCC 11 18 V Operating junction temperature –40 125 °C (1) Operating Ratings are conditions under which operation of the device is specified and do not imply assured performance limits. For specified performance limits and associated test conditions, see the Electrical Characteristics table.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified –40°C ≤ TJ = TA ≤ 125°C, VCC = 14 V, CVCC = 10 µF CGATE = 2.2 nF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE INPUT (VCC) IQ VVCC quiescent current Not switching 1.3 2.5 mA IQ_SD VVCC low power mode current VCC < VCC(UVLO) 120 250 µA VVCC Input range VCC ≤ VCC(OVP) 18 V VVCC(OVP) Overvoltage protection threshold VCC > VCC(OVP) 18.0 20.0 V VCC rising 9.8 10.5 V VVCC(UVLO) VVCC UVLO threshold VCC falling 5.75 6.40 V VVCC(HYS) VVCC UVLO hysteresis 3.3 V LINE SYNCHRONIZATION VSENTH-Hi VSEN line detect rising threshold 0.9 1.0 1.1 V VSENTH-Low VSEN line detect falling threshold 0.465 0.500 0.540 V OFF-TIME CONTROL VCOFF OFF capacitor threshold 1.14 1.20 1.285 V RCOFF OFF capacitor pull-down resistance 33 60 Ω tOFF(max) Maximum off-time 280 μs GATE DRIVER OUTPUT (GATE) RGATE(H) Gate sourcing resistance 3 8 Ω RGATE(L) Gate sinking resistance 3 8 Ω CURRENT SENSE VISNS Average ISNS limit threshold DAC: 63/127 445 500 555 mV VCL Current limit 1.2 V Leading edge blanking 240 ns tISNS Current limit reset delay 280 µs ISNS limit to GATE delay 33 ns tCOFF_DLY OFF capacitor limit to GATE delay 33 ns THERMAL SHUTDOWN TSD Thermal limit threshold 160 °C THYS Thermal limit hysteresis 20 °C Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS92074

1.2 V Control

1.2 V 0 -V to 1-V (Analog) TPS92074 TPS92074 SLUSBO7 –AUGUST 2013 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM

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Product Folder Links: TPS92074

www.ti.com SLUSBO7 –AUGUST 2013 SOIC (D) PACKAGE

8 PINS

(TOP VIEW) TSOT (DDC) PACKAGE

6 PINS

(TOP VIEW) PIN DESCRIPTIONS PIN NUMBERS NAME SIOC TSOT I/O DESCRIPTION(D) (DDC) Used to set the converter constant off-time. A current and capacitor connected from the outputCOFF 2 6 I to this pin sets the constant off-time of the switching controller. Power MOSFET driver pin. This output provides the gate drive for the power switchingGATE 4 4 O MOSFET. GND 1 2 — Circuit ground connection LED current sense pin. Connect a resistor from main switching MOSFET source to GND to setISNS 5 3 I the maximum switching cycle LED current. Connect ISNS to the switching FET source. Input voltage pin. This pin provides the power for the internal control circuitry and gate driver. VCC undervoltage lockout has been implemented with a wide range: 10V rising, 6V falling toVCC 3 5 — ensure operation with start-up methods that allow elimination of the linear pass device. This includes using a coupled inductor with resistive start-up. The line voltage and frequency are detected through this pin and fed to the digital decoder.VSEN 8 1 I Sensing thresholds are 1V rising and 0.5V falling – nominal. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS92074

Figure 1. COFF Threshold Voltage vs Temperature Figure 2. VCC Input Current vs Vcc Input Voltage Figure 3. Input Voltage (UVLO Rising) vs Junction Figure 4. Input Voltage (UVLO Falling) vs Junction Figure 5. ISNS 0.5V Threshold Distribution

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SLUSBO7 –AUGUST 2013 www.ti.com Initial Start-Up The TPS92074 is designed to achieve instant turn-on using an external linear regulator circuit. The start-up sequence is internally controlled by a VCC under-voltage lockout (UVLO) circuit. Sufficient headroom has been incorporated to support the use of an auxiliary winding with start-up linear, resistive or coupled capacitor start-up methods. VCC Bias Supply The TPS92074 can be configured to use a linear regulator with or without the use of an auxiliary winding. Using a linear regulator to provide VCC incurs more losses than an auxiliary winding, but has several advantages:

• allows the use of inexpensive off-the-shelf inductors as the main magnetic
• can reduce the size of the required VCC capacitor to as low as 0.1uF Another consideration when selecting a bias method involves the OVP configuration. Because the feature is enabled via the VCC pin, an auxiliary winding provides the simplest implementation of output over-voltage protection. A typical start-up sequence begins with VVCC input voltage below the UVLO threshold and the device operating in low-power, shut-down mode. The VVCC input voltage increases to the UVLO threshold of 9.8V typical. At this point all of the device features are enabled. The device loads the initial start-up value as the output reference and switching begins. The device operates until the VVCC level falls below the VCC(UVLO) falling threshold. (6.4V typical) When VVCC is below this threshold, the device enters low-power shut-down mode. Voltage Sense Operation The VSEN (voltage sense) pin is the only input to the digital controller. The time between the rising edge and the falling edge of the signal determines converter functions. The pin incorporates internal analog and digital filtering so that any transition that remains beyond the threshold for more than approximately 150 µs will cause the device to record a change-of-state.

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Product Folder Links: TPS92074

• Start-Up
• Normal Operation After the initial start-up period where the reference is a DC level, the reference is changed to a triangular ramp to achieve a high power factor. The ramp generates gradually over several cycles ensuring the change is undetectable. The controller maintains the ramp between the rising and falling VSEN signals.

Table 1. Control States and Controlled Reference Values Hz. After determining frequency and duty cycle, the controller enters normal operation. Figure 8. Line Synchronization between rising and falling edges of the VSEN signal as shown in Figure 9.

Figure 9. Controlled Reference Output a method that further ensures transparency to the user. Figure 10. Transition Stages of the Controlled Reference during Start-Up THD is higher without the ramp waveform. (negative temperature coefficient) thermistor.

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/c40 /c41 IN BULK L LED LED LED ripple PC 4 f R V I/c179 /c112 /c180 /c180 /c180 /c180 TPS92074 www.ti.com SLUSBO7 –AUGUST 2013 For example, a resistor combination creating a dominant effect when the thermistor reaches the desired temperature and resistance can be incorporated by paralleling a thermistor and another resistor like R10 with the suggested On-Time clamp (see Figure 12. ). This circuit option creates a shorter on-time as the temperature increases, reducing the output current. The use of a thermistor (NTC or PTC) in these types of circuit implementations is simple and saves costly added circuitry and additional device pins. Overvoltage Protection (OVP) The implementation of overvoltage protection is simple and built-in if using a two-coil magnetic (coupled inductor) to derive VCC. If the LED string is opened the auxiliary VCC rises and reaches the VCC(OVP) trip point. This action disables and grounds the gate pin, preventing the converter from switching. The converter remains disabled until VCC drops 0.5 V after a 1 second time-out. If an inductor is used, implement other discrete circuits to disable the converter. Output Bulk Capacitor The required output bulk capacitor, CBULK, stores energy during the input voltage zero crossing interval and limits twice the line frequency ripple component flowing through the LEDs. Equation 1 describes the calculation of the of output capacitor value. where

• RLED is the dynamic resistance of LED string
• ILED(ripple) is the peak to peak LED ripple current
• and fL is line frequency (1) Compute RLED as the difference in LED forward voltage divided by the difference in LED current for a given LED using the manufacturer’s VF vs. IF curve. For an initial estimate, a typical value of 0.25 Ω per LED can be used. More detail can be found in the Application Report Design Challenges of Switching LED Drivers (AN-1656). In typical applications, the solution size becomes a limiting factor and dictates the maximum dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating factors should be applied based on the worst case capacitor ripple current, output voltage and operating temperature to achieve the desired operating lifetime. It should also be a consideration to provide a minimum load at the output of the driver to discharge the capacitor after the power is switched off or during LED open circuit failures. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS92074

1 LED

2 V 3CF 1 90 2

sensing. Output inductor, sense resistor and switching frequency are the key aspects of the power stage design. the use of an on-time clamp in the design. Figure 11. TPS92074 Output Current Control through Equation 6. For a more comprehensive approach refer to the TPS92074 Design Spreadsheet. To calculate RSENSE, use Equation 2. To calculate the conversion factor, use Equation 3. To calculate inductance ripple, use Equation 4.

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To calculate the average switching frequency, use Equation 6. used so that the circuit has the capability to draw current from the line below the LED stack voltage. must use the on-time clamp to obtain very low THD. Figure 12. On-time Clamp Circuitry In the regions at the start and end of a line cycle the current sense reference is controlled to 0.173 V (22/127). capacitor C10, and assuming VGATE ≈ VCC, R10 (Rton(max)) is calculated in Equation 7.

conduction time may not be adequate to ensure use of the ramp reference by the controller. Figure 13. Voltage Sense for Low Figure 14. Voltage Sense for Figure 15. Voltage Sense for applications, implement the circuit shown in Figure 15. A capacitor on the VSEN pin may be required, depending on operating conditions.

• the use of ‘X’versus non-X rated filter capacitors
• the use of ceramic versus film capacitors
• component rating requirements when on the AC or DC side of the diode bridge
• snubber time constant and position in the design schematic
• filter design choices and audible noise

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Figure 18. TPS92074 Buck-Boost Topology with Resistive Start-up and AUX Supply Figure 19. TPS92074 Buck Topology with Thermal Foldback and Analog Dimming (0 to 100%)

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS92074D Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 T92074 TPS92074D.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 T92074 TPS92074DDCR Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DDCR.A Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DDCT Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DDCT.A Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PC5Q TPS92074DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 T92074 TPS92074DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 T92074 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS92074DDCR SOT-23- THIN TPS92074DDCT SOT-23- THIN Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92074DDCR SOT-23-THIN DDC 6 3000 208.0 191.0 35.0 TPS92074DDCT SOT-23-THIN DDC 6 250 208.0 191.0 35.0 TPS92074DR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS92074D D SOIC 8 95 495 8 4064 3.05 TPS92074D.A D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com PACKAGE OUTLINE C 0.20

0.12 TYP

0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1

0.0 TYP

6X 0.5 0.3 0.6

0.3 TYP

1.9 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/E 08/2024 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4

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