TPS92001 TI | Alldatasheet
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TPS92001,TPS92002 www.ti.com SLUSA24 –FEBRUARY 2010 GENERALPURPOSELEDLIGHTINGPWM CONTROLLER Check forSamples: TPS92001 ,TPS92002 1FEATURES DESCRIPTION
- IdealforSingleStage Designs The TPS92001/2 familyofgeneralLED lightingPWM controllerscontains control and drive circuitry• Supports Isolatedand Non-Isolated requiredfor off-lineisolatedor non-isolatedLEDTopologies lightingapplications.• Phase-Cut TRIAC Dimmable The controllerscan support Phase Cut TRIAC• Few ExternalComponents Mode Operation dimming with minimal externalcomponents. The• Wide Duty Cycle Range forWide-InputVoltage controllerscan also be implemented for stageor Dimming Range conversionwhere the power factor(PF) exceeds
- Convenient 5-V ReferenceOutput regulatoryrequirementsforlighting.These controllers alsohave an accessible5-V referencethatcouldbe• UndervoltageLockout forSafe Operation used to power a microcontrolleror otherlow power• Operationto1-MHz peripheralcomponents. The controllersoperate in
- 0.4-ASource/0.8-ASink FET Driver fixedfrequencycurrentmode switchingwithminimal externalpartscount.Internallyimplementedcircuits• Low 100-µA StartupCurrent includeundervoltagelockoutfeaturingstartupcurrent lessthan100 µA, logictoensurelatchedoperation,aAPPLICATIONS PWM comparator,and a totem poleoutputstageto• ResidentialLED LightingDriversforA19 sink or source peak current.The output stage,E12/E26/27,GU10, MR16, PAR30/38 Integral suitablefordrivingN-Channel MOSFETs, is low inLamps theoffstate.Oscillatorfrequencyand maximum duty
- DriversforWallSconces, Pathway Lighting cycle are programmed with two resistorsand a and Overhead Lighting capacitor.
- DriversforWallWashing, Architecturaland The TPS92001/2 familyalsofeaturesfullcyclesoftDisplayLighting start.The family offers UVLO thresholdsand hysteresislevelsforoff-lineand DC-to-DC systems.DEVICE TURN-ON TURN-OFF The TPS92001/2 isofferedinthe8-pinMSOP (DGK)NUMBER THRESHOLD (V) THRESHOLD (V) and 8-pinSOIC (D) packages. The small MSOPTPS92001 10 package makes the device ideallysuited for8 TPS92002 15 applicationswhere board space and heightare at a premium Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
TPS92001,TPS92002 SLUSA24 –FEBRUARY 2010 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerangeunlessotherwisenoted(1) RANGE UNIT VDD 19 Inputvoltagerange SS -0.3toREF + 0.3 V RTC, RTD -0.3toREF + 0.3 IREF -15 Continuousinputcurrent mA IVDD 25 Outputcurrent IGD (tpw< 1 µs and DutyCycle< 10%) -0.4to0.8 A Operatingjunctiontemperature TJ −55 to+150 °C Storagetemperature Tstg −65 to+150 Lead temperature Soldering,10 s +300 (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.Allvoltages arewithrespecttoGND. Currentsarepositiveinto,negativeoutofthespecifiedterminal. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VDD Inputvoltage 21 V IGD Outputsinkcurrent 0 A TJ Operatingjunctiontemperature –40 105 °C DISSIPATION RATINGS qJA ,THERMAL qJB ,THERMAL TA = 25°C TA = 85°C TB = 85°CIMPEDANCE IMPEDANCEPACKAGE POWER POWER POWERJUNCTION-TO-AMBIENT, JUNCTION-TO-BOARD, RATING (mW) RATING (mW) RATING (mW)NO AIRFLOW (°C/W) NO AIRFLOW (°C/W) (1) TestedperJEDEC EIA/JESD51-1.Thermalresistanceisa functionofboardconstructionand layout.Airflowwillreducethermal resistance.Thisnumber isincludedonlyas a generalguideline;see TIdocument SPRA953 IC Package ThermalMetrics. (2) Maximum junctiontemperatureTJ,equalto125°C. (3) Thermalresistancetothecircuitboardislower.Measured withstandardsingle-sidedPCB construction.Board temperature,TB, measured approximately1 cm fromtheleadtoboardinterface.Thisnumber isprovidedonlyas a generalguideline. ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX UNIT Human body model 2000 V CDM 1500
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TPS92001,TPS92002 www.ti.com SLUSA24 –FEBRUARY 2010
ELECTRICAL CHARACTERISTICS
VVDD = 12 V,C REF = 0.47-mF,TA = TJ (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY SECTION VDD Supplyclamp IVDD = 10 mA 16 17.5 19 V IVDD Supplycurrent No Load 600 900 µA IVDD Supplycurrentstartup(1) 110 µA TPS92001 110 125 Supplycurrentstandby VVDD = Startthreshold– 300 mv µA TPS92002 130 170 UNDERVOLTAGE LOCKOUT SECTION TPS92001 9.4 10.4 Startthreshold TPS92002 14.0 15.6 V TPS92001 1.65 UVLO hysteresis TPS92002 6.2 VOLTAGE REFERENCE SECTION Outputvoltage IREF = 0 mA 4.75 5 5.25 V Lineregulation 10 V ≤ VVDD ≤ 15 V 2 mV Load regulation 0 mA ≤ IREF ≤ 5 mA 2 mV COMPARATOR SECTION ICS Currentsense OutputOFF -100 nA Comparatorthreshold 0.9 0.95 1 V GD DLY GD propagationdelay(No Load) 0.8V ≤ VCS ≤ 1.2V atTR = 10 ns 50 100 ns SOFT START SECTION VVDD = 16 V,VSS = 0 V,-40°C ≤ TA ≤ 85°C -4.9 -7.0 -9.1 µA ISS Soft-startcurrent VSS Low-leveloutputvoltage VVDD = 7.5V,ISS = 200 µA 0.2 V Shutdown threshold 0.44 0.48 0.52 V OSCILLATOR SECTION R RTC = 10 kΩ,R RTD = 4.32kΩ,C CT =Switchingfrequency 90 100 110 kHz820pF Frequencychange withvoltage 10 V ≤ VVDD ≤ 15 V 0.1 %/V VCT(peak) Timingcapacitorpeak voltage 3.33 V VCT(valley) Timingcapacitorvalleyvoltage 1.67 V VCT(p-p) Timingcapacitorpeak-to-peakvoltage 1.54 1.67 1.80 V GATE DRIVE SECTION Power driverVSAT low IGD = 80 mA (dc) 0.8 1.5 V Power driverVSAT high IGD = -40mA (dc),(VVDD – VGD ) 0.8 1.5 V Power driverlow-voltageduringUVLO IGD = 20 mA (dc) 1.5 V D MIN Minimum dutycycle VCS = 2 V 0% D MAX Maximum dutycycle 70% tRISE RiseTime C GD = 1nF 35 ns tFALL FallTime C GD = 1nF 18 ns (1) Specifiedby design.Not productiontested. Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPS92001 TPS92002
0.5 V + 5 V 5 V REF OSC S Q R PWM Latch 15/8 V 10/8 V CLK 17.5 V TPS92001,TPS92002 SLUSA24 –FEBRUARY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM
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DGK□Package (Top□View) CS SS RTC RTD REF VDD GD GND D□Package (Top□View) /c40 /c41RISE CT RTCt 0.74 C 27 pF R/c61 /c180 /c43 /c180 /c40 /c41FALL CT RTDt 0.74 C 27 pF R/c61 /c180 /c43 /c180 TPS92001,TPS92002 www.ti.com SLUSA24 –FEBRUARY 2010
ORDERING INFORMATION
THRESHOLDOPERATING ORDERABLE TRANSPORTTEMPERATURE PACKAGE DEVICE PINS QUANTITYTURN- TURN- MEDIARANGE TA NUMBERON OFF TPS92001DGK Tube 80 PlasticSmallOutline(MSOP) TPS92001DGKR Tape and Reel 2500 TPS92001D Tube 75 PlasticSmallOutline(SOIC) TPS92001DR Tape and Reel 2500 –40°C to85°C 8 8 TPS92002DGK Tube 80 PlasticSmallOutline(MSOP) TPS92002DGKR Tape and Reel 2500 TPS92002D Tube 75 PlasticSmallOutline(SOIC) TPS92002DR Tape and Reel 2500 DEVICE INFORMATION TPS92001/2 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. Thispinisthesumming node forcurrentsense feedback,voltagesense feedback(byoptocoupler)and slope compensation.Slopecompensationisderivedfromtherisingvoltageatthetimingcapacitorand can be buffered withan externalsmallsignalNPN transistor.Externalhighfrequencyfiltercapacitanceappliedfromthisnode toCS 1 I GND isdischargedby an internal250ohm on resistanceNMOS FET duringPWM offtime.Itofferseffective leadingedge blanking,withthedelaysetby theRC timeconstantofthefeedbackresistancefromcurrentsense resistortoCS inputand thehighfrequencyfiltercapacitoratthisnode toGND. GND 5 – Referencegroundand power groundforallfunctions. Thispinisthehighcurrentpower driveroutput.A minimum seriesgateresistorof3.9Ω isrecommended tolimitGD 6 O thegatedrivecurrentwhen operatingwithhigh-biasvoltages. The internal5-V referenceoutput.Thisreferenceisbufferedand isavailableon theREF pin.The REF pinshouldREF 8 O be bypassedwitha 0.47-µF ceramiccapacitortoGND. ThispinconnectstotimingresistorR RTC ,and controlsthepositiveramp (rise)timeoftheinternaloscillator(see Equation1).The positivethresholdoftheinternaloscillatorissensed throughinactivetimingresistorR RTD which connectstopinRTD and timingcapacitor,C CT .RTC 3 I (1) ThispinconnectstotimingresistorRTD and controlsthenegativeramp (fall)timeoftheinternaloscillator(see Equation2).The negativethresholdoftheinternaloscillatorissensed throughinactivetimingresistorR RTC which connectstopinRTC and timingcapacitor,C CT .RTD 4 I (2) Thispinservestwo functions.The softstarttimingcapacitorconnectstoSS and ischargedby an internal6-µA currentsource.Under normalsoft-start,theSS pinisdischargedtoatleast0.4V and thenramps positiveto1 V SS 2 I duringwhichtimetheoutputdriverisheldlow.As theSS pinchargesfrom1 V to2 V,thesoft-startis implementedby an increasingoutputdutycycle.IftheSS pinistakenbelow0.5V,theoutputdriverisinhibited and heldlow.The useraccessible5-V voltagereferencealsogoes lowand IVDD = 100 µA The power inputconnectionforthisdevice.Thispinisshuntregulatedat17.5V whichissufficientlybelowtheVDD 7 I voltageratingoftheDMOS outputdriverstage.VDD shouldbe bypassedwitha 1-µF ceramiccapacitor. Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPS92001 TPS92002
/c40 /c41 /c40 /c41/c40 /c41 /c45 /c61 /c180 /c43 /c180 /c43 OSC CT RTC RTDf 0.74 C 27 pF R R /c40 /c41/c61 /c180 /c180 /c43 /c180MAX TC T OSCD 0.74 R C 27 pF f S Q R RRTD CCT RRTC VREF 3.33 V 1.67 V CLK Oscillator Oscillator Latch UDG-10005 RTC RTD TPS92001,TPS92002 SLUSA24 –FEBRUARY 2010 www.ti.com
APPLICATION INFORMATION
The typicalapplicationdiagramsinFigure3 and Figure4 show isolatedand non-isolatedflybackconverters utilizingtheTPS92001. Note thatthecapacitorsC REF and C VDD arelocaldecouplingcapacitorsforthereference and deviceinputvoltage,respectively.Both capacitorsshouldbe low ESR and ESL ceramic,placedas closeas possibletothedevicepins,and returneddirectlytotheground pinofthedeviceforbeststability.The REF pin providestheinternalbiastomany ofthedevicefunctionsand C REF shouldbe atleast0.47-µF topreventthe REF voltagefromdrooping. CurrentSense (CS)Pin IntheTPS92001/2,thecurrentregulationisobtainedthroughthesummation oftheprimarycurrentsense and any slopecompensationat the CS pincompared to a 1-V threshold,as shown inthe FUNCTIONAL BLOCK DIAGRAM . Crossingthis1-V thresholdresetsthe PWM latchand modulatesthe outputdriveron-time.In the absence of a CS signal,the outputobeys the programmed maximum on-timeof the oscillator.When adding slope compensation,itis importantto use a smallcapacitorto AC couple the oscillatorwaveform before summing thissignalintothe CS pin.By forcingthe CS node to exceed the 1-V thresholdthe TPS92001/2 is forcedtozeropercentdutycycle. Oscillator Equation3 calculatestheoscillatorfrequencysetting. (3) (4) ReferringtoFigure1 and thewaveformsinFigure2,when Q1 ison,C CT chargesviatheon-resistanceoftheQ1 MOSFET and theRTC pin.Duringthischargingprocess,thevoltageofC CT issensed throughtheRTD pin.The S inputoftheoscillatorlatch,SOSC ,islevelsensitive,so crossingtheupperthreshold(setat2/3VREF or3.33V fora typical5.0V reference)setstheQ output(CLK signal)oftheoscillatorlatchhigh.A highCLK signalresults inturningoffQ1 and turningon Q2. The timingcapacitorthendischargesthroughRTD and theR DS(on) ofQ2. C CT dischargesfrom3.33V tothelowerthreshold(setat1/3REF or1.67V fora typical5.0-Vreference)sensed throughRTC. The R inputtotheoscillatorlatch,R OSC ,isalsolevelsensitiveand resetstheCLK signallow when C CT crossesthe1.67-Vthreshold,turningoffQ2 and turningon Q1, initiatinganotherchargingcycle. Figure1. OscillatorFunction
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QOSC=CLK=SPWM CS RPWM QPWM VGD CCT Charging C CT Discharging 3.33 V 1.67 V 1 V 70% ON 30% OFF CS Signal Dominant Maximum Duty Cycle Dominant ROSC UDG-10006 TPS92001,TPS92002 www.ti.com SLUSA24 –FEBRUARY 2010 Figure2. OscillatorLatch and PWM Latch Waveforms Figure2 shows the waveforms associatedwiththe oscillatorlatchand the PWM latch(shown inthe Typical ApplicationDiagram).A highCLK signalnotonlyinitiatesa dischargecycleforC CT ,italsoturnson theinternal N-channelMOSFET on theCS pincausingany externalcapacitanceused forleadingedge blankingconnected to thispinto be dischargedto ground.By dischargingany externalcapacitorcompletelyto ground duringthe externalswitchoff-time,thenoiseimmunityoftheconverterisenhanced allowingtheusertodesigninsmaller R-C components forleadingedge blanking.A highCLK signalalsosetsthelevelsensitiveS inputofthePWM latch,SPWM ,high,resultingina highoutput,Q PWM ,as shown inFigure2.ThisQ PWM signalremainshighuntila resetsignal,R PWM isreceived.A highR PWM signalresultsfrom the CS signalcrossingthe 1-V threshold,or duringsoft-startoriftheSS pinisdisabled. Assuming theUVLO thresholdissatisfied,theGD signalofthedeviceremainshighas longas Q PWM ishighand SPWM ,alsoreferredtoas CLK, islow.The GD signalisdominatedby theCS signalas longas theCS signal tripsthe1-V thresholdwhileCLK islow.IftheCS signaldoes notcrossthe1-V thresholdwhileCLK islow,the GD signalwillbe dominatedby themaximum dutycycleprogrammed by theuser.Figure2 illustratesthevarious waveformsfora designsetup fora maximum dutycycleof70%. The recommended valueforC CT is1 nF forfrequenciesinthe100 kHz orlessrangeand smallerC CT forhigher frequencies.The minimum recommended valuesofR RTC is10 kΩ.The minimum recommended valueofR RTD is 4.32kΩ.Using thesevaluesmaintainsa ratioofatleast20:1between theR DS(on) oftheinternalFETs and the externaltimingresistors,resultinginminimalchange infrequencyover temperature.Because of the oscillator susceptibilityto capacitivecoupling,examine the oscillatorfrequencyby lookingat the common RTC-RTD-CT node on thecircuitboardas opposed tolookingatpins3 and 4 directly.For good noiseimmunity,theRTC and RTD resistorsshouldbe placedas closetopins3 and 4 ofthedeviceas possible.The timingcapacitorshould be returneddirectlytothegroundpinofthedevicewithminimalstrayinductanceand capacitance. Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPS92001 TPS92002
TPS92001,TPS92002 SLUSA24 –FEBRUARY 2010 www.ti.com Figure3. IsolatedFlybackwithTRIAC Dimming Interface CAUTION Do notoperatetheIsolatedFlybackdescribedinFigure3 withoutload.
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TPS92001,TPS92002 www.ti.com SLUSA24 –FEBRUARY 2010 Figure4. Non-IsolatedFlybackwithTRIAC Dimming Interface Copyright© 2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPS92001 TPS92002
TJ – Junction Temperature – °C –50 –25 0 25 50 75 100 125 VUVLO – Undervoltage Lockout Threshold – V TPS92001 UVLO On TPS92002 UVLO On UVLO Off 180IVDD – Standby Current – /c109A –50 –25 0 25 50 75 100 125 120 100 160 140 TPS92001 TPS92002 TJ – Junction Temperature – °C 1000 100 CCT – Timing Capacitance – pF 100 1000 10000 RRTC = 10 k/c87 RRTD = 4.32 k/c87 fOSC – Oscillator Frequency – kHz 105 110fOSC – Oscillator Frequency – kHz 100 –50 –25 0 25 50 75 100 125 TJ – Junction Temperature – °C TPS92001,TPS92002 SLUSA24 –FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS VDD STANDBY CURRENT UNDERVOLTAGE LOCKOUT THRESHOLD vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure5. Figure6. OSCILLATOR FREQUENCY OVERVOLTAGE PROTECTION THRESHOLD vs vs JUNCTION TEMPERATURE TEMPERATURE Figure7. Figure8.
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Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS92001D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS92001DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS92001DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS92001DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS92002D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS92002DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS92002DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS92002DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 15-Mar-2010 Addendum-Page 1
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