TPS9103 TI | Alldatasheet
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POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Charge Pump Provides Negative Gate Bias for Depletion-Mode GaAs Power Amplifiers /C0068Buffered Clock Output to Drive Additional External Charge Pump /C0068135-mΩ High-Side Switch Controls Supply Voltage to the GaAs Power Amplifier /C0068Power-Good Circuitry Prevents High-Side Switch Turn-on Until Negative Gate Bias is Present /C0068Charge Pump Can Be Driven From the Internal Oscillator or An External Clock /C006810-µA Maximum Standby Current /C0068Low-Profile (1.2-mm Max Height), 20-Pin
description
The TPS9103 is a highly integrated power supply for depletion-mode GaAs power amplifiers (PA) in cellular handsets and other wireless communications equipment. Functional integration and low-profile packaging combine to minimize circuit-board area and component height requirements. The device includes: a p-channel MOSFET configured as a high-side switch to control the application of power to the PA; a driver for the high-side switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent turn-on of the high-side switch until gate bias is present. The high-side switch has a typical on-state resistance of 135 mΩ . The TPS9103 is available in a 20-pin thin shrink small-outline package (TSSOP) or in chip form. Contact factory for die sales. The device operates over a junction temperature range of –25°C to 125°C. AVAILABLE OPTIONS PACKAGED DEVICE CHIP FORMTA TSS0P (PW) CHIP FORM (Y) –25°C to 85°C TPS9103PWLE TPS9103Y The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GATE_BIAS VCC C1– C1+ BATT_IN BATT_IN BATT_IN PGP PG GND VDD CLK BCLK GND BATT_OUT BATT_OUT BATT_OUT SW_EN OSC_EN EN PW PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1996, Texas Instruments Incorporated
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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0.6R 5, 6, 7 10, 17 14, 15, 16 BATT_OUT SW_EN PG CLK GATE_BIAS BATT_IN VCC BCLK VDD EN OSC_EN PGP C1+ C1– GND Vref UVLO UVDLO VCC PG ComparatorR
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS9103Y chip information This chip, when properly assembled, displays characteristics similar to the TPS9103. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. Contact factory for die sales. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ± 10%. ALL DIMENSIONS ARE IN MILS. 116 (6)(7) TPS9103Y C1+ C1– BATT_IN PGP EN OSC_EN SW_EN CLK GATE_BIAS BATT_OUT BCLK PG VCC VDD 202 GND 10, 17 14, 15, 16 5, 6, 7 (4) (5) (6) (7) (17) (16) (15) (14)
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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NAME NO. GATE_BIAS 1 Negative gate-bias output voltage VCC 2 Logic supply voltage C1– 3 External capacitor connection (inverting charge pump) C1+ 4 External capacitor connection (inverting charge pump) BATT_IN 5 High-side switch input voltage BATT_IN 6 High-side switch input voltage BATT_IN 7 High-side switch input voltage PGP 8 Program input for power-good threshold PG 9 Power-good output GND 10 Ground EN 11 Chip-enable input OSC_EN 12 Oscillator-enable input SW_EN 13 High-side switch enable input BATT_OUT 14 High-side switch output voltage BATT_OUT 15 High-side switch output voltage BATT_OUT 16 High-side switch output voltage GND 17 Ground BCLK 18 Buffered clock output CLK 19 Clock (bidirectional) VDD 20 Charge-pump supply voltage
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description high-side switch and driver (BATT_IN, BATT_OUT, SW_EN) The high-side switch is a p-channel MOSFET with a maximum on-state resistance of 180 mΩ (VI(BATT_IN) = 6 V and VCC = 3.3 V). The driver pulls the gate of the high-side switch to GATE_BIAS instead of ground to reduce the MOSFET on-state resistance. Gate breakdown considerations limit the voltage between BATT_IN and GATE_BIAS to 15 V. Extremely fast switching times are not required in this application, and the high-side switch/driver is designed to provide 2 µs maximum switching times with minimum power consumption. The GaAs depletion-mode MOSFETs in the PA are protected from damage at power-up by internal logic that inhibits the driver until negative gate bias is available. The control input SW_EN is compatible with 3-V and 5-V CMOS logic; a logic-high input turns the high-side switch on. oscillator (OSC_EN , CLK) The internal oscillator drives the charge pump at 50 kHz with a nominal duty cycle of 50% when both the EN and OSC_EN inputs are logic lows. CLK outputs the internal oscillator signal (no buffer). A logic-high input to OSC_EN disables the internal oscillator and allows the charge pump to operate from an external clock connected to CLK. When an external clock with negative overshoot is applied, a Schottky diode must be added to limit the amplitude of the overshoot. charge pump (GATE_BIAS, C1+, C1–) The inverting charge pump generates the negative gate-bias voltage output at GATE_BIAS. chip enable (EN A logic high on EN shuts down the internal functions of the TPS9103 and turns the bias system off, reducing the supply current to less than 10 µA. A low input on EN causes normal operation to resume. power good (PG, PGP) PG output is logic high when GATE_BIAS is in regulation. PG output is logic low when GATE_BIAS is not in regulation. The high-side switch is disabled and PG is forced to logic low whenever the magnitude of GATE_BIAS is less than 0.6 × V DD . A modified threshold for the power-good function can be achieved by programming PGP with an external resistor. undervoltage lockout for VCC and VDD (UVLO and UVDLO) Undervoltage lockout prevents operation at supply voltages too low for proper operation. When UVLO or UVDLO is active, all power-switch drives are forced to the off state and bias is removed from unneeded functions. Hysteresis is provided to minimize cycling on and off because of source impedance loading when the supply voltage is close to the threshold. buffered clock output (BCLK) The buffered clock output is a driver for an external charge pump. When the optional external charge pump is not needed, BCLK should be left unconnected. For more details, see the application section. supply input for inverting charge pump (V DD ) VDD is the supply voltage for the inverting charge pump. In normal operation, VDD is connected to VCC . If the negative gate-bias needs to be larger than VCC (i.e., more negative), then a higher voltage supply needs to be connected to VDD . This can be supplied from an external charge pump driven from BCLK.
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mounted on an FR4 board with no special thermal considerations. Figure 1. Dissipation vs Free-Air Temperature implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to device GND.
- Differential voltage calculated: |VImax| + |GATE_BIAS|
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN NOM MAX UNIT Input voltage, BATT_IN 3 9 V Supply voltage, VCC, VDD 2.7 5.5 V Output voltage, GATE_BIAS, VO –2 –5 V Continuous output current, GATE_BIAS 0 10 mA Continuous output current, BATT_OUT 0 2 A Charge-pump capacitor value at C1+/C1– 0.33 µF External clock frequency, CLK 25 75 kHz High-level input voltage, VIH 2 V Low-level input voltage, VIL SW_EN, EN, OSC_EN, CLK 0.8 V Input current, II –1 1 µA Operating junction temperature, TJ –25 125 °C electrical characteristics over recommended operating junction temperature range, BATT_IN = 6 V, VCC = VDD = 3.3 V, IO(BATT_OUT) = 0.5 A, IO(GATE_BIAS) = 2 mA, EN = OSC_EN = 0 V, SW_EN = VCC , C1 = 0.33 µF (unless otherwise noted) charge pump PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage –3 –3.10 –3.3 V Output resistance 95 Ω high-side switch PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C 135 180 Dran to source on state resistance TA = –25°C to 85°C 210 m ΩD ran-to-source on-state resistance TA = 25°C, VI(BATT_IN) = 3 V 160 220 m Ω TA = –25°C to 85°C, BATT_IN = 3 V 260 Leakage current TA = 25°C, VI(BATT_IN) = 9 V, SW_EN = 0 V 1 µALeakage current TA = 85°C, VI(BATT_IN) = 9 V, SW_EN = 0 V 10 µA Delay to high-level output SW_EN from 0 to VCC 0.2 2 µs Delay to low-level output SW_EN from VCC to 0 0.9 2 µs oscillator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency VCC = 2.7 V to 5.5 V 35 50 60 kHz Duty cycle VCC = 2.7 V to 5.5 V 40% 50% 60% buffered clock output (BCLK) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output resistance 10 Ω High-level output voltage I(BCLK) = 30 mA VCC –0.3 V Low-level output voltage I(BCLK) = 30 mA 0.3 V
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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power good (PG) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Threshold voltage VDD = 2.7 V to 5.5 V 0.60 × VDD V On-state voltage IO(PG) = 500 µA, VCC = 2.7 V to 5.5 V 0.3 V Off-state voltage IO(PG) = –500 µA, VCC = 2.7 V to 5.5 VVCC –0.3 V Hysteresis 130 mV power good (PGP) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input impedance 85 kΩ undervoltage lockout (UVLO + UVDLO) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start threshold voltage VCC increasing 2.4 2.7 V Hysteresis 130 mV supply current (ICC and IDD ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standby mode EN = VCC 1 10 µA Undervoltage lockout VCC = VDD < 2.3 V 35 50 µA Operating mode No load 300 500 µA
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Figure 4. Ripple on GATE_BIAS
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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2.5 3 3.5 4 OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE 4.5 5 5.5 VCC – Supply Voltage – V – Oscillator Frequency – kHzfosc IO – Output Current – mA – 3 – 4 – 5 – 6 0123456 – Output Voltage – V – 2 – 1 GATE BIAS OUTPUT VOLTAGE vs OUTPUT CURRENT 789 1 0 VO VCC = 2.7 V VCC = 3.3 V VCC = 5 V Figure 8 T – Temperature – °C 47.5 – 50 – 25 0 25 50 48.5 OSCILLATOR FREQUENCY vs TEMPERATURE 49.5 75 100 125 3.3 V 2.7 V 5 V – Oscillator Frequency – kHzfosc Figure 10 – 3.15 – 3.2 – 3.25 – 3.3 25 30 35 40 45 50 55 – Output Voltage – V – 3.1 – 3.05 f – CLK Frequency – kHz GATE BIAS OUTPUT VOLTAGE vs CLK FREQUENCY – 3 60 65 70 75 VO
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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Implementation of integrated circuits in low-profile and fine-pitch packages requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: /C0068Improving the power-dissipation capability of the PWB design /C0068Improving the thermal coupling of the component to the PWB /C0068Introducing airflow in to the system Using the given RθJA for this IC, the maximum power dissipation can be calculated with the equation: P D max /C0043 TJmax /C0042TA R /C0113JA For the TPS9103, the power dissipation is in the PMOSFET. To calculate the power, use: I2 /C0032R where I is the current through the device and R is the internal resistance as shown in the electrical characteristics table. For a VI of 6 V, the resistance at 85°C is 0.210 Ω . At a current of 2 A, the peak power dissipation is: PD /C004322 /C00320.210/C00430.84 W Assuming a duty cycle of 1/8 or 0.125, the average power is: 0.84 W /C00320.125/C00430.105 W The change in temperature is: and the junction temperature is:
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Traditionally the RF power amplifier (PA) is powered directly from the battery, with a switching arrangement for powering down when not in use. GaAs FET PAs require a negative bias voltage that must be present before the supply is connected, or there is risk of destroying the FET. Logic must be provided to ensure the presence of the negative bias voltage. A secondary charge pump is necessary for systems in which the supply voltage is insufficiently high – the negative bias produced from the charge pump is inadequate. In mobile telephony a second charge pump (regulated or unregulated) may also be needed, e.g. for varicap diodes/VCOs and some preamplifiers. The need for larger dynamic range or control-voltage range can become critical in certain applications. the TPS9103 approach The TPS9103 integrates a P-channel MOSFET high-side switch together with a selectable oscillator and charge pump for the GaAs FET power-amplifier gate bias, which is monitored. Complete precautions are taken to ensure that the PA supply is not enabled unless the gate bias is present while V CC and VDD are also good. This protects the PA from inadvertent damage–without a major system size/cost increase. The bias regulation monitor is flexible, accommodating both fixed and programmable approaches. The fixed resistors, provided internally, set the trip voltage to –0.6 x VDD . If VDD is 5 V, then the trip voltage is –3 V. Should another value be preferred, it can be set by applying voltage divider to PGP. See the section “dimensioning the external voltage divider” for more details. The charge pump clock is also flexible. The on-chip oscillator runs at a nominal 50 kHz, or alternatively an external oscillator can be connected to CLK. When an external clock is used, OSC_EN should be taken high to disable the oscillator. When OSC_EN is low and the on-chip oscillator is used, CLK provides an unbuffered clock output. The circuit provides for a secondary charge pump driver. The buffered BCLK output can be used (with four external components) to provide a higher supply, both for those system functions that require it and for those GaAs PAs that need a more negative bias than is made possible by inverting the existing supply. This is facilitated by use of single-cell Li-ion batteries. Figure 14 shows the TPS9103 in a typical application.
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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BATT_IN BATT_IN BATT_IN SW_EN C1+ C1– VDD EN OSC_EN GND GND BATT_OUT BATT_OUT BATT_OUT GATE_BIAS PG PGP CLK BCLK 0.1 µF 0.1 µF 4.7 µF 0.33 µF 0.1 µF 4.7 µF+ PA Drain TSP9103 Battery
4 V to 8 V
3.3 V 17 10
2 VCC
PA Gate–3 V Figure 14. Typical Application
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 capacitors of the internal inverting charge pump (see Figure 15) This charge pump inverts the voltage at VDD and provides a negative output voltage at GATE_BIAS. Charge Pump GATE_BIAS C + C – TPS9103 Figure 15. Internal Inverting Charge Pump With a capacitor C6 of 4.7 µF and an output current of 10 mA, the voltage ripple at GATE_BIAS is 42 mV. the output is –4.05 V with a 42 mV ripple. The capacitors should have a low equivalent series resistance (ESR) to maintain low ripple and low noise.
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996
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dimensioning of the external charge pump For systems in which the bias voltage requirement is not met by inverting the power rail, the BCLK output can be used (with four passive components) to generate a higher VDD. The higher voltage is then inverted as before to produce the bias voltage. This voltage is also available for other parts of the main circuitry (see Figure 16). With the TPS9103, an external charge pump could be used to increase the voltage at VDD , thereby deriving a higher negative voltage at GATE_BIAS than would otherwise be available. VDD VCC V BCLK Figure 16. External Charge Pump capacitor C8 charges up to 2 VCC – 2 Vdiode. This voltage can then be connected to VDD . C8 depends on the load current. ICC = 10 mA, the value of C8 is 3 µF. A 4.7 µF meets this requirement. V on VCC the output is 4.2 V with a 42-mV ripple.
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 BATT_IN BATT_IN BATT_IN SW_EN C1+ C1– EN OSC_EN GND GND BATT_OUT BATT_OUT BATT_OUT GATE_BIAS VDD PGP CLK BCLK 0.1 µF 0.1 µF 4.7 µF 0.33 µF 0.1 µF 4.7 µF+ PA Drain TSP9103 Battery 3.3 V 17 10 XMIT PA Gate–3 V 0.22 µF PG 9 + C8 4.7 µF Figure 17. TPS9103 Configured With External Charge Pump
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switched on when the voltage at GATE_BIAS reaches –3 V. values, R1 and R2, are chosen within the 10-kΩ range. Figure 18. External Voltage Divider for Setting the Trip Point where VDD = supply voltage, and Vtrip = chosen value to trip PG comparator.
POWER SUPPLY FOR GaAs POWER AMPLIFIERS SLVS131A – OCTOBER 1995 – REVISED JULY 1996 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040064/D 10/95
14 PIN SHOWN
0,10 MIN1,20 MAX A 0,19 4,50 4,30 6,10 6,70 0,32 0,75 0,50 0,25 Gage Plane 0,15 NOM 0,65 M0,13 0°–8° 0,10 PINS ** A MIN A MAX DIM 2,90 3,10 4,90 5,10 6,60 6,404,90 5,10 7,70 7,90 9,60 9,80 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
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