TPS82140 TI | Alldatasheet
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Technical content
Load (A) Efficiency (%) 100 1m 10m 100m 1 5 D017 VOUT = 1.0 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V TPS82140 12V 124k 100k VIN POWER GOOD VIN EN 22µF 100k VOUT 1.8V/2AC1 10µF SS/TR GND PG FB VOUT 3.3nF Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS82140 SLVSDN3 –JUNE 2017 TPS8214017-VInput2-AStep-DownConverterMicroSiP™ ModulewithIntegrated Inductor
1 Features
1• 3.0-mm x 2.8-mm x 1.5-mm MicroSiP™ Package
- 3.0-V to 17-V Input Range
- 2-A Continuous Output Current
- DCS-Control™ Topology
- Power Save Mode for Light Load Efficiency
- 20-µA Operating Quiescent Current
- 0.9-V to 6-V Adjustable Output Voltage
- 100% Duty Cycle for Lowest Dropout
- Power Good Output
- Programmable Soft Startup with Tracking
- Thermal Shutdown Protection
- Pin to Pin compatible with TPS82130 and TPS82150
- –40°C to 125°C Operating Temperature Range
- Create a Custom Design using the TPS82140 with the WEBENCH® Power Designer
2 Applications
- Industrial Applications
- Telecom and Networking Applications
- Solid State Drives
- Inverting Power Supply space space
3 Description
The TPS82140 is a 17-V input 2-A step-down converter MicroSiP™ power module optimized for small solution size and high efficiency. The module integrates a synchronous step-down converter and an inductor to simplify design, reduce external components and save PCB area. The low profile and compact solution is suitable for automated assembly by standard surface mount equipment. To maximize efficiency, the converter operates in PWM mode with a nominal switching frequency of 2.0MHz and automatically enters Power Save Mode operation at light load currents. In Power Save Mode, the device operates with typically 20-µA quiescent current. Using the DCS-Control™ topology, the device achieves excellent load transient performance and accurate output voltage regulation. space Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS82140SIL µSiL (8) 3.0 mm x 2.8 mm x 1.5 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic spacespace Efficiency vs Output Current, VIN=12V space
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11.2 Receiving Notification of Documentation Updates 20
12 Mechanical, Packaging, and Orderable
4 Revision History
June 2017 * Initial release.
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5 Pin Configuration and Functions
8-Pin µSiL Package (SIL0008C Top View) space Pin Functions PIN I/O DESCRIPTION NAME NO. EN 1 I Enable pin. Pull High to enable the device. Pull Low to disable the device. This pin has an internal pull-down resistor of typically 400kΩ when the device is disabled. VIN 2 PWR Input pin. GND 3 Ground pin. VOUT 4,5 PWR Output pin. FB 6 I Feedback reference pin. An external resistor divider connected to this pin programs the output voltage. PG 7 O Power good open drain output pin. A pull-up resistor can be connected to any voltage less than 6V. Leave it open if it is not used. SS/TR 8 I Soft startup and voltage tracking pin. An external capacitor connected to this pin sets the internal reference voltage rising time. Exposed Thermal Pad The exposed thermal pad must be connected to the GND pin. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground pin.
6 Specifications
6.1 Absolute Maximum Ratings(1)
Voltage at pins(2) VIN -0.3 20 V EN, SS/TR -0.3 VIN + 0.3 PG, FB -0.3 7 VOUT 0 7 Sink current PG 10 mA Module operating temperature –40 125 °C Storage temperature –55 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22- C101(2) ±1000 (1) The module operating temperature range includes module self temperature rise and IC junction temperature rise. In applications where high power dissipation is present, the maximum operating temperature or maximum output current must be derated. For applications where the module operates continuously at 125 °C temperature, the maximum lifetime is reduced to 50,000 hours.
6.3 Recommend Operating Conditions
VPG Power good pull-up resistor voltage 6 V VOUT Output voltage 0.9 6 V IOUT Output current 0 2 A TJ Module operating temperature range for 100,000 hours lifetime(1) -40 110 °C (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Theta-JA can be improved with a custom PCB design containing thermal vias where possible.
6.4 Thermal Information
THERMAL METRIC(1) TPS82140 UNIT8-Pin SIL JEDEC 51-5 EVM RθJA Junction-to-ambient thermal resistance 58.2 46.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 9.4 9.4 °C/W RθJB Junction-to-board thermal resistance 14.4 14.4 °C/W ψJT Junction-to-top characterization parameter 0.9 0.9 °C/W ψJB Junction-to-board characterization parameter 14.2 14.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 21.3 21.3 °C/W
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6.5 Electrical Characteristics
TJ = -40°C to 125°C and VIN = 3.0V to 17V. Typical values are at TJ = 25°C and VIN = 12V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Quiescent current into VIN No load, device not switching 20 35 µA ISD Shutdown current into VIN EN = Low 1.5 7.4 µA VUVLO Under voltage lock out threshold VIN falling 2.6 2.7 2.8 V VIN rising 2.8 2.9 3.0 V TJSD Thermal shutdown threshold TJ rising 160 °C TJ falling 140 °C LOGIC INTERFACE (EN) VIH High-level input voltage 0.9 0.65 V VIL Low-level input voltage 0.45 0.3 V Ilkg(EN) Input leakage current into EN pin EN = High 0.01 1 µA CONTROL (SS/TR, PG) ISS/TR SS/TR pin source current 2.1 2.5 2.8 µA VPG Power good threshold VOUT rising, referenced to VOUT nominal 92% 95% 99% VOUT falling, referenced to VOUT nominal 87% 90% 94% VPG,OL Power good low-level voltage Isink = 2mA 0.1 0.3 V Ilkg(PG) Input leakage current into PG pin VPG = 1.8V 1 400 nA OUTPUT VFB Feedback regulation voltage PWM mode 785 800 815 mV TJ = 0°C to 85°C 788 800 812 PSM COUT = 22µF 785 800 823 COUT = 2x22µF, TJ = 0°C to 85°C 788 800 815 Ilkg(FB) Feedback input leakage current VFB = 0.8V 1 100 nA Line regulation IOUT = 1A, VOUT = 1.8V 0.002 %/V Load regulation IOUT = 0.5A to 2A, VOUT = 1.8V 0.12 %/A POWER SWITCH RDS(on) High-side FET on-resistance ISW = 500mA, VIN ≥ 6V 90 170 mΩ ISW = 500mA, VIN = 3V 120 Low-side FET on-resistance ISW = 500mA, VIN ≥ 6V 40 70 ISW = 500mA, VIN = 3V 50 RDP Dropout resistance 100% mode, VIN ≥ 6V 125 mΩ 100% mode, VIN = 3V 160 ILIMF High-side FET switch current limit VIN = 6V, TJ = 25°C 3 3.5 4 A fSW PWM switching frequency IOUT = 1A, VOUT = 1.8V 2.0 MHz
6.6 Typical Characteristics
Figure 1. Dropout Resistance Figure 2. Quiescent Current Figure 3. Shutdown Current
400kΩ (1) Note: (1) When the device is enabled, the 400 k resistor is disconnected. (2) The integrated inductor of 1 µH in the module. Ω L (2) Voltage Clamp VIN VREF SS/TR 22pF Copyright 2016, Texas Instruments Incorporated© TPS82140 www.ti.com SLVSDN3 –JUNE 2017 Product Folder Links: TPS82140 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
7 Detailed Description
7.1 Overview
The TPS82140 synchronous step-down converter MicroSiP™ power module is based on DCS-Control™ (Direct Control with Seamless transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of hysteretic and voltage mode control. The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load conditions and in PSM (Power Save Mode) at light load currents. In PWM mode, the converter operates with its nominal switching frequency of 2.0MHz having a controlled frequency variation over the input voltage range. As the load current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC's quiescent current to achieve high efficiency over the entire load current range. DCS-Control™ supports both operation modes using a single building block and therefore has a seamless transition from PWM to PSM without effects on the output voltage. The TPS82140 offers excellent DC voltage regulation and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
DPOUT(min)OUT(min)IN RIVV /c180/c43/c61 L VV V Vt I 2f OUTIN OUT IN2 ON OUT PSM /c45/c180/c180 /c180/c61 L VVtI OUTIN ONL /c45/c180/c61/c68 IN OUT ON V Vns500t /c180/c61 TPS82140 SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 PWM and PSM Operation
The TPS82140 includes an on-time (tON) circuitry. This tON, in steady-state operation in PWM and PSM modes, is estimated as: space (1) space In PWM mode, the TPS82140 operates with pulse width modulation in continuous conduction mode (CCM) with a tON shown in Equation 1 at medium and heavy load currents. A PWM switching frequency of typically 2.0MHz is achieved by this tON circuitry. The device operates in PWM mode as long as the output current is higher than half the inductor's ripple current estimated by Equation 2. space (2) space To maintain high efficiency at light loads, the device enters Power Save Mode seamlessly when the load current decreases. This happens when the load current becomes smaller than half the inductor's ripple current. In PSM, the converter operates with reduced switching frequency and with a minimum quiescent current to maintain high efficiency. PSM is also based on the tON circuitry. The switching frequency in PSM is estimated as: space (3) space In PSM, the output voltage rises slightly above the nominal output voltage in PWM mode. This effect is reduced by increasing the output capacitance. The output voltage accuracy in PSM operation is reflected in the electrical specification table and given for a 22-µF output capacitor. For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Also the off-time can reach its minimum value at high duty cycles. The output voltage remains regulated in such cases. When VIN decreases to typically 15% above VOUT, the TPS82140 can't enter Power Save Mode, regardless of the load current. The device maintains output regulation in PWM mode.
7.3.2 Low Dropout Operation (100% Duty Cycle)
The TPS82140 offers a low input to output voltage differential by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain a minimum output voltage is given by: space (4) space Where RDP = Resistance from VIN to VOUT, including high-side FET on-resistance and DC resistance of the inductor VOUT(min) = Minimum output voltage the load can accept.
7.3.3 Switch Current Limit
the battery or input voltage rail. Excessive current might occur with a heavy load/shorted output circuit condition. side FET is turned off and the low-side FET is turned on to ramp down the inductor current.
7.3.4 Undervoltage Lockout
down the devices at voltages lower than VUVLO with a hysteresis of 200mV.
7.3.5 Thermal Shutdown
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable (EN)
pin is pulled Low with a shutdown current of typically 1.5 μA. resistor is disconnected when the EN pin is High.
7.4.2 Soft Startup (SS/TR)
pin is discharged by an internal resistor. Returning from those states causes a new startup sequence.
7.4.3 Voltage Tracking (SS/TR)
circuit is shown in Figure 4. Figure 4. Output Voltage Tracking
4 R3 R
2 R1 R
SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is VIN+0.3V. Details about tracking and sequencing circuits are found in SLVA470.
7.4.4 Power Good Output (PG)
the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage. resistor connecting to any voltage rail less than 6V. of other converters. Leave the PG pin floating when it is not used. Table 1 shows the PG pin logic. Table 1. Power Good Pin Logic
8 Application and Implementation
validate and test their design implementation to confirm system functionality.
8.1 Application Information
options by using typical applications as a reference.
8.2 Typical Applications
Figure 5. 1.8-V Output Application
8.2.1.1 Design Requirements
For this design example, use the following as the input parameters. Table 2. Design Parameters The components used for measurements are given in the following table. Table 3. List of Components
V25 . 1 ItC TR / SS TR / SSTR / SS /c180/c61 OUT FB R1 R1V = V 1 + = 0.8 V 1 +R2 R2 /c230 /c246 /c230 /c246/c180 /c180/c231 /c247 /c231 /c247 /c232 /c248 /c232 /c248 TPS82140 SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS82140 device with the WEBENCH® Power Designer. 1. Start by entering your VIN, VOUT, and IOUT requirements. 2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments. 3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability. 4. In most cases, you will also be able to: – Run electrical simulations to see important waveforms and circuit performance – Run thermal simulations to understand the thermal performance of your board – Export your customized schematic and layout into popular CAD formats – Print PDF reports for the design, and share your design with colleagues 5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations: space (6) space R2 should not be higher than 100kΩ to achieve high efficiency at light load while providing acceptable noise sensitivity. Larger currents through R2 improve noise sensitivity and output voltage accuracy. Figure 5 shows the external resistor divider value for a 1.8-V output. Choose appropriate resistor values for other outputs. In case the FB pin gets opened, the device clamps the output voltage at the VOUT pin internally to about 7V.
8.2.1.2.3 Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR ceramic capacitors are required. The input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail for the device. A 10-µF or larger input capacitor is required. The output capacitor value can range from 22μF up to more than 400μF. Higher values are possible as well and can be evaluated through the transient response. Larger soft start times are recommended for higher output capacitances. High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance.
8.2.1.2.4 Soft Startup Capacitor Selection
A capacitance connected between the SS/TR pin and the GND allows programming the startup slope of the output voltage. A constant current of 2.5 μA charges the external capacitor. The capacitance required for a given soft startup time for the output voltage is given by: space (7)
8.2.1.3 Application Performance Curves
TA = 25°C, VIN = 12 V, VOUT = 1.8 V, unless otherwise noted. Figure 6. Efficiency, VOUT = 1.0 V Figure 7. Efficiency, VOUT = 1.0 V Figure 8. Efficiency, VOUT = 1.8 V Figure 9. Efficiency, VOUT = 1.8 V Figure 10. Efficiency, VOUT = 2.5 V Figure 11. Efficiency, VOUT = 2.5 V
8.3 System Examples
8.3.1 Inverting Power Supply
The TPS82140 can be used as inverting power supply by rearranging external circuitry as shown in Figure 30. VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 8). Figure 30. Inverting Power Supply Schematic information is given in TIDUCV2.
9 Power Supply Recommendations
Ensure that the power supply has a sufficient current rating for the applications.
10 Layout
10.1 Layout Guidelines
- TI recommends placing all components as close as possible to the IC. The input capacitor placement specifically, must be closest to the VIN and GND pins of the device.
- Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
- To enhance heat dissipation of the device, the exposed thermal pad should be connected to bottom or internal layer ground planes using vias.
- Refer to Figure 31 for an example of component placement, routing and thermal design.
10.2 Layout Example
Figure 31. TPS82140 PCB Layout
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10.3 Thermal Consideration
The output current of the TPS82140 needs to be derated when the device operates in a high ambient temperature or delivers high output power. The amount of current derating is dependent upon the input voltage, output power, PCB layout design and environmental thermal condition. Care should especially be taken in applications where the localized PCB temperature exceeds 65°C. The TPS82140 module temperature must be kept less than the maximum rating of 125°C. Three basic approaches for enhancing thermal performance are below:
- Improve the power dissipation capability of the PCB design.
- Improve the thermal coupling of the TPS82140 to the PCB.
- Introduce airflow into the system. To estimate approximate module temperature of TPS82140, apply the typical efficiency stated in this datasheet to the desired application condition to find the module's power dissipation. Then calculate the module temperature rise by multiplying the power dissipation by its thermal resistance. For more details on how to use the thermal parameters in real applications, see the application notes: SZZA017 and SPRA953.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS82140 device with the WEBENCH® Power Designer. 1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements. 2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial. 3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability. In most cases, these actions are available:
- Run electrical simulations to see important waveforms and circuit performance
- Run thermal simulations to understand board thermal performance
- Export customized schematic and layout into popular CAD formats
- Print PDF reports for the design, and share the design with colleagues Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.4 Trademarks
MicroSiP, DCS-Control, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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11.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com PACKAGE OUTLINE C B 2.9 2.7 A 3.1 2.9 (45 X0.25) PIN 1 ID 1.95 6X 0.65 (0.1) TYP 8X 0.42 0.38 8X 0.52 0.48
1.53 MAX
1.9±0.1 1.1±0.1 (2.5) (2) MicroSiP - 1.53 mm max heightSIL0008D MICRO SYSTEM IN PACKAGE 4221520/A 07/2015 PIN 1 INDEX AREAPICK AREA NOTE 3 0.08 C
0.1 C A B
0.05 C 4 5 SYMM SYMM THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pick and place nozzle 1.3 mm or smaller recommended. 4. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. MicroSiP is a trademark of Texas Instruments TM 0.08 C SCALE 4.000 TPS82140 SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
www.ti.com EXAMPLE BOARD LAYOUT (1.1) 8X (0.5)
0.05 MIN
8X (0.4) (2.1) 6X (0.65) (0.75) ( ) VIA TYP 0.2 (1.9) (R ) TYP0.05 MicroSiP - 1.53 mm max heightSIL0008D MICRO SYSTEM IN PACKAGE 4221520/A 07/2015 SYMM SYMM 4 5 SOLDER MASK DEFINED LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). TM METAL UNDER SOLDER MASK SOLDER MASK OPENING NOT TO SCALE DETAIL TPS82140 www.ti.com SLVSDN3 –JUNE 2017 Product Folder Links: TPS82140 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
www.ti.com EXAMPLE STENCIL DESIGN (R ) TYP0.05 8X (0.4) (1.04) 8X (0.5) 6X (0.65) (2.1) (0.85) (1.05) MicroSiP - 1.53 mm max heightSIL0008D MICRO SYSTEM IN PACKAGE 4221520/A 07/2015 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. TM SYMM SYMM METAL TYP BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 85% PRINTED SOLDER COVERAGE BY AREA SCALE:30X SOLDER MASK EDGE 4 5 TPS82140 SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed TPS82140 www.ti.com SLVSDN3 –JUNE 2017 Product Folder Links: TPS82140 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated
12.1 Package Materials Information
12.1.1 Tape and Reel Information
(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant
TAPE AND REEL BOX DIMENSIONS Width (mm) W L H TPS82140 SLVSDN3 –JUNE 2017 www.ti.com Product Folder Links: TPS82140 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS82140SILR µSiP SIL 8 3000 383.0 353.0 58.0 TPS82140SILT µSiP SIL 8 250 223.0 194.0 35.0
www.ti.com 2-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS82140SILR Active Production uSiP (SIL) | 8 3000 | LARGE T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R TPS82140SILR.A Active Production uSiP (SIL) | 8 3000 | LARGE T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R TPS82140SILR.B Active Production uSiP (SIL) | 8 3000 | LARGE T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R TPS82140SILT Active Production uSiP (SIL) | 8 250 | SMALL T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R TPS82140SILT.A Active Production uSiP (SIL) | 8 250 | SMALL T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R TPS82140SILT.B Active Production uSiP (SIL) | 8 250 | SMALL T&R Yes NIAU Level-2-260C-1 YEAR -40 to 125 5R (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 2-Jun-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 22-Apr-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS82140SILR uSiP SIL 8 3000 383.0 353.0 58.0 TPS82140SILT uSiP SIL 8 250 223.0 194.0 35.0 Pack Materials-Page 2
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