TPS81256

TPS81256_14 TI1 | Alldatasheet

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SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE DEVICE OPTION PACKAGEDEVICEPART NUMBER OUTPUT VOLTAGE ORDERING MARKINGSPECIFIC FEATURES CHIP CODE TPS81256 5.0V TPS81256SIP TT TPS81257(1) 5.1V TPS81257SIP (1) Product preview. Contact TI factory for more information ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) UNIT Input voltage TPS8125x Voltage at VIN(2), VOUT(2), EN(2) –0.3 to 6 V Continuous average current into VIN(3) 1.05 A Input current TPS8125x Pulsed current into VIN(4) 1.3 A Power dissipation Internally limited Operating temperature range, TA Temperature range Operating virtual junction, TJ –40 to 150 °C Storage temperature range, Tstg –55 to 125 °C Human Body Model - (HBM) 2000 V ESD rating(6) Charge Device Model - (CDM) 1000 V Machine Model - (MM) 200 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to network ground terminal. (3) Limit the junction and the (top side) inductor case temperature to 110°C, limit the (top side) capacitor case temperature to 85°C for 2000h operation at maximum output power. Contact TI for more details on lifetime estimation. (4) Limit the (top side) inductor case temperature to 140°C and the (top side) capacitor temperature to 115°C for 100h operation. Contact TI for more details on lifetime estimation. (5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max)). To achieve optimum performance, it is recommended to operate the device with a maximum junction temperature of 125°C, a maximum inductor case temperature of 125°C and a maximum capacitor case temperature of 85°C. (6) The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin.

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www.ti.com SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 THERMAL INFORMATION TPS8125x THERMAL METRIC(1)(2) SIP UNIT

9 PINS

θJA Junction-to-ambient thermal resistance 62 ψJB Junction-to-board characterization parameter 31 °C/W ψJT Junction-to-case (top) thermal resistance (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) Thermal data have been simulated with high-K board (per JEDEC standard). RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI Input voltage range TPS81256 2.5 5.5 V RL Minimum resistive load for start-up (VI ≤ 4.8V) TPS81256 65 Ω CEXT Output capacitance 2 30 µF TA Ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C TCASE_IND Operating inductor case temperature 125 °C TCASE_CAP Operating capacitor case temperature 85 °C

ELECTRICAL CHARACTERISTICS

Minimum and maximum values are at VIN = 2.5V to 5.5V, VOUT = 5.0V (or VIN, whichever is higher), EN = 1.8V, TA = –40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at VIN = 3.6V, VOUT = 5.0V, EN = 1.8V, TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Operating quiescent current into VIN (1) IOUT = 0mA, VOUT = 5.0V, VIN = 3.6V 30 50 µA IQ TPS8125X EN = VIN Operating quiescent current into VOUT (1) 7 20 µADevice not switching ISD Shutdown current(1) TPS8125x EN = GND 0.85 5.0 μA Falling 2.0 2.1 V VUVLO Under-voltage lockout threshold TPS81256 Hysteresis 0.1 V ENABLE VIL Low-level input voltage 0.4 V VIH High-level input voltage TPS8125x 1.0 V Ilkg Input leakage current Input connected to GND or VIN 0.5 µA OUTPUT 3.3V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 550mAVOUT Regulated DC output voltage TPS81256 4.85 5 5.2 VPFM/PWM operation 2.9V ≤ VIN ≤ 4.85V, 0mA ≤ IOUT ≤ 450mA 4.85 5 5.2 VPFM/PWM operation Power-save mode output ripple voltage PFM operation, IOUT = 1mA 35 mVpk ΔVOUT TPS81256 PWM mode output ripple voltage PWM operation, IOUT = 200mA 8 mVpk POWER SWITCH rDS(on) Input-to-output On-resistance TPS8125x VI = 5.25 V. Device not switching 320 mΩ Ilkg Reverse leakage current into VOUT(1) TPS81256 EN = GND 5 µA ILIM Average input current limit TPS8125x EN = VIN. VIN = 3.3V 1180 mA Overtemperature protection 140 °C TPS8125x Overtemperature hysteresis 20 °C (1) Maximum values can vary over lifetime due to intrinsic capacitor ageing effects. For more details, refer to THERMAL AND RELIABILITY INFORMATION section. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS81256

= 5.0V, EN = 1.8V, TA = 25°C (unless otherwise noted). Table 1. TERMINAL FUNCTIONS VIN C1, C2 I Power supply input. VOUT A3, B3, C3 O Boost converter output.

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Table 2. List of Components

SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE vs Output current 3, 5 η Efficiency vs Input voltage 4 vs Output current 6, 7, 8 VO DC output voltage vs Input voltage 9 IO Maximum output current vs Input voltage 10 ΔVO Peak-to-peak output ripple voltage vs Output current 11 ICC Supply current vs Input voltage 12 ILIM Input current vs Output current 13 AC load transient response 14 Load transient response 15, 16, 17 Combined line/load transient response 18 Overload recovery response 19 Start-up 20 TABLE OF ANIMATED PERFORMANCE CHARACTERISTICS VIDEO AC Load Response vs. Input Voltage Video 1 Load Transient Response (10mA to 400mA) vs. Input Voltage Video 2 vs. Base Load Current (2.9VIN) Video 3 Load Transient Response (to 400mA) vs. Base Load Current (3.6VIN) Video 4 vs. Base Load Current (4.2VIN) Video 5 vs. Delay to Load Current (2.9VIN) Video 6 Start-Up Response vs. Delay to Load Current (3.6VIN) Video 7 vs. Delay to Load Current (4.2VIN) Video 8 Start-Up Response (200mA IOUT) vs. Input Voltage Video 9 Overload Response vs. Input Voltage Video 10

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Figure 7. Figure 8. Figure 9. Figure 10.

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Figure 15. Figure 16. Figure 17. Figure 18.

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Figure 19. Figure 20.

SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 www.ti.com DETAILED DESCRIPTION OPERATION The TPS8125x is a stand-alone, synchronous, step-up converter. The converter operates at a quasi-constant 4- MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS8125x converter operates in power-save mode with pulse frequency modulation (PFM). During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on timer again and activating the low-side N-MOS switch. In general, a dc/dc step-up converter can only operate in "true" boost mode, i.e. the output “boosted”by a certain amount above the input voltage. The TPS8125x device operates differently as it can smoothly transition in and out of zero duty cycle operation. Therefore the output can be kept as close as possible to its regulation limits even though the converter is subject to an input voltage that tends to be excessive. In this operation mode, the output current capability of the regulator is limited to ca. 150mA. Refer to the typical characteristics section (DC Output Voltage vs. Input Voltage) for further details. The current mode architecture with adaptive slope compensation provides excellent transient load response while requiring only one external tiny capacitor for output filtering and loop stability purposes. Internal soft-start and loop compensation simplifies the application design process. POWER-SAVE MODE The TPS8125X integrates a power-save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in PFM mode.

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/c104/c103 /c103OUT OUT(DC) IN(CL) IN VI = I V TPS81256 www.ti.com SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 CURRENT LIMIT OPERATION, MAXIMUM OUTPUT CURRENT The TPS8125x directly and accurately controls the average input current through intelligent adjustment of the valley current limit. The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off-time by sensing of the voltage drop across the synchronous rectifier. The output voltage is reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by Equation 1. (1) The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached the output voltage decreases during further load increase. SOFTSTART, ENABLE The TPS8125x device starts operation when EN is set high and starts up with the soft-start sequence. For proper operation, the EN pin must be terminated and must not be left floating. The TPS8125x device has an internal softstart circuit that limits the inrush current during start-up. The first step in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (approx. 200mA) during this phase. This mechanism is used to limit the output current under short-circuit condition. Once the output capacitor has been biased to the input voltage, the converter starts switching. The soft-start system progressively increases the on-time as a function of the input-to-output voltage ratio. As soon as the output voltage is reached, the regulation loop takes control and full current operation is permitted. Pulling the EN pin low forces the device in shutdown, with a shutdown current of typically 1µA. In this mode, true load disconnect between the battery and load prevents current flow from VIN to VOUT, as well as reverse flow from VOUT to VIN. LOAD DISCONNECT AND REVERSE CURRENT PROTECTION Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will be discharge during shutdown. The advantage of TPS8125x is that this converter is disconnecting the output from the input of the power supply when it is disabled (so called true shutdown mode). In case of a connected battery it prevents it from being discharge during shutdown of the converter. UNDERVOLTAGE LOCKOUT The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO threshold plus its hysteresis of 100 mV at typ. 2.1V. THERMAL REGULATION The TPS8125x device contains a thermal regulation loop that monitors the die temperature during the pre-charge phase. If the die temperature rises to high values of about 110 °C, the device automatically reduces the current to prevent the die temperature from increasing further. Once the die temperature drops about 10 °C below the threshold, the device will automatically increase the current to the target value. This function also reduces the current during a short-circuit condition. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 140°C (typ.) the device goes into thermal shutdown. In this mode, the high-side and low-side MOSFETs are turned-off. When the junction temperature falls below the thermal shutdown minus its hysteresis, the device continuous the operation. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPS81256

ESR OUT ESRV I R/c61 /c103 /c40 /c41 /c45 /c68 /c61 /c103 /c103 /c103 OUT OUT IN OUT I V VV C V f TPS81256 SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 www.ti.com

APPLICATION INFORMATION

Because of the pulsating output current nature of the boost converter, a low ESR output capacitor is required to maintain control loop stability, to enhance the converter's transient response and to reduce the output voltage ripple. For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC. The minimum capacitance is 2μF. To get an estimate of the steady ripple due to charging and discharging the output capacitance, Equation 2 can be used. (2) Where f is the switching frequency which is 4MHz (typ.) and C is the effective output capacitance. Notice the TPS8125x device already incorporates ca. 1.2μF effective output capacitance. In practice, the total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 3 (3) An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause lower output voltage ripple as well as lower output voltage drop during load transients but the total output capacitance value should not exceed ca. 30µF. DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size and voltage rating in combination with material are responsible for differences between the rated capacitor value and it's effective capacitance. For instance, a 4.7µF X5R 16V 0603 MLCC capacitor would typically show an effective capacitance of less than 2.5µF (under 5V bias condition, high temperature and ageing effects). Because the damping factor in the output path is directly related to several resistive parameters (e.g. inductor DCR, power-stage rDS(on), PWB DC resistance, load switches rDS(on) … ) that are temperature dependant, the converter small and large signal behavior must be checked over the input voltage range, load current range and temperature range. The easiest sanity test is to evaluate, directly at the converter’s output, the following aspects:

• PFM/PWM efficiency
• PFM/PWM and PWM load transient response During the recovery time from a load transient, the output voltage can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.

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www.ti.com SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 INPUT CAPACITOR In a dc/dc boost converter, since the input current is continuous, only minimum input capacitor is required. The TPS8125x device integrates a low ESR decoupling capacitor to prevent large voltage transients that can cause misbehavior of the device or interference in other circuits in the system. For most applications, the input capacitor that is integrated into the TPS8125x should be sufficient. If the application exhibits a noisy or erratic switching frequency, experiment with additional input capacitance to find a remedy. Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have extremely low ESR and are available in small footprints. Additional input capacitors should be located as close as possible to the device. The TPS8125x uses a tiny ceramic input capacitor. When a ceramic capacitor is combined with trace or cable inductance, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or can even damage the part. In this circumstance, additional "bulk" capacitance, such as electrolytic or tantalum, should be placed between the input of the converter and the power source lead to reduce ringing that can occur between the inductance of the power source leads and CI. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TPS81256

1 F/c109

4.7 F/c109

10 F/c109

0.1 F/c109

47 F/c109

5.0 V, up to 550mA

but is also required to stable operation of the SMPS converter. The SMPS converter should be located in the close vicinity of the audio power amplifier. Figure 21. "Boosted" Audio Power Supply Figure 22. Battery Powered USB-DCP Power Supply

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Figure 23. Recommended Land Pattern Image and Dimensions Area" in the package drawings. similarly to a 0805 component. See JEDEC/IPC standard J-STD-20b for reflow recommendations.

where the localized PWB temperature exceeds 65°C. power dissipation by the thermal resistance. Figure 24. VIN=3.6V, VOUT=5V, IOUT=300mA Figure 25. VIN=3.6V, VOUT=5V, IOUT=600mA 150mW Power Dissipation at Room Temp. 600mW Power Dissipation at Room Temp. temperatures for prolonged or repetitive intervals, which may damage or impair the reliability of the device. operating temperature and voltage.

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E TOP VIEW BOTTOM VIEW YML LSB CC 0.01 0.1 100 1000 10000 20 40 60 80 100 120 140 Capacitor Case Temperature ( °C) Time (Thousand Hours) VBias=5V VBias=4.35V VBias=3.6V VBias=3V G000 TPS81256 www.ti.com SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 Capacitor Lifetime vs Capacitor Case Temperature Figure 26. Failures caused by systematic degradation can be described by the Arrhenius model. The most critical is used as the failure criterion, see Figure 26. It should be noted that the wear-out mechanisms occurring in the MLCC capacitors are not reversible but cumulative over time. PACKAGE SUMMARY SIP PACKAGE Code:

• CC — Package marking Chip Code (see for more details)
• YML — Y: Year, M: Month, L: Lot trace code
• LSB — L: Lot trace code, S: Site code, B: Board locator MicroSiPTM DC/DC MODULE PACKAGE DIMENSIONS The TPS8125x device is available in an 8-bump ball grid array (BGA) package. The package dimensions are:
• D = 2.575 ±0.05 mm
• E = 2.925 ±0.05 mm Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPS81256

SLVSAZ9A –JUNE 2012–REVISED AUGUST 2013 www.ti.com

REVISION HISTORY

Note: Page numbers of current revision may differ from previous versions. Changes from Original (June 2012) to Revision A Page

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www.ti.com 20-Feb-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS81256SIPR ACTIVE uSiP SIP 9 3000 Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR -40 to 85 TT TXI256 TPS81256SIPT ACTIVE uSiP SIP 9 250 Green (RoHS & no Sb/Br) Call TI Level-2-260C-1 YEAR -40 to 85 TT TXI256 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 20-Feb-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS81256SIPR uSiP SIP 9 3000 223.0 194.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Aug-2013 Pack Materials-Page 2

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