TPS70158

TPS70145 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 34

Technical content

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Dual Output Voltages for Split-Supply

Applications

/C0068Selectable Power Up Sequencing for DSP /C0068Output Current Range of 500 mA on Regulator 1 and 250 mA on Regulator 2 /C0068Fast Transient Response /C0068Voltage Options are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs /C0068Open Drain Power-On Reset With 120-ms Delay /C0068Open Drain Power Good for Regulator 1 /C0068Ultra Low 190 mA (typ) Quiescent Current /C00681 mA Input Current During Standby /C0068Low Noise: 65 mVRMS Without Bypass Capacitor /C0068Quick Output Capacitor Discharge Feature /C0068Two Manual Reset Inputs /C00682% Accuracy Over Load and Temperature /C0068Undervoltage Lockout (UVLO) Feature /C006820-Pin PowerPAD TSSOP Package /C0068Thermal Shutdown Protection

description

TPS701xx family devices are designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervi- sory circuit, manual reset inputs, and enable function, provide a complete system solution. 1.8 V VIN1 VIN2 EN SEQ VOUT1 VSENSE1 PG1 MR2 RESET MR1 VSENSE2 VOUT2 TPS70151 PWP 5 V

3.3 V I/O

0.1 mF RESET 10 mF 10 mF 0.1 mF DSP MR2 PG1 EN 250 kW >2 V <0.7 V 250 kW >2 V <0.7 V >2 V <0.7 V PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. PWP PACKAGE (TOP VIEW) NC VIN1 VIN1 MR1 MR2 EN SEQ GND VIN2 VIN2 NC VOUT1 VOUT1 VSENSE1 /FB1 PG1 RESET VSENSE2 /FB2 VOUT2 VOUT2 NC Copyright  2000, Texas Instruments Incorporated

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued) The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10 uF low ESR capacitors. options. The 3.3-V output regulator (regulator 1) can support up to 500 mA, and the other regulator (regulator 2) can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 225 mA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 mA at TJ = 25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, V OUT2 will turn on first and VOUT1 will remain off until VOUT2 reaches approximately 83% of it’s regulated output voltage. At that time VOUT1 will be turned on. If VOUT2 is pulled below 83% (i.e. over load condition) VOUT1 will be turned off. Pulling the SEQ terminal low, reverses the power-up order and VOUT1 will be turned on first. The SEQ pin is connected to an internal pullup current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off(disabled). The PG1 pin reports the voltage conditions at the VOUT1, which can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP systems in the event of an undervoltage condition. RESET indicates the status of the VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of it’s regulated voltage and MR1 and MR2 are in the logic high state, RESET will go to a high impedance state after 120 ms delay. RESET will go to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e. over load condition) of it’s regulated voltage. To monitor VOUT1 , the PG1 output pin can be connected to MR1 or MR2. The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until VIN1 reaches 2.5V. AVAILABLE OPTIONS TJ REGULATOR 1 VO (V) REGULATOR 2 VO (V) TSSOP (PWP) 3.3 V 1.2 V TPS70145PWP 3.3 V 1.5 V TPS70148PWP –40°Ct o1 2 5°C 3.3 V 1.8 V TPS70151PWP–40°C to 125°C 3.3 V 2.5 V TPS70158PWP Adjustable (1.22 V to 5.5 V) Adjustable (1.22 V to 5.5 V) TPS70102PWP NOTE: The TPS70102 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70102PWPR).

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed block diagram – fixed voltage version UVLO Thermal Shutdown Shutdown V_UVLO Current Sense Reference VREF VREF ENA_1 ENA_1 10 kW Rising Edge Deglitch0.95 × VREP FB2 Falling Edge Delay VIN1 PG1 Comp 0.95 × VREF FB1 Rising Edge Deglitch Falling Edge Deglitch0.83 × VREF FB2 UV Comp Falling Edge Deglitch0.83 × VREF FB1 UV Comp Power Sequence Logic SHUTDOWN ENA_! ENA_2 VCC Current Sense 10 kW ENA_2 ENA_2 FB2VREF VIN1 (2 Pins) GND EN SEQ (see Note B) VIN2 (2 Pins) VOUT1 (2 Pin) VSENSE1 (see Note A) PG1 MR2 RESET MR1 VSENSE2 (see Note A) VOUT2(2 Pin) FB1 VCC NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in Application information section. B. If the SEQ terminal is floating at the input, the VOUT2 will power-up first.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed block diagram – adjustable voltage version UVLO Thermal Shutdown Shutdown 2.5 V Current Sense Reference VREF VREF ENA_1 ENA_1 Rising Edge Deglitch0.95 × VREP FB2 Falling Edge Delay VIN1 PG1 Comp 0.95 × VREF FB1 Rising Edge Deglitch Falling Edge Deglitch0.83 × VREF FB2 UV Comp Falling Edge Deglitch0.83 × VREF FB1 UV Comp Power Sequence Logic SHUTDOWN ENA_! ENA_2 VCC Current Sense ENA_2 ENA_2 VREF VIN1 (2 Pins) GND EN SEQ (see Note B) VIN2 (2 Pins) VOUT1 (2 Pin) FB1 (see Note A) PG1 MR2 RESET MR1 FB2 (see Note A) VOUT2 (2 Pin) VCC NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in Application information section. B. If the SEQ terminal is floating at the input, the VOUT2 will power-up first.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RESET timing diagram NOTES: A. V res is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. Î Î Î Î Î Î Î Î Î Î VIN1 and VIN2 Vres (see Note A) Vres t t t VOUT2 Threshold Voltage RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined VIT+(see Note B) VIT– (see Note B) VIT+(see Note B) B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO ) VIT– to VIT+ is the hysteresis voltage. VIT– (see Note B) PG timing diagram NOTES: A. V res is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Vres t t t Threshold Voltage PG Output Output Undefined Output Undefined VIT+(see Note B)VIT+(see Note B) B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO ) VIT– to VIT+ is the hysteresis VIN1 and VIN2 VOUT2 Vres (see Note A) VIT– (see Note B) VIT– (see Note B)

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NAME NO. I/O DESCRIPTION EN 6 I Active low enable GND 8 Ground MR1 4 I Manual reset input 1, active low, pulled up internally MR2 5 I Manual reset input 2, active low, pulled up internally NC 1, 11, 20 No connection PG1 16 O Open drain output, low when VOUT1 voltage is less than 55 of the nominal regulated voltage RESET 15 O Open drain output, SVS (power on reset) signal, active low SEQ 7 I Power up sequence control: SEQ=High, VOUT2 powers up first; SEQ=Low, VOUT1 powers up first, SEQ terminal pulled up internally. VIN1 2, 3 I Input voltage of regulator 1 VIN2 9, 10 I Input voltage of regulator 2 VOUT1 18, 19 O Output voltage of regulator 1 VOUT2 12, 13 O Output voltage of regulator 2 VSENSE2 /FB2 14 I Regulator 2 output voltage sense/ regulator 2 feedback for adjustable VSENSE1 /FB1 17 I Regulator 1 output voltage sense/ regulator 2 feedback for adjustable absolute maximum ratings over operating junction temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are tied to network ground. DISSIPATION RATING TABLE PACKAGE AIR FLOW (CFM) TA ≤ 25°C ÁÁÁÁÁÁ ÁÁÁÁÁÁ DERATING FACTOR TA = 70°C TA = 85°C ÁÁÁÁÁ ÁÁÁÁÁ PWP § ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ 3.067 W ÁÁÁÁÁÁ ÁÁÁÁÁÁ 30.67 mW/°C ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1.687 W ÁÁÁÁÁÁ ÁÁÁÁÁÁ 1.227 W ÁÁÁÁÁ ÁÁÁÁÁ PWP § 250 4.115 W ÁÁÁÁÁÁ ÁÁÁÁÁÁ 41.15 mW/°C 2.265 W 1.646 W § This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in ground layer. For more information, refer to TI technical brief SLMA002.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions MIN MAX UNIT Input voltage, VI† 2.7 6 V Output current, IO (regulator 1) 0 500 mA Output current, IO (regulator 2) 0 250 mA Output voltage range (for adjustable option) 1.22 5.5 V Operating virtual junction temperature, TJ –40 125 °C † To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C) VI= VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 mF(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Adjustable 1.22 V ≤ VO ≤ 5.5 V, 2.7 V < V IN < 6 V, FB connected to VO VOj voltage 1.22 V ≤ VO ≤ 5.5 V, 2.7 V < V IN < 6 V, FB connected to VO 0.98 VO 1.02 VO 1 2 V Output 2.7 V < VIN < 6 V, T J = 25°C 1.2

1.2 V Output

2.7 V < VIN < 6 V 1.176 1.224 Output voltage 1 5 V Output 2.7 V < VIN < 6 V, T J = 25°C 1.5 VO Out ut voltage (see Notes 1 and 3)

1.5 V Output

2.7 V < VIN < 6 V 1.47 1.53 V() 1 8 V Output 2.8 V < VIN < 6 V, T J = 25°C 1.8 V

1.8 V Output

2.8 V < VIN < 6 V 1.764 1.836 2 5 V Output 3.5 V < VIN < 6 V, T J = 25°C 2.5

2.5 V Output

3.5 V < VIN < 6 V 2.45 2.55 3 3 V Output 4.3 V < VIN < 6 V, T J = 25°C 3.3 V3.3 V Output 4.3 V < VIN < 6 V 3.234 3.366 V Quiescent current (GND current) for regulator 1 andSee Note 3, T J = 25°C 190 mA() g regulator 2, EN = 0 V, (see Note 1) See Note 3 230 mA Output voltage line regulation (DVO /VO ) for VO + 1 V < VI ≤ 6 V, T J = 25°C, (see Note 1) 0.01% Vgg ( OO ) regulator 1 and regulator 2 (see Note 2) VO + 1 V < VI ≤ 6 V, (see Note 1) 0.1% V Load regulation for VOUT1 and VOUT2 TJ = 25°C 1 mV V Output noise voltage Regulator 1 BW = 300 Hz to 50 kHz CO =3 3mFT J =2 5°C 65 mVrmsVn Output noise voltage Regulator 2 BW = 300 Hz to 50 kHz, C O = 33 mF, TJ = 25°C mVrms Output current limit Regulator 1 VO =0V I 1.6 1.9 AOutput current limit Regulator 2 VO = 0 VI 0.750 1 A Thermal shutdown junction temperature TJ = 25°C 150 °C Regulator 1 EN = VI,T J = 25°C 1 mA II( t db ) Standby current Regulator 1 EN = VI 3 mA II(standby) Standby current Regulator 2 EN = VI,T J = 25°C 1 mARegulator 2 EN = VI 3 mA PSRR Power supply ripple rejection f = 1 kHz, CO = 33 mF, T J = 25°C, (see Note 1) 60 dB NOTES: 1. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current 1 mA. 2. If VO < 1.8 V then Vimax = 6 V, Vimin = 2.7 V: Line Regulation (mV)/C0043/C0466% /C0324V/C0467/C0032 V O /C0466V imax/C00422.7 V/C0467 100 /C00321000 If VO > 2.5 V then Vimax = 6 V, Vimin = Vo + 1 V: Line Regulation (mV)/C0043/C0466% /C0324V/C0467/C0032 V O /C0466V imax/C0042/C0466V O /C00411/C0467/C0467 100 /C00321000 3. IO = 1 mA to 500 mA for Regulator 1 and 1 mA to 250 mA for Regulator 2.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C) VI = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 mF(unless otherwise noted) (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Minimum input voltage for valid RESET I(RESET) = 300 mA, V (RESET) ≤ 0.8 V 1.0 1.3 V Trip threshold voltage VO decreasing 92% 98% VO Hysteresis voltage Measured at VO 0.5% VO RESET t(RESET ) RESET pulse duration 80 120 160 ms tr(RESET) Rising edge deglitch 30 ms Output low voltage VI = 3.5 V, I O(RESET) = 1 mA 0.15 0.4 V Leakage current V(RESET) = 6 V 1 mA Minimum input voltage for valid PG IO(PG) = 300 mA, V (PG1) ≤ 0.8 V 1.0 1.3 V Trip threshold voltage VO decreasing 92% 98% VO PG Hysteresis voltage Measured at VO 0.5% VOPG tr(PG1) Rising edge deglitch 30 ms Output low voltage VI = 2.7 V, I O(PG) = 1 mA 0.15 0.4 V Leakage current V(PG1) = 6 V 1 mA High level EN input voltage 2 V EN Low level EN input voltage 0.7 V EN Input current (EN) –1 1 mA Falling Edge deglitch Measured at VO 140 ms High level SEQ input voltage 2 V SEQ Low level SEQ input voltage 0.7 V SEQ Falling edge deglitch Measured at VO 140 ms SEQ pull up current source 6 mA High level input voltage 2 V MR1 / MR2 Low level input voltage 0.7 V MR1 / MR2 Falling edge deglitch Measured at VO 140 ms Pull up current source 6 mA V VOUT2 UV comparator – positive-going input threshold voltage of VOUT1 UV comparator 80% VO 83% V O 86% VO V V VOUT2 UV comparator – hysteresis 0.5% VO mV VOUT2 VOUT2 UV comparator – falling edge deglitchVSENSE_2 decreasing below threshold 140 ms Peak output current 2 ms pulse width 375 mA Discharge transistor current VOUT2 = 1.5 V 7.5 mA V VOUT1 UV comparator – positive-going input threshold voltage of VOUT1 UV comparator 80% VO 83% V O 86% VO V V VOUT1 UV comparator – hysteresis 0.5% VO mV V VOUT1 UV comparator – falling edge deglitchVSENSE_1 decreasing below threshold 140 ms VOUT1 Dropout voltage (see Note 4) IO = 500 mA, VIN1 = 3.2 V 170 mVD ropout voltage (see N ote 4) IO = 500 mA, V IN1 = 3.2 V 275 m V Peak output current 2 ms pulse width 750 mA Discharge transistor current VOUT1 = 1.5 V 7.5 mA VOUT1 UVLO UVLO threshold 2.4 2.65 V FB Input current – TPS70102 FB = 1.8 V 2 nA The 3.3 V regulator input voltage is to 3.2 V to perform this test.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1.198 1.197 1.196 1.195 0 0.05 0.1 0.15 1.199 1.200 1.201 0.2 0.25 0.3 IO – Output Current – A – Output Voltage – V TPS70145 OUTPUT VOLTAGE vs OUTPUT CURRENT VO VIN2 = 2.7 V TA = 25°C VOUT2 Figure 3 Figure 4 T – Temperature – °C 3.268 3.270 3.272 3.274 3.276 3.278 3.280 3.282 3.284 3.286 TPS70151 OUTPUT VOLTAGE vs TEMPERATURE – Output Voltage – VVO –40 –25 –10 5 20 35 50 65 80 95 110 125 VIN1 = 4.3 V IO = 1 mA VOUT1 Figure 5 3.270 3.272 3.274 3.276 3.278 3.280 3.282 3.284 3.286 3.288 T – Temperature – °C TPS70151 OUTPUT VOLTAGE vs TEMPERATURE – Output Voltage – VVO –40 –25 –10 5 20 35 50 65 80 95 110 125 VIN1 = 4.3 V IO = 500 mA VOUT1

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IO = 10 mA C O = 22 mF VOUT1 –60 –80 –9010 100 1 k 10 k –40 –20 –10 100 k 1 M –30 –50 –70 PSRR – Power Supply Rejection Ratio – dB f – Frequency – Hz TPS70151 POWER SUPPLY REJECTION RATIO vs FREQUENCY Figure 11 –40 –60 –70 –90 10 100 1 k 10 k –20 100 k 1 M –10 –30 –50 –80 IO = 500 mA C O = 22 mF VOUT1 PSRR – Power Supply Rejection Ratio – dB f – Frequency – Hz TPS70151 POWER SUPPLY REJECTION RATIO vs FREQUENCY Figure 12 –60 –80 –90 10 100 1 k 10 k –40 –20 –10 100 k 1 M –30 –50 –70 PSRR – Power Supply Rejection Ratio – dB f – Frequency – Hz TPS70151 POWER SUPPLY REJECTION RATIO vs FREQUENCY IO = 10 mA C O = 22 mF VOUT2 Figure 13 –40 –60 –7010 100 1 k 10 k –20 100 k 1 M –10 –30 –50 PSRR – Power Supply Rejection Ratio – dB f – Frequency – Hz TPS70151 POWER SUPPLY REJECTION RATIO vs FREQUENCY IO = 250 mA C O = 22 mF VOUT2

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

C O = 33 mF IO = 500 mA VOUT1 = 3.3 V TA = 25 C 10 100 1 k 10 k – Output Impedance – f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 100 100 k 1 M 10 M 0.1 0.01 Z O W Figure 19 C O = 33 mF IO = 10 mA VOUT1 = 3.3 V TA = 25 C 10 100 1 k 10 k – Output Impedance – f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 100 100 k 1 M 10 M 0.1 0.01 Z O W Figure 20 C O = 33 mF IO = 250 mA VOUT2 = 1.8 V TA = 25 C 10 100 1 k 10 k – Output Impedance – f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 100 100 k 1 M 10 M 0.1 0.01 Z O W Figure 21 C O = 33 mF IO = 10 mA VOUT2 = 1.8 V TA = 25 C 10 100 1 k 10 k – Output Impedance – f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 100 100 k 1 M 10 M 0.1 0.01 Z O W

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– Output Current – mA VO – Change inD Output Voltage – mV IO t – Time – ms C O = 33 mF TA = 25°C VOUT1 = 3.3 V –20 500 Figure 27 LOAD TRANSIENT RESPONSE – Output Current – mA VO – Change inD Output Voltage – mV IO t – Time – ms 250 –20 C O = 33 mF TA = 25°C VOUT2 = 1.8 V Figure 28 0 20 40 60 80 100 120 5.3 LINE TRANSIENT RESPONSE (V OUT1 ) 4.3 140 160 180 200 – Input Voltage – VVI t – Time – ms IO = 500 mA C O = 33 mF VOUT1 –50 VO – Change inD Output Voltage – mV Figure 29 0 20 40 60 80 100 120 LINE TRANSIENT RESPONSE (V OUT2 ) 2.8 140 160 180 200 – Input Voltage – VVI t – Time – ms IO = 250 mA C O = 33 mF VOUT2 VO – Change inD Output Voltage – mV –10 3.8

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IO – Output Current – mA VO = 3.3 V C O = 10 mF TA = 25°C TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE † vs OUTPUT CURRENT ESR – Equivalent Series Resistance –W REGION OF INSTABILITY Figure 34 0 100 200 300 400 500 IO – Output Current – mA VO = 3.3 V C O = 6.8 mF TA = 25°C TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE † vs OUTPUT CURRENT ESR – Equivalent Series Resistance –W REGION OF INSTABILITY 250 mW Figure 35 0 50 100 150 200 250 IO – Output Current – mA VO = 1.8 V C O = 10 mF TA = 25°C TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE † vs OUTPUT CURRENT ESR – Equivalent Series Resistance –W REGION OF INSTABILITY Figure 36 0 50 100 150 200 250 IO – Output Current – mA VO = 1.8 V C O = 6.8 mF TA = 25°C TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE † vs OUTPUT CURRENT ESR – Equivalent Series Resistance –W REGION OF INSTABILITY 250 mW † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO .

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal the device will be in shutdown mode. When the EN goes to voltage low, then the device will be enabled. sequence The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2 ) will be turned on first. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 will turn on first and VOUT1 will remain off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time the VOUT1 will be turned on. If VOUT2 is pulled below 83% (i.e., over load condition) VOUT1 will be turned off. For a detailed timing diagram, refer to Figures 37 – 43. These terminals have a 6-mA pullup current to VIN1. Pulling the SEQ terminal low reverses the power-up order and VOUT1 will be turned on first. For detail timing diagram refer to Figures 37 and 42. power–good The PG1 is an open drain, active high output terminal which indicates the status of the VOUT1 regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedance state when it is pulled below 95% (i.e. over load condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pullup resistor manual reset pins (MR1 and MR2) MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) will occur. These terminals have a 6-mA pullup current to VIN1. sense (VSENSE1 , VSENSE2 ) The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the V SENSE terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate. FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. it is essential to route them in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and V OUT terminals to filter noise is not recommended because it can cause the regulators to oscillate. RESET indicator The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET can be used to drive power-on reset circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the VOUT2 regulator and both manual reset pins (MR1 and MR2). When VOUT2 exceeds to 95% of it’s regulated voltage, and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120-ms delay. RESET will go to a low impedance state when VOUT2 is pulled below 95% (i.e. over load condition) of it’s regulated voltage. To monitor VOUT1 , PG1 output pin can be connected to MR1 or MR2. The open drain output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating. VIN1 and VIN2 VIN1 and VIN2 are input to the regulators. Internal bias voltages are powered by VIN1.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VOUT1 and VOUT2 are output terminals of the LDO. The TPS701xx low dropout regulator family provides dual regulated output voltages for DSP applications, which require high performance power management solution. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This reduces the component cost and board space while increasing total system reliability. TPS701xx family has an enable feature which puts the device in sleep mode reducing the input currents to less than 3 mA. Other features are integrated SVS (Power On Reset, RESET ) and Power Good (PG1) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete DSP power solution. The TPS701xx, unlike many other LDOs, feature very low quiescent current which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (I B = IC /b). The TPS701xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the full load range.

(Fixed Output Option) VIN VOUT1 MR1 0.1 mF RESET 10 mF 10 mF 0.1 mF MR2 EN >2 V <0.7 V TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 The following figures provide a timing diagram of how this device functions in different configurations. and VIN2 are tied to same input voltage, the SEQ pin is tied to logic low and the device is toggled with enable (EN) function. When the device is enabled (EN is pulled low) VOUT1 will turn on first and VOUT2 will remain off until VOUT1 reaches to approximately 83% of its regulated output voltage. At that time VOUT2 will be turned on. When VOUT1 reaches to 95% of its regulated output the PG1 will turn on (active high). Since MR2 is connected to PG1 for this application, it will follow the logic of PG1. When V OUT2 reaches to 95% of its regulated voltage, RESET will switch to high voltage level after 120 ms delay (see Figure 37). 83% 95% t1 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQ 95% 83% Figure 37. Timing When SEQ = Low

0.1 mF 10 mF 10 mF 0.1 mF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

and VIN2 are tied to same input voltage, the SEQ pin is tied to logic high and the device is toggled with enable (EN) function. When the device is enabled (EN is pulled low), VOUT2 will begin to power up and when it reaches to 83% of its regulated voltage, VOUT1 will begin to power up. PG1 will turn on when VOUT1 reaches 95% of its regulated voltage, and since MR2 and PG1 is tied together, MR2 will follow the logic of the PG1 output. When VOUT1 reaches 95% of its regulated voltage, RESET will switch to high voltage level after 120 ms delay (see Figure 38). 83% 95% 83% 95% t1 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQ Figure 38. Timing When SEQ = High

0.1 mF 10 mF 10 mF 0.1 mF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

and VIN2 are tied to same input voltage, the SEQ pin is tied to logic high and VOUT1 faults out. VOUT2 will begin to power up when device is enabled (EN is pulled low). When VOUT2 reaches 83% of its regulated voltage, then VOUT1 will begin to power up. When V OUT1 reaches 95% of its regulated voltage, the PG1 will turn on and RESET will switch to high voltage level after 120 ms delay. When V OUT1 faults out, VOUT2 remains powered on. PG1 is tied to MR2 and they change state to logic low. RESET will be driven by VOUT1 . (see Figure 40). 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQUENCE t1 – Vout1 and Vout2 are greater than the PG thresholds and MR1 is logic high. 95% 83% 83% 95% Vout1 faults out Figure 40. Timing When VOUT1 Faults Out

0.1 mF 10 mF 10 mF 0.1 mF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 and VIN2 are tied to same input voltage, the SEQ is tied to logic high, device is enabled, and VOUT2 faults out. When VOUT2 faults out. VOUT2 will begin to power up when device is enabled (EN is pulled low). When V OUT2 reaches 95% of its regulated voltage, then VOUT1 will begin to power up. When VOUT1 reaches 95% of its regulated voltage, PG1 will turn on and RESET will switch to high voltage level after 120 ms delay. When VOUT2 faults out, VOUT1 will be powered down. PG1 is tied to MR2 and they change state to logic low. RESET will be driven by VOUT2 .(see Figure 41). 83% 95% 83% 95% 120ms ENABLE VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQUENCE t1 – Vout1 and Vout2 are greater than the PG thresholds and MR1 is logic high. Vout2 faults out Figure 41. Timing When VOUT2 Faults Out

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

split voltage DSP application Figure 42 shows a typical application where the TPS70151 is powering up a DSP. In this application by grounding the SEQ pin, VOUT1 (I/O) will be powered up first, and then VOUT2 (core). 1.8 V VIN1 VIN2 EN SEQ VOUT1 VSENSE1 PG1 MR2 RESET MR1 VSENSE2 VOUT2 TPS70151 PWP 5 V 0.1 mF RESET 10 mF 10 mF 0.1 mF DSP MR2 PG1 EN 250 kW >2 V <0.7 V 250 kW >2 V <0.7 V >2 V <0.7 V 83% 95% 120ms EN VOUT2 (Core) PG1 RESET SEQ 95% 83% VOUT1 (I/O) Figure 42. Application Timing Diagram (SEQ = Low)

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 split voltage DSP application Figure 43 shows a typical application where the TPS70151 is powering up a DSP. In this application by pulling up the SEQ pin, VOUT2 (Core) will be powered up first, and then VOUT1 (I/O). VIN1 VIN2 EN SEQ VOUT1 VSENSE1 PG1 MR2 RESET MR1 VSENSE2 VOUT2 TPS70151 PWP 5 V 0.1 mF 0.1 mF 1.8 V EN>2 V <0.7 V 250 kW 83% 95% 83% 95% t1120ms EN VOUT2 (Core) VOUT1 (I/O) PG1 RESET SEQ Figure 43. Application Timing Diagram (SEQ = High)

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

For a typical application, an input bypass capacitor (0.1 mF – 1 mF) is recommended. This capacitor will filter any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependant on the output current and response time of the main power supply, as well as the distance to the load (LDO). output capacitor As with most LDO regulators, the TPS701xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 mF and the ESR (equivalent series resistance) must be between 50 mW and 2.5 W . Capacitor values 10 mF or larger are acceptable, provided the ESR is less than 2.5 W . Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Below is a partial listing of surface-mount capacitors usable with the TPS701xx. for fast transient response application. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. VALUE MFR. MAX ESR † PART NO. 22 mF Kemet 345 m W 7495C226K0010AS 33 mF Sanyo 100 m W 10TPA33M 47 mF Sanyo 100 m W 6TPA47M 68 mF Sanyo 45 m W 10TPC68M ESR and transient response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 44. R ESR LESL C Figure 44. – ESR and ESL focuses mainly on the parasitic resistance ESR.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. ESR 1 ESR 2 ESR 3 t1 t2 IO VO Figure 46. – Correlation of Different ESRs and Their Influence to the Regulation of VO at a

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 programming the TPS70102 adjustable LDO regulator The output voltage of the TPS70102 adjustable regulators are programmed using external resistor dividers as shown in Figure 47. Resistors R1 and R2 should be chosen for approximately 50 mA divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kW to set the divider current at approximately 50 mA and then calculate R1 using: R1 /C0043/C0466 V O V ref /C00421/C0467/C0032R2 Where: Vref = 1.224 V typ (the internal reference voltage) OUTPUT VOLTAGE PROGRAMMING GUIDE VO VI OUT FB GND EN IN <0.7V >2.0 V TPS70102 0.1 mF OUTPUT VOLTAGE R1 R2 2.5 V 3.3 V 3.6 V UNIT 33.5 53.6 61.9 30.1 30.1 30.1 kW kW kW Figure 47. TPS70102 Adjustable LDO Regulator Programming

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, P D(max), and the actual dissipation, PD , which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P D(max) /C0043 TJmax /C0042TA R /C0113JA Where: TJmax is the maximum allowable junction temperature. TA is the ambient temperature. R qJA is the thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal PWP with no airflow. The regulator dissipation is calculated using: P D /C0043/C0466V I/C0042V O /C0467/C0032IO Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit.

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS SLVS222A – DECEMBER 1999 – REVISED MARCH 2000 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PWP (R-PDSO-G) PowerPAD  PLASTIC SMALL-OUTLINE PACKAGE 4073225/E 03/97 0,50 0,75 0,25 0,15 NOM Thermal Pad (See Note D) Gage Plane 2824 7,70 7,90 6,40 6,60 9,60 9,80 6,60 6,20 0,19 4,50 4,30 0,15 A 0,30 1,20 MAX 1614 5,10 4,90 PINS 4,90 5,10 DIM A MIN A MAX 0,05 Seating Plane 0,65 0,10 M0,10 0°–8° 20-PIN SHOWN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated.

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  2000, Texas Instruments Incorporated