TPS70148PWPG4

Dual-Output Low-Dropout Vltg Reg with Pwr Up Sequencing For Split Vo (Rev. I)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SLVS222,I]
PDF pages: 42

Technical content

(TOP VIEW) NC VIN1 VIN1 MR1 MR2 EN SEQ GND VIN2 VIN2 NC VOUT1 VOUT1 VSENSE1 /FB1 PG1 RESET VSENSE2 /FB2 VOUT2 VOUT2 NC TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 Dual-OutputLowDropoutVoltageRegulators withPower-UpSequencingforSplit-VoltageDSPSystems Check forSamples: TPS70145 ,TPS70148 ,TPS70151 ,TPS70158 ,TPS70102 1FEATURES DESCRIPTION 23• Dual Output VoltagesforSplit-Supply TPS701xx familydevicesare designedto providea Applications complete power management solutionfor the TMS320 ™ DSP family,processor power, ASIC,• SelectablePower-Up Sequencing forDSP FPGA, and digitalapplicationswhere dual outputApplications voltageregulatorsarerequired.Easy programmability• Output CurrentRange of500mA on Regulator of the sequencing functionmakes the TPS701xx1 and 250mA on Regulator2 familyidealforany TMS320 DSP applicationswith

FastTransientResponse power sequencing requirements. Differentiated The TPS701xx familyofvoltageregulatorsoffervery• Open DrainPower-On Reset with120ms Delay low dropoutvoltageand dualoutputswithpower-up• Open DrainPower Good forRegulator1 sequence control,which is designed primarilyfor
UltraLow 190mA (typ)QuiescentCurrent DSP applications.These deviceshave extremelylow noise outputperformancewithoutusing any added• 1mA InputCurrentDuring Standby filterbypass capacitorsand are designedto have a• Low Noise:65mVRMS WithoutBypass Capacitor fasttransientresponseand be stablewith10mF low
Quick Output CapacitorDischargeFeature ESR capacitors.
Two Manual Reset Inputs These devices have fixed 3.3V/2.5V,3.3V/1.8V,
2% Accuracy Over Load and Temperature 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltageoptions.Regulator1 can support up to• UndervoltageLockout (UVLO) Feature 500mA, and regulator2 can supportup to 250mA.• 20-PinPowerPAD ™ TSSOP Package Separate voltage inputs allow the designer to
Thermal Shutdown Protection configurethesourcepower. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerPAD, TMS320 aretrademarksofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

1.8 V VIN1 VIN2 EN SEQ VOUT1 VSENSE1 PG1 MR2 RESET MR1 VSENSE2 VOUT2 TPS70151 PWP 5 V

3.3 V I/O

0.1 µF RESET 10 µF 10 µF 0.1 µF DSP MR2 PG1 EN 250 kΩ >2 V <0.7 V 250 kΩ >2 V <0.7 V >2 V <0.7 V TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com Because thePMOS devicebehaves as a low-valueresistor,thedropoutvoltageisverylow (typically170mV on regulator1) and isdirectlyproportionalto the outputcurrent.Additionally,sincethe PMOS pass elementisa voltage-drivendevice,thequiescentcurrentisverylow and independentofoutputloading(maximum of230mA overthefullrangeofoutputcurrent).ThisLDO familyalsofeaturesa sleepmode; applyinga highsignaltoEN (enable)shutsdown bothregulators,reducingtheinputcurrentto1mA atTJ = +25°C. The deviceisenabledwhen theEN pinisconnectedtoa low-levelinputvoltage.The outputvoltagesofthetwo regulatorsaresensed attheVSENSE1 and VSENSE2 pins,respectively. The inputsignalat the SEQ pin controlsthe power-up sequence of the two regulators.When the deviceis enabledand theSEQ terminalispulledhighorleftopen,VOUT2 turnson firstand VOUT1 remainsoffuntilVOUT2 reachesapproximately83% of itsregulatedoutputvoltage.At thattimeVOUT1 isturnedon. IfVOUT2 ispulled below 83% (forexample,an overloadcondition),VOUT1 isturnedoff.PullingtheSEQ terminallow reversesthe power-uporderand VOUT1 isturnedon first.The SEQ pinisconnectedtoan internalpull-upcurrentsource. For each regulator,thereisan internaldischargetransistortodischargetheoutputcapacitorwhen theregulator isturnedoff(disabled). The PG1 pinreportsthevoltageconditionsatVOUT1 ,which can be used toimplementan SVS forthecircuitry suppliedby regulator1. The TPS701xx featuresa RESET (SVS, POR, or Power-On Reset).RESET outputinitiatesa resetin DSP systemsand relateddigitalapplicationsintheeventofan undervoltagecondition.RESET indicatesthestatusof VOUT2 and bothmanual resetpins(MR1 and MR2). When VOUT2 reaches95% ofitsregulatedvoltageand MR1 and MR2 areinthelogichighstate,RESET goes toa highimpedance stateaftera 120ms delay.RESET goes tothelogiclow statewhen theVOUT2 regulatedoutputvoltageispulledbelow 95% (forexample,an overload condition)ofitsregulatedvoltage.To monitorVOUT1 ,thePG1 outputpincan be connectedtoMR1 orMR2. The devicehas an undervoltagelockout(UVLO) circuitthatpreventstheinternalregulatorsfromturningon until VIN1 reaches2.5V.

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TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) VOLTAGE (V)(2) PACKAGE- SPECIFIED LEAD TEMPERATURE ORDERING TRANSPORT PRODUCT VOUT1 VOUT2 (DESIGNATOR) RANGE (TJ) NUMBER MEDIA, QUANTITY TPS70102PWP Tube,70 TPS70102 Adjustable Adjustable HTSSOP-20 (PWP) -40°C to+125°C TPS70102PWPR Tape and Reel,2000 TPS70145PWP Tube,70 TPS70145 3.3V 1.2V HTSSOP-20 (PWP) -40°C to+125°C TPS70145PWPR Tape and Reel,2000 TPS70148PWP Tube,70 TPS70148 3.3V 1.5V HTSSOP-20 (PWP) -40°C to+125°C TPS70148PWPR Tape and Reel,2000 TPS70151PWP Tube,70 TPS70151 3.3V 1.8V HTSSOP-20 (PWP) -40°C to+125°C TPS70151PWPR Tape and Reel,2000 TPS70158PWP Tube,70 TPS70158 3.3V 2.5V HTSSOP-20 (PWP) -40°C to+125°C TPS70158PWPR Tape and Reel,2000 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum locatedattheend ofthisdocument,orsee theTIweb siteatwww.ti.com. (2) Forfixed1.20Voperation,tieFB toOUT. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange(unlessotherwisenoted). TPS701xx UNIT Inputvoltagerange:VIN1,VIN2 (2) –0.3to+7 V VoltagerangeatEN –0.3to+7 V Outputvoltagerange(VOUT1 ,VSENSE1 ) 5.5 V Outputvoltagerange(VOUT2 ,VSENSE2 ) 5.5 V Maximum RESET, PG1 voltage 7 V Maximum MR1, MR2, and SEQ voltage VIN1 V Peak outputcurrent Internallylimited — Continuoustotalpower dissipation See ThermalInformationTable — Junctiontemperaturerange,TJ –40 to+150 °C Storagetemperaturerange,Tstg –65 to+150 °C ESD rating,HBM 2 kV (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Allvoltagesaretiedtonetworkground. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

LineReg. (mV)/C0043(% /C0324V) /C0032V O /C0466V Imax/C00422.7V/C0467 100 /C00321000 LineReg. (mV)/C0043(% /C0324V) /C0032V O /C0466V Imax/C0042/C0466V O /C00411V/C0467/C0467 100 /C00321000 (3) IfVO < 1.8VthenVImax = 6V,VImin= 2.7V: IfVO > 2.5VthenVImax = 6V,VImin= VO + 1V: TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com THERMAL INFORMATION TPS701xx THERMAL METRIC (1)(2) UNITS PWP (20PINS) qJA Junction-to-ambientthermalresistance 74.1 qJCtop Junction-to-case(top)thermalresistance 43.1 qJB Junction-to-boardthermalresistance 19.7 °C/W yJT Junction-to-topcharacterizationparameter 2.9 yJB Junction-to-boardcharacterizationparameter 17.3 qJCbot Junction-to-case(bottom)thermalresistance 1.4 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) Forthermalestimatesofthisdevicebased on PCB copperarea,see theTIPCB ThermalCalculator. RECOMMENDED OPERATING CONDITIONS Over operatingtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Inputvoltage,VI (1)(regulator1 and 2) 2.7 6 V Outputcurrent,IO (regulator1) 0 500 mA Outputcurrent,IO (regulator2) 0 250 mA Outputvoltagerange(foradjustableoption) 1.22 5.5 V Operatingjunctiontemperature,TJ –40 +125 °C (1) To calculatetheminimum inputvoltageformaximum outputcurrent,use thefollowingequation:VI(min)= VO(max) + VDO(max load).

ELECTRICAL CHARACTERISTICS

Over recommended operatingjunctiontemperaturerange(TJ = –40°C to+125°C),VIN1 orVIN2 = VOUT(nom) + 1V,IO = 1mA, EN = 0V,C O = 33mF,(unlessotherwisenoted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference 2.7V< VI< 6V, FB connectedtoVO 1.22voltage TJ = +25°C 2.7V< VI< 6V, FB connectedtoVO 1.196 1.244 1.2VOutput 2.7V< VI< 6V, TJ = +25°C 1.2 2.7V< VI< 6V, 1.176 1.224 1.5VOutput 2.7V< VI< 6V, TJ = +25°C 1.5Output 2.7V< VI< 6V, 1.47 1.53VO voltage(1), V (2) 1.8VOutput 2.7V< VI< 6V, TJ = +25°C 1.8 2.7V< VI< 6V, 1.764 1.836 2.5VOutput 2.7V< VI< 6V, TJ = +25°C 2.5 3.3VOutput 2.7V< VI< 6V, TJ = +25°C 3.3 2.7V< VI< 6V, 3.234 3.366 (2) TJ = +25°C 190Quiescentcurrent(GND current)for mAregulator1 and regulator2,EN = 0V (1) (2) 230 VO + 1V < VI≤ 6V, TJ = +25°C (1) 0.01%Outputvoltagelineregulation(∆VO /VO ) Vforregulator1 and regulator2 (3) Load regulationforVOUT 1 and VOUT2 TJ = +25°C (2) 1 mV (1) Minimum inputoperatingvoltageis2.7VorVO(typ)+ 1V,whicheverisgreater.Maximum inputvoltage= 6V,minimum output current= 1mA. (2) IO = 1mA to250mA forRegulator1 and 1mA to125mA forRegulator2.

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TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingjunctiontemperaturerange(TJ = –40°C to+125°C),VIN1 orVIN2 = VOUT(nom) + 1V,IO = 1mA, EN = 0V,C O = 33mF,(unlessotherwisenoted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Regulator1 65OutputnoiseVn BW 300Hz to50kHz, C O = 33mF,TJ = +25°C mVRMSvoltage Regulator2 65 Regulator1 1.6 1.9 Outputcurrentlimit VOUT = 0V A Regulator2 0.750 1 Thermalshutdownjunctiontemperature +150 °C EN = VI, TJ = +25°C 1 Regulator1 mA EN = VI 3II Standby (standby)current EN = VI, TJ = +25°C 1 Regulator2 mA EN = VI 3 Power-supplyripple f= 1kHz,C O = 33mF, TJ = +25°C (1) dBPSRR 60rejection RESET Terminal Minimum inputvoltageforvalidRESET IRESET = 300mA, V(RESET) ≤ 0.8V 1.0 1.3 V Tripthresholdvoltage VO decreasing 92% 95% 98% VOUT Hysteresisvoltage Measured atVO 0.5% VOUT t(RESET) RESET pulseduration 80 120 160 ms tr (RESET) Risingedge deglitch 30 ms Outputlowvoltage VI= 3.5V, IO(RESET) = 1mA 0.15 0.4 V Leakage current V(RESET) = 6V 1 mA PG1 Terminal Minimum inputvoltageforvalidPG1 I(PG1) = 300mA, V(PG1) ≤ 0.8V 1.0 1.3 V Tripthresholdvoltage VO decreasing 92% 95% 98% VOUT Hysteresisvoltage Measured atVO 0.5% VOUT tr(PG1) Risingedge deglitch 30 ms Outputlowvoltage VI= 2.7V, IO(PG1) = 1mA 0.15 0.4 V Leakage current V(PG1) = 6V 1 mA EN Terminal HighlevelEN inputvoltage 2 V Low levelEN inputvoltage 0.7 V Inputcurrent(EN) –1 1 mA Fallingedge deglitch Measured atVO 140 ms SEQ Terminal HighlevelSEQ inputvoltage 2 V Low levelSEQ inputvoltage 0.7 V SEQ pull-upcurrentsource 6 mA MR1 /MR2 Terminals Highlevelinputvoltage 2 V Low levelinputvoltage 0.7 V Pull-upcurrentsource 6 mA VOUT2 Terminal VOUT2 UV comparator:Positive-going inputthresholdvoltageofVOUT2 UV 80% VO 83% VO 86% VO V comparator VOUT2 UV comparator:Hysteresis 0.5% VO mV VOUT2 UV comparator:Fallingedge VSENSE_2 decreasingbelowthreshold 140 msdeglitch Peak outputcurrent 2ms pulsewidth 375 mA Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operatingjunctiontemperaturerange(TJ = –40°C to+125°C),VIN1 orVIN2 = VOUT(nom) + 1V,IO = 1mA, EN = 0V,C O = 33mF,(unlessotherwisenoted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dischargetransistorcurrent VOUT2 = 1.5V 7.5 mA VOUT1 Terminal VOUT1 UV comparator:Positive-going inputthresholdvoltageofVOUT1 UV 80% VO 83% VO 86% VO V comparator VOUT1 UV comparator:Hysteresis 0.5% VO mV VOUT1 UV comparator:Fallingedge VSENSE_1 decreasingbelowthreshold 140 msdeglitch VOUT1 Terminal,continued Dropoutvoltage(4) IO = 500mA, TJ = +25°C VIN1 = 3.2V 170 mV Dropoutvoltage(4) IO = 500mA, VIN1 = 3.2V 275 mV Peak outputcurrent(4) 2ms pulsewidth 750 mA Dischargetransistorcurrent VOUT1 = 1.5V 7.5 mA VIN1 UVLO threshold 2.4 2.65 V FB Terminal Inputcurrent:TPS70102 FB = 1.8V 1 mA The 3.3Vregulatorinputissetto3.2Vtoperformthistest.

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/c45 /c45 /c45 /c45 Thermal Shutdown 2.5□V +/c45 Current Sense Reference Vref Vref ENA_1 FB1 ENA_1 120ms Delay0.95□x□Vref FB2 Current Sense +/c45 ENA_2 ENA_2 Vref VIN1 (2□Pins) GND EN VIN2 (2□Pins) SEQ (see□Note□B) PG1 MR2 RESET VIN1 MR1 VIN1 Rising□Edge Deglitch Reset Comp VOUT2 (2□Pins) Falling□Edge Deglitch0.83 x Vref FB2 V UV□CompOUT2 Falling□Edge Deglitch0.83 x Vref FB1 V UV□CompOUT1 Power Sequence Logic ENA_1 ENA_2 VIN1 10□k/c87 VSENSE1 (see□Note□A) V (2□Pins)OUT1 VSENSE2 (see□Note□A) 10□k/c87 0.95□x□Vref FB1 Rising□Edge Deglitch PG Comp /c45 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 DEVICE INFORMATION FixedVoltageVersion A. For most applications,VSENSE1 and VSENSE2 shouldbe externallyconnectedto VOUT as closeas possibleto the device.For otherimplementations,referto SENSE terminalconnectiondiscussioninthe ApplicationInformation section. B. IftheSEQ terminalisfloatingattheinput,VOUT2 powers up first. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

/c45 /c45 /c45 /c45 Thermal Shutdown 2.5□V +/c45 Current Sense Reference Vref Vref ENA_1 ENA_1 120ms Delay 0.95□x□Vref FB1 0.95□x□Vref FB2 Rising□Edge Deglitch Current Sense +/c45 ENA_2 ENA_2 Vref VIN1 (2□Pins) GND EN VIN2 (2□Pins) SEQ (see□Note□B) FB1 (see□Note□A) PG1 MR2 RESET FB2 (see□Note□A) VIN1 MR1 VIN1 PG CompRising□Edge Deglitch Reset Comp VOUT1 (2□Pins) VOUT2 (2□Pins) /c45 Falling□Edge Deglitch0.83 x Vref FB2 V UV□CompOUT2 Falling□Edge Deglitch0.83 x Vref FB1 V UV□CompOUT1 Power Sequence Logic ENA_1 ENA_2 VIN1 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com AdjustableVoltageVersion A. For most applications,FB1 and FB2 shouldbe externallyconnectedtoresistordividersas closeas possibletothe device.For otherimplementations,referto FB terminalsconnectiondiscussionin the ApplicationInformation section. B. IftheSEQ terminalisfloatingattheinput,VOUT2 powers up first

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NOTES: A. V RES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. Î Î Î Î Î Î Î Î Î Î Î Î VIN2 VRES (see Note A) VRES t t t VOUT2 Threshold Voltage RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined VIT+(see Note B) VIT− (see Note B) VIT+(see Note B) B. V IT −Trip voltage is typically 5% lower than the output voltage (95%VO ) VIT− to VIT+ is the hysteresis voltage. VIT− (see Note B) NOTES: A. V PG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ VPG1 t t t Threshold Voltage PG1 Output Output Undefined Output Undefined VIT+(see Note B)VIT+(see Note B) B. V IT −Trip voltage is typically 5% lower than the output voltage (95%VO ) VIT− to VIT+ is the hysteresis voltage. VIN1 VOUT2 VPG1 (see Note A) VIT− (see Note B) VIT− (see Note B) VUVLO VUVLO TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 RESET Timing Diagram (withVIN1 Powered Up) PG1 Timing Diagram Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com Table1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. EN 6 I Activelowenable GND 8 — Ground MR1 4 I Manual resetinput1,activelow,pulledup internally MR2 5 I Manual resetinput2,activelow,pulledup internally NC 1,11,20 — No connection Open drainoutput,lowwhen VOUT1 voltageislessthan95% ofthenominalregulatedPG1 16 O voltage RESET 15 O Open drainoutput,SVS (power-onreset)signal,activelow Power-upsequence control:SEQ = High,VOUT2 powers up first;SEQ 7 I SEQ = Low, VOUT1 powers up first,SEQ terminalpulledup internally. VIN1 2,3 I Inputvoltageofregulator1 VIN2 9,10 I Inputvoltageofregulator2 VOUT1 18,19 O Outputvoltageofregulator1 VOUT2 12,13 O Outputvoltageofregulator2 VSENSE2 /FB2 14 I Regulator2 outputvoltagesense/regulator2 feedbackforadjustable VSENSE1 /FB1 17 I Regulator1 outputvoltagesense/regulator1 feedbackforadjustable DetailedDescription The TPS701xx low dropoutregulatorfamilyprovidesdualregulatedoutputvoltagesforDSP applicationsthat requirehigh-performancepower management solutions.These devicesprovidefasttransientresponseand high accuracywithsmalloutputcapacitors,whiledrawinglow quiescentcurrent.Programmable sequencingprovides a power solutionfor DSPs withoutany externalcomponent requirements.This architecturereduces the component costand board space whileincreasingtotalsystem reliability.The TPS701xx familyhas an enable featurethatputsthe deviceinsleepmode reducingthe inputcurrentsto lessthan 3mA. Other featuresare integratedSVS (Power-On Reset,RESET) and Power Good (PG1) thatmonitoroutputvoltagesand provide logicoutputtothesystem.These differentiatedfeaturesprovidea completeDSP power solution. The TPS701xx, unlikemany otherLDOs, featureverylow quiescentcurrentthatremainsvirtuallyconstanteven withvaryingloads.ConventionalLDO regulatorsuse a pnp pass element,thebase currentofwhich isdirectly proportionaltotheloadcurrentthroughtheregulator(IB = IC /b).The TPS701xx uses a PMOS transistortopass current;because thegateofthePMOS isvoltage=driven,operatingcurrentislow and stableoverthefullload range. Pin Functions Enable The EN terminalisan inputthatenablesorshutsdown thedevice.IfEN isata voltagehighsignal,thedeviceis inshutdownmode. When EN goes tovoltagelow,thedeviceisenabled. Sequence The SEQ terminalisan inputthatprograms which outputvoltage(VOUT1 or VOUT2 ) isturnedon first.When the deviceisenabledand theSEQ terminalispulledhighorleftopen,VOUT2 turnson firstand VOUT1 remainsoffuntil VOUT2 reachesapproximately83% of itsregulatedoutputvoltage.At thattime,VOUT1 isturnedon. IfVOUT2 is pulledbelow 83% (forexample,inan overloadcondition)VOUT1 isturnedoff.These terminalshave a 6-mA pullup currenttoVIN1. Pullingthe SEQ terminallow reversesthe power-up orderand VOUT1 isturnedon first.For detailedtiming diagrams,refertoFigure40 throughFigure44.

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TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 Power-Good The PG1 isan open drain,activehighoutputterminalthatindicatesthestatusoftheVOUT1 regulator.When the VOUT1 reaches95% ofitsregulatedvoltage,PG1 willgo toa highimpedance state.Itwillgo toa low impedance statewhen itispulledbelow 95% (forexample,duringan overloadcondition)ofitsregulatedvoltage.The open drainoutputofthePG1 terminalrequiresa pull-upresistor. Manual Reset Pins (MR1 and MR2) MR1 and MR2 areactivelow inputterminalsused totriggera resetcondition.When eitherMR1 orMR2 ispulled tologiclow,a POR (RESET) willoccur.These terminalshave a 6mA pull-upcurrenttoVIN1. Sense (VSENSE1 ,VSENSE2 ) The sense terminalsof fixed-outputoptionsmust be connectedto the regulatoroutput,and the connection shouldbe as shortas possible.Internally,sense connectstohigh-impedance,wide-bandwidthamplifiersthrough a resistor-dividernetworkand noisepickupfeedsthroughto the regulatoroutput.Itisessentialto routethe sense connectioninsuch a way to minimizeor avoidnoisepickup.Adding RC networksbetween the VSENSE terminalsand VOUT terminalsto filternoise is not recommended because these networks can cause the regulatorstooscillate. FB1 and FB2 FB1 and FB2 are inputterminalsused foradjustable-outputdevicesand must be connectedto the external feedbackresistordivider.FB1 and FB2 connectionsshouldbe as shortas possible.Itisessentialtoroutethem insuch a way as tominimizeor avoidnoisepickup.Adding RC networksbetween theFB terminalsand VOUT terminalstofilternoiseisnotrecommended because thesenetworkscause theregulatorstooscillate. RESET Indicator The TPS701xx featuresa RESET (SVS, POR, orPower-On Reset).RESET can be used todrivepower-onreset circuitryor a low-batteryindicator.RESET isan activelow,open drainoutputthatindicatesthe statusof the VOUT2 regulatorand bothmanual resetpins(MR1 and MR2). When VOUT2 exceeds 95% ofitsregulatedvoltage, and MR1 and MR2 areinthehighimpedance state,RESET willgo toa high-impedancestateafter120ms delay. RESET willgo toa low-impedancestatewhen VOUT2 ispulledbelow 95% (forexample,an overloadcondition)of itsregulatedvoltage.To monitorVOUT1 ,thePG1 outputpincan be connectedtoMR1 orMR2. The open drain outputoftheRESET terminalrequiresa pullupresistor.IfRESET isnotused,itcan be leftfloating. VIN1 and VIN2 VIN1 and VIN2 areinputtotheregulators.Internalbiasvoltagesarepowered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 areoutputterminalsoftheLDO. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

IO − Output Current − A 3.296 3.295 3.293 3.292 0 0.1 0.2 0.3 − Output Voltage − V 3.298 3.299 3.300 0.4 0.5 0.6 3.297 3.294 VO VIN1 = 4.3 V TA = 25°C VOUT1 1.799 1.797 1.796 1.795 0 0.05 0.1 0.15 1.800 1.801 1.802 0.2 0.25 0.3 1.798 IO − Output Current − A − Output Voltage − VVO VIN2 = 2.8V TA = 25°C VOUT2 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS Table2.TableofGraphs FIGURE vs Outputcurrent Figure1 toFigure3 VO Outputvoltage vs Temperature Figure4 toFigure7 Ground current vs Junctiontemperature Figure8 PSRR Power-supplyrejectionratio vs Frequency Figure9 toFigure12 Outputspectralnoisedensity vs Frequency Figure13 toFigure16 ZO Outputimpedance vs Frequency Figure17 toFigure20 vs Temperature Figure21 and Figure22 Dropoutvoltage vs Inputvoltage Figure23 and Figure24 Load transientresponse Figure25 and Figure26 Linetransientresponse Figure27 and Figure28 VO Outputvoltageand enablevoltage vs Time (start-up) Figure29 and Figure30 Equivalentseriesresistance vs Outputcurrent Figure31 toFigure38 Testcircuitfortypicalregionsofstability(equivalentseriesresistance)performance Figure39 TPS70151 TPS70151 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT Figure1. Figure2.

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T − Temperature − °C 3.268 3.270 3.272 3.274 3.276 3.278 3.280 3.282 3.284 3.286 − Output Voltage − VVO −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN1 = 4.3 V IO = 1 mA VOUT1 1.198 1.197 1.196 1.195 0 0.05 0.1 0.15 1.199 1.200 1.201 0.2 0.25 0.3 IO − Output Current − A − Output Voltage − VVO VIN2 = 2.7 V TA = 25°C VOUT2 3.270 3.272 3.274 3.276 3.278 3.280 3.282 3.284 3.286 3.288 T − Temperature − °C − Output Voltage − VVO −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN1 = 4.3 V IO = 500 mA VOUT1 1.786 1.788 1.790 1.792 1.794 1.796 1.798 1.800 T − Temperature − °C − Output Voltage − VVO −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN2 = 2.8 V IO = 1 mA VOUT2 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 TPS70145 TPS70151 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs OUTPUT CURRENT TEMPERATURE Figure3. Figure4. TPS70151 TPS70151 OUTPUT VOLTAGE OUTPUT VOLTAGE vs vs TEMPERATURE TEMPERATURE Figure5. Figure6. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

1.790 1.791 1.792 1.793 1.794 1.795 1.796 1.797 1.798 1.799 T − Temperature − °C − Output Voltage − VVO −40 −25 −10 5 20 35 50 65 80 95 110 125 VIN2 = 2.8 V IO = 250 mA VOUT2 150 160 170 180 −40 −25 −10 5 20 35 50 65 80 TJ − Junction Temperature − °C 95 110 125 190 200 210 Ground Current − Am Regulator 1 and Regulator 2 IOUT1 = 1 mA IOUT2 = 1 mA IOUT1 = 250 mA IOUT2 = 500 mA IO = 10 mA C O = 22 µF VOUT1 −60 −80 −9010 100 1 k 10 k −40 −20 −10 100 k 1 M −30 −50 −70 PSRR − Power Supply Rejection Ratio − dB f − Frequency − Hz −40 −60 −70 −90 10 100 1 k 10 k −20 100 k 1 M −10 −30 −50 −80 IO = 500 mA C O = 22 µF VOUT1 PSRR − Power Supply Rejection Ratio − dB f − Frequency − Hz TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com TPS70151 OUTPUT VOLTAGE GROUND CURRENT vs vs TEMPERATURE JUNCTION TEMPERATURE Figure7. Figure8. TPS70151 TPS70151 POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure9. Figure10.

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−60 −80 −90 10 100 1 k 10 k −40 −20 −10 100 k 1 M −30 −50 −70 PSRR − Power Supply Rejection Ratio − dB f − Frequency − Hz IO = 10 mA C O = 22 µF VOUT2 −40 −60 −7010 100 1 k 10 k −20 100 k 1 M −10 −30 −50 PSRR − Power Supply Rejection Ratio − dB f − Frequency − Hz IO = 250 mA C O = 22 µF VOUT2 0.01 0.1 100 1 k 10 k 100 k f − Frequency − Hz VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA V HzOutput Spectral Noise Density − µ 0.01 0.1 100 1 k 10 k 100 k f − Frequency − Hz VIN1 = 4.3 V VOUT1 = 3.3 V IO = 500 mA V HzOutput Spectral Noise Density − µ TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 TPS70151 TPS70151 POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO vs vs FREQUENCY FREQUENCY Figure11. Figure12. OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY Figure13. Figure14. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

0.01 0.1 100 1 k 10 k 100 k f − Frequency − Hz VIN2 = 2.8 V VOUT2 = 1.8 V IO = 250 mA V HzOutput Spectral Noise Density − µ 0.01 0.1 100 1 k 10 k 100 k f − Frequency − Hz VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA V HzOutput Spectral Noise Density − µ CO =□33 /c109F IO =□500□mA VO =□3.3 V TA =□25 C/c176 10 100 1□k 10 k -□Output□Impedance - 10 f□-□Frequency□-□Hz 100 100 k 1□M 10 M 0.1 0.01 ZO /c87 CO =□33 /c109F IO =□10□mA VO =□3.3 V TA =□25 C/c176 10 100 1□k 10 k -□Output□Impedance□- f□-□Frequency□-□Hz 100 100 k 1□M 10 M 0.1 0.01 ZO /c87 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY vs vs FREQUENCY FREQUENCY Figure15. Figure16. OUTPUT IMPEDANCE OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY Figure17. Figure18.

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CO =□33 /c109F IO =□250□mA VO =□1.8 V TA =□25/c176C 10 100 1□k 10 k -□Output□Impedance□- f□-□Frequency□-□Hz 100 100 k 1□M 10 M 0.1 0.01 ZO /c87 CO =□33 /c109F IO =□10□mA VO =□1.8 V TA =□25 C/c176 10 100 1□k 10 k -□Output□Impedance□- f□-□Frequency□-□Hz 100 100 k 1□M 10 M 0.1 0.01 ZO /c87 100 150 200 250 −40 −25 −10 5 20 35 50 65 80 T − Temperature − °C Dropout Voltage − mV IO = 500 mA C O = 33 mF VIN1 = 3.2 V 95 110 125 T − Temperature − °C Dropout Voltage − mV −40 −25 −10 5 20 35 50 65 80 95 110 125 IO = 10 mA IO = 0 mA C O = 33 mF VIN1 = 3.2 V TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 OUTPUT IMPEDANCE OUTPUT IMPEDANCE vs vs FREQUENCY FREQUENCY Figure19. Figure20. DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs TEMPERATURE TEMPERATURE Figure21. Figure22. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

2.5 3 3.5 4 4.5 5 5.5 VI − Input Voltage − V Dropout Voltage − mV IO = 500 mA VIN1 300 TJ = 125°C TJ = 25°C TJ= −40°C 100 200 300 400 500 2.5 3 3.5 4 4.5 5 5.5 VI − Input Voltage − V Dropout Voltage − mV IO = 250 mA VIN2 TJ = 125°C TJ = 25°C TJ = −40°C 250 − Output Current − mA VO − Change inD Output Voltage − mV IO t − Time − ms C o = 33 mF TA = 25°C VOUT1 = 3.3 V −20 500 − Output Current − mA VO − Change inD Output Voltage − mV IO t − Time − ms 250 −20 C o = 33 mF TA = 25°C VOUT2 = 1.8 V TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com TPS70102 TPS70102 DROPOUT VOLTAGE DROPOUT VOLTAGE vs vs INPUT VOLTAGE INPUT VOLTAGE Figure23. Figure24. LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE Figure25. Figure26.

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2.8 140 160 180 200 − Input Voltage − VVI t − Time − µs IO = 250 mA C o = 33 µF VOUT2 VO − Change inΔ Output Voltage − mV −10 3.8 0 20 40 60 80 100 120 5.3 4.3 140 160 180 200 − Input Voltage − VVI t − Time − µs IO = 500 mA C o = 33 µF VOUT1 −50 VO − Change inΔ Output Voltage − mV t − Time (Start-Up) − ms VO = 3.3 V C o = 33 µF IO = 500 mA VOUT1 SEQ = Low 0 2 − Output Voltage − VVOEnable Voltage − V VO = 1.8 V C o = 33 µF IO = 250 mA VOUT2 SEQ = High t − Time (Start-Up) − ms 0 2 Enable Voltage − V − Output Voltage − VVO TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE Figure27. Figure28. OUTPUT VOLTAGE AND ENABLE VOLTAGE OUTPUT VOLTAGE AND ENABLE VOLTAGE vs vs TIME (START-UP) TIME (START-UP) Figure29. Figure30. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 3.3V C O = 33 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 3.3 V C O = 33 /C0109F + 1 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω REGION OF INSTABILITY REGION OF INSTABILITY 50m /C0087 VO = 3.3 V C O = 10 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 3.3V C O = 10 /C0109F + 1 /C0109F TJ = 25/C0053C TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure31. Figure32. TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure33. Figure34. (1)Equivalentseriesresistance(ESR) referstothetotalseriesresistance,includingtheESR ofthecapacitor,any seriesresistanceadded externally,and PWB traceresistancetoC O .

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0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 1.8 V C O = 33 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 1.8 V C O = 33 /C0109F + 1 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω REGION OF INSTABILITY REGION OF INSTABILITY 50m /C0087 VO = 1.8 V C O = 10 /C0109F TJ = 25/C0053C 0.1 0.01 0 100 200 300 400 500 IO −Output Current −mA ESR −Equivalent Series Resistance −Ω 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 1.8 V C O = 10 /C0109F + 1 /C0109F TJ = 25/C0053C TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure35. Figure36. TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE (1) EQUIVALENT SERIES RESISTANCE (1) vs vs OUTPUT CURRENT OUTPUT CURRENT Figure37. Figure38. (1)Equivalentseriesresistance(ESR) referstothetotalseriesresistance,includingtheESR ofthecapacitor,any seriesresistanceadded externally,and PWB traceresistancetoC O . Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com Figure39.TestCircuitforTypicalRegions ofStability

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(Fixed Output Option) VI VOUT1 MR1 0.1 µF RESET 10 µF 10 µF 0.1 µF MR2 EN >2 V <0.7 V 250 kΩ 83% 95% 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQ 95% 83% NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010

APPLICATION INFORMATION

Sequencing Timing Diagrams This sectionprovidesa number of timingdiagrams showing how this device functionsin different configurations. VIN2 are tiedtothesame inputvoltage,theSEQ pin istiedtologiclow and thedeviceistoggledwiththe enable(EN) function. When thedeviceisenabled(EN ispulledlow),VOUT1 turns on firstand VOUT2 remains off untilVOUT1 reaches approximately83% of itsregulatedoutput voltage.At thattime,VOUT2 isturnedon.When VOUT1 reaches 95% of itsregulatedoutput,PG1 turnson (activehigh).SinceMR2 isconnectedtoPG1 forthis application,itfollowsPG1. When VOUT2 reaches95% of itsregulatedvoltage,RESET switchesto high voltagelevelaftera 120ms delay(seeFigure40). Figure40. Timing when SEQ = Low Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

0.1 µF 10 µF 10 µF 0.1 µF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V 250 kΩ 83% 95% 83% 95% 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQ NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com VIN2 are tiedtothesame inputvoltage,theSEQ pin istiedtologichighand thedeviceistoggledwiththe enable(EN) function. When thedeviceisenabled(EN ispulledlow),VOUT2 begins to power up. When itreaches 83% of its regulatedvoltage,VOUT1 begins to power up. PG1 turnson when VOUT1 reaches 95% of itsregulated voltage,and sinceMR2 and PG1 are tiedtogether, MR2 followsPG1. When VOUT1 reaches 95% of its regulatedvoltage,RESET switchesto high voltage levelaftera 120ms delay(seeFigure41). Figure41. Timing when SEQ = High

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0.1 µF RESET 10 µF 10 µF 0.1 µF MR2 EN 2 V 0.7 V TPS701xxPWP (Fixed Output Option) >2 V <0.7 V 250 kΩ 83% 95% 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQ 120ms 83% 95% NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 VIN2 are tiedtothesame inputvoltage,theSEQ pin istiedtologichighand MR1 istoggled. When thedeviceisenabled(EN ispulledlow),VOUT2 begins to power up. When itreaches 83% of its regulatedvoltage,VOUT1 begins to power up. PG1 turnson when VOUT1 reachesto95% ofitsregulated voltage,and sinceMR2 and PG1 are tiedtogether, MR2 followsPG1. When VOUT1 reaches 95% of its regulatedvoltage,the RESET switches to high voltagelevelaftera 120ms delay.When MR1 is pulledlow, itcauses RESET to go low, but the regulatorsremainsinregulation(seeFigure42). Figure42. Timing when MR1 isToggled Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

0.1 µF 10 µF 10 µF 0.1 µF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V 250 kΩ 120ms EN VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQUENCE 95% 83% 83% 95% NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) VOUT1 faults out TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com VIN2 are tiedtothesame inputvoltage,theSEQ pin istiedtologichighand VOUT1 faultsout. VOUT2 beginstopower up when thedeviceisenabled (EN ispulledlow).When VOUT2 reaches83% of its regulatedvoltage,then VOUT1 begins to power up. When VOUT1 reaches 95% of itsregulatedvoltage, PG1 turnson and RESET switchesto high voltage levelaftera 120ms delay.When VOUT1 faultsout, VOUT2 remainspowered on because the SEQ pinis high.PG1 istiedto MR2 and both change stateto logiclow.RESET isdrivenby MR2 and goes tologic lowwhen VOUT1 faultsout(seeFigure43). Figure43. Timing when VOUT1 FaultsOut

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0.1 µF 10 µF 10 µF 0.1 µF MR2 EN TPS701xxPWP (Fixed Output Option) >2 V <0.7 V 83% 95% 83% 95% 120ms ENABLE VOUT2 VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET SEQUENCE NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) VOUT2 faults out TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 VIN2 aretiedtosame inputvoltage,theSEQ istiedto logichigh,the deviceis enabled,and VOUT2 faults out. VOUT2 beginstopower up when thedeviceisenabled (EN ispulledlow).When VOUT2 reaches83% of its regulatedvoltage,VOUT1 beginsto power up. When VOUT1 reaches 95% of itsregulatedvoltage,PG1 turnson and RESET switchesto highvoltagelevel aftera 120ms delay.When VOUT2 faultsout,VOUT1 is powered down because SEQ ishigh.PG1 istiedto MR2 and both change stateto logiclow. RESET goes lowwhen VOUT2 faultsout(seeFigure44). Figure44. Timing when VOUT2 FaultsOut Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

1.8 V VIN1 VIN2 EN SEQ VOUT1 VSENSE1 PG1 MR2 RESET MR1 VSENSE2 VOUT2 TPS70151 PWP 5 V 0.1 µF RESET 10 µF 10 µF 0.1 µF DSP MR2 PG1 EN 250 kΩ >2 V <0.7 V 250 kΩ >2 V <0.7 V >2 V <0.7 V 5 V 83% 95% 120ms EN VOUT2 (Core) PG1 RESET SEQ 95% 83% VOUT1 (I/O) NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com SplitVoltageDSP Application Figure45 shows a typicalapplicationwhere the TPS70151 is powering up a DSP. In thisapplication,by groundingtheSEQ pin,VOUT1 (I/O)ispowered up first,and thenVOUT2 (core). Figure45.ApplicationTiming Diagram (SEQ = Low)

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0.1 µF 0.1 µF 1.8 V 10 µF 10 µF DSP MR2 PG1 250 kΩ EN>2 V <0.7 V 250 kΩ 5 V 83% 95% 83% 95% 120ms EN VOUT2 (Core) VOUT1 (I/O) PG1 RESET SEQ NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. (see Note A) TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 Figure46 shows a typicalapplicationwhere theTPS70151 ispoweringup a DSP. Inthisapplication,by pulling up theSEQ pin,VOUT2 (core)ispowered up first,and thenVOUT1 (I/O). Figure46.ApplicationTiming Diagram (SEQ = High) InputCapacitor For a typicalapplication,an inputbypass capacitor(0.1mF to 1mF) isrecommended. Thiscapacitorfiltersany high-frequencynoisegeneratedintheline.For fasttransientconditionswhere droopattheinputoftheLDO may occurbecause ofhighinrushcurrent,itisrecommended toplacea largercapacitorattheinputas well.The size of thiscapacitordepends on the outputcurrentand responsetimeof the main power supply,as wellas the distancetotheVI pinsoftheLDO. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com Output Capacitor As withmost LDO regulators,theTPS701xx requiresan outputcapacitorconnectedbetween OUT and GND to stabilizethe internalcontrolloop.The minimum recommended capacitancevalue is 10mF and the ESR (equivalentseriesresistance)must be between 50m Ω and 2.5Ω.Capacitorvalues10mF orlargerareacceptable, providedthe ESR islessthan 2.5Ω. Solidtantalumelectrolytic,aluminum electrolytic,and multilayerceramic capacitorsare allsuitable,providedtheymeet the requirementsdescribedabove.Largercapacitorsprovidea widerrange of stabilityand betterloadtransientresponse.Table 3 providesa partiallistingof surface-mount capacitorssuitableforuse withtheTPS701xx forfasttransientresponseapplication. Thisinformation,alongwiththeESR graphs,isincludedtoassistinselectionofsuitablecapacitancefortheuser application.When necessarytoachievelow heightrequirementsalongwithhighoutputcurrentand/orhighload capacitance,severalhigherESR capacitorscan be used inparalleltomeet theguidelinesabove. Table3.PartialListingofTPS701xx-Compatible Surface-MountCapacitors VALUE MANUFACTURER MAXIMUM ESR MFR PART NO. 22mF Kemet 345m Ω 7495C226K0010AS 33mF Sanyo 100m Ω 10TPA33M 47mF Sanyo 100m Ω 6TPA47M 68mF Sanyo 45m Ω 10TPC68M ESR and TransientResponse LDOs typicallyrequirean externaloutputcapacitorforstability.Infasttransientresponseapplications,capacitors areused tosupporttheloadcurrentwhiletheLDO amplifierisresponding.Inmost applications,one capacitoris used tosupportbothfunctions. Besidesitscapacitance,everycapacitoralsocontainsparasiticimpedances.These parasiticimpedances are resistiveas wellas inductive.The resistiveimpedance iscalledequivalentseriesresistance(ESR), and the inductiveimpedance iscalledequivalentseriesinductance(ESL).The equivalentschematicdiagram of any capacitorcan thereforebe drawn as shown inFigure47. Figure47. ESR and ESL In most cases one can neglectthe effectof inductiveimpedance ESL. Therefore,the followingapplication focusesmainlyon theparasiticresistanceESR.

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 Figure48 shows theoutputcapacitorand itsparasiticresistancesina typicalLDO outputstage. Figure48. LDO Output Stage withParasiticResistancesESR Insteadystate(dcstatecondition),theloadcurrentissuppliedby theLDO (solidarrow)and thevoltageacross thecapacitoristhesame as theoutputvoltage(V(CO) = VOUT ).Thisconditionmeans no currentisflowingintothe C O branch.IfIOUT suddenlyincreases(atransientcondition),thefollowingresultsoccur:

The LDO isnotabletosupplythesudden currentneed because ofitsresponsetime(t1 inSplitVoltageDSP Application).Therefore,capacitorC O providesthecurrentforthenew loadcondition(dashedarrow).C O now actslikea batterywithan internalresistance,ESR. Dependingon thecurrentdemand attheoutput,a voltage dropoccursatR ESR .Thisvoltageisshown as VESR inFigure44.
When C O isconductingcurrenttotheload,initialvoltageattheloadwillbe VO = V(CO) – VESR .As a resultof the dischargeof C O , the outputvoltageVO drops continuouslyuntilthe response time t1 of the LDO is reachedand theLDO resumes supplyingtheload.From thispoint,theoutputvoltagestartsrisingagainuntil itreachestheregulatedvoltage.Thisperiodisshown as t2 inFigure49. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31

/C00421/C0467/C0032R2 TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com Figure49. CorrelationofDifferentESRs and TheirInfluenceon theRegulationofVO ata Load Step from Low-to-HighOutput Current Figure49 alsoshows theimpactofdifferentESRs on theoutputvoltage.The leftbracketsshow differentlevels ofESRs where number 1 displaysthelowestand number 3 displaysthehighestESR. From above,thefollowingconclusionscan be drawn:

The highertheESR, thelargerthedroopatthebeginningofloadtransient.
The smallertheoutputcapacitor,thefasterthedischargetimeand thegreaterthevoltagedroop duringthe LDO responseperiod. Conclusion To minimizethetransientoutputdroop,capacitorsmust have a low ESR and be largeenough tosupportthe minimum outputvoltagerequirement. Programming theTPS70102 AdjustableLDO Converter The outputvoltageof the TPS70102 adjustableregulatorsare programmed usingexternalresistordividersas shown inFigure50. ResistorsR1 and R2 shouldbe chosen forapproximately50mA dividercurrent.Lower valueresistorscan be used,but offerno inherentadvantageand waste more power.Highervaluesshouldbe avoidedas leakage currentsat the sense terminalincreasethe outputvoltageerror.The recommended designprocedureisto choose R2 = 30.1kΩ tosetthedividercurrentatapproximately50mA,and thencalculateR1 usingEquation1: (1) where:
VREF = 1.224Vtyp(theinternalreferencevoltage)

OUTPUT□VOLTAGE PROGRAMMING□GUIDE VO VI OUT FB GND EN IN <0.7□V >2.0 V TPS70102 0.1 /c109F OUTPUT VOLTAGE R1 R2 2.5□V 3.3□V 3.6□V UNIT 31.6 51.1 59.0 30.1 30.1 30.1 k/c87 k/c87 k/c87 P D(max) /C0043TJ max /C0042TA R /C0113JA P D /C0043/C0466V I/C0042V O /C0467/C0032IO TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 www.ti.com SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 Figure50. TPS70102 AdjustableLDO RegulatorProgramming RegulatorProtection Both TPS701xx PMOS-pass transistorshave built-inback diodesthatconductreversecurrentswhen theinput voltagedropsbelow theoutputvoltage(forexample,duringpower-down).Currentisconductedfromtheoutput totheinputand isnotinternallylimited.When extendedreversevoltageisanticipated,externallimitingmay be appropriate. The TPS701xx also featuresinternalcurrentlimitingand thermalprotection.During normal operation,the TPS701xx regulator1 limitsoutputcurrentto approximately1.6A (typ)and regulator2 limitsoutputcurrentto approximately750mA (typ).When currentlimitingengages, the outputvoltagescalesback linearlyuntilthe overcurrentconditionends.While currentlimitingisdesignedto preventgrossdevicefailure,care shouldbe taken not to exceed the power dissipationratingsof the package.Ifthe temperatureof the deviceexceeds +150°C (typ),thermal-protectioncircuitryshuts itdown. Once the devicehas cooled below +130°C (typ), regulatoroperationresumes. Power Dissipationand JunctionTemperature Specifiedregulatoroperationisassuredtoa junctiontemperatureof+125°C; themaximum junctiontemperature shouldbe restrictedto+125°C undernormaloperatingconditions.Thisrestrictionlimitsthepower dissipationthe regulatorcan handleinany givenapplication.To ensure the junctiontemperatureiswithinacceptablelimits, calculatethemaximum allowabledissipation,PD(max),and theactualdissipation,PD ,whichmust be lessthanor equaltoPD(max). The maximum-power-dissipationlimitisdeterminedusingEquation2: (2) where:

TJmax isthemaximum allowablejunctiontemperature
R qJA isthethermalresistancejunction-to-ambientforthepackage;thatis,32.6°C/W forthe20-terminalPWP withno airflow
TA istheambienttemperature The regulatordissipationiscalculatedusingEquation3: (3) Power dissipationresultingfrom quiescentcurrentisnegligible.Excessivepower dissipationwilltriggerthe thermalprotectioncircuit. Copyright© 1999–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33

TPS70145,TPS70148 TPS70151,TPS70158 TPS70102 SLVS222I –DECEMBER 1999–REVISED AUGUST 2010 www.ti.com

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionH (December, 2009)toRevisionI Page Changes from RevisionG (August,2009)toRevisionH Page

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS70102PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70102 TPS70102PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70102 TPS70102PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70102 TPS70102PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70102 TPS70145PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70145 TPS70145PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70145 TPS70145PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70145 TPS70145PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70145 TPS70148PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70148 TPS70148PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70148 TPS70148PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70148 TPS70148PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70148 TPS70151PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70151 TPS70151PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70151 TPS70151PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70151 TPS70151PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70151 TPS70158PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70158

www.ti.com 11-Apr-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS70158PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70158 TPS70158PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70158 TPS70158PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70158 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70102PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70145PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70148PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70151PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70158PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2

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Summary

Dual-Output Low Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems REVISED AUGUST 2010

Description