TPS51117PWG4

TPS51117 TI | Alldatasheet

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EN_PSV TON VOUT TPS51117PW TRIP V5DRV DRVL PGND V5FILT VFB PGOOD GND VOUT PGND PGOOD +5V EN_PSV VIN 1.8V~28V GND TPS51117 SLVS631–DECEMBER 2005 SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER High Efficiency, Low Power Consumption, The TPS51117 is a cost effective, synchronous buck 4.5-µA Typical Shutdown Current controller for POL voltage regulation in notebook PC applications. The controller is dedicated for Adaptive Fixed Frequency Emulated On-Time Control, On-Time D-CAP™Mode operation that provides Adjustable from 100 kHz to 550 kHz ease of use, low external component count, and Fast Transient Response excellent fast transient response at the same time. < 1% Initial Reference Accuracy Auto-skip mode for high efficiency down to the milli-ampere load range, or PWM-only mode for low Output Voltage Range: 0.75 V to 5.5 V noise operation is selectable. Wide Input Voltage Range: 1.8 V to 28 V The current sensing scheme for positive overcurrent Selectable Auto-Skip/PWM-Only Operation and negative overcurrent protection is loss-less Temperature Compensated (4500 ppm/°C) low-side RDS(on) sensing plus temperature Low-Side RDS(on) Overcurrent Sensing compensation. The device receives 5-V (4.5 V to 5.5 Negative Overcurrent Limit supply from another regulator such as the TPS51120 or TPS51020 in the NBPC system. The Integrated Boost Diode conversion input can be either VBAT or 5-V rail, Integrated OVP/UVP and Thermal Shutdown ranging from 1.8 V to 28 V, and the output voltage Power-Good Signal range is from 0.75 V to 5.5 V. Internal 1.2-ms Voltage Softstart The TPS51117 is available in the 14-pin TSSOP Output Discharge (Softstop) package and is specified from –40°C to 85°C. Notebook Computers I/O Supplies System Power Supplies Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS(1) DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TPS51117 SLVS631–DECEMBER 2005 ORDERING INFORMATION(1)(2) MINIMUM ORDERING PART OUTPUT TA PACKAGE PINS ORDER ECO PLAN NUMBER SUPPLY QUANTITY TPS51117PW Tube PLASTIC Green –40°C to 85°C TSSOP (PW) (RoHS & no Sb/Br) TPS51117PWR Tape-and-Reel 2000 (1) All packaging options have Cu NIPDAU lead/ball finish. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. VALUE UNIT VBST –0.3 to 36 VBST (with respect to LL) –0.3 to 6 Input voltage range EN_PSV, TRIP, V5DRV, V5FILT –0.3 to 6 V VOUT –0.3 to 6 TON –0.3 to 6 DRVH –1 to 36 DRVH (with respect to LL) –0.3 to 6 Output voltage range LL –1 to 30 V PGOOD, DRVL –0.3 to 6 PGND –0.3 to 0.3 TA Operating free-air temperature –40 to 85 ° C Tstg Storage temperature range –55 to 150 TJ Junction temperature range –40 to 125 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Ta <25°C DERATING FACTOR TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING 14 pin TSSOP 750 mW 7.5 mW/°C 300 mW over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply input voltage range 4.5 5.5 V VBST 4.5 VBST (with respect to LL) 4.5 5.5 Input voltage range EN_PSV, TRIP, V5DRV, V5FILT –0.1 5.5 V VOUT –0.1 5.5 TON –0.1 5.5 DRVH –0.8 DRVH (with respect to LL) –0.1 5.5 Output voltage range LL –0.8 V PGOOD, DRVL –0.1 5.5 PGND –0.1 0.1 Operating free-air temperature, TA –40

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ELECTRICAL CHARACTERISTICS

SLVS631–DECEMBER 2005 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT V5FILT + V5DRV current, PWM, EN_PSV = float, VFB IV5FILTPWM Supply current 400 750 µA V5FILT + V5DRV current, auto-skip, EN_PSV = 5 V, IV5FILTSKIP Supply current 250 470 µA VFB = 0.77V, LL = 0.5 V IV5DRVSDN V5DRV shutdown current V5DRV current, EN_PSV = 0 V µA IV5FILTSDN V5FILT shutdown current V5FILT current, EN_PSV = 0 V 4.5 7.5 µA VOUT AND VFB VOLTAGES VOUT Output voltage Adjustable output range 0.75 5.5 V VVFB VFB regulation voltage 750 mV TA = 25°C, bandgap initial accuracy –0.9% 0.9% VFB regulation voltage VVFB_TOL TA = 0°C to 85°C –1.3% 1.3% tolerance TA = -40°C to 85°C –1.6% 1.6% IVFB VFB input current VFB = 0.75 V, absolute value 0.02 0.1 µA RDischg VOUT discharge resistance EN_PSV = 0 V, VOUT = 0.5 V Ω ON-TIME TIMER AND INTERNAL SOFT START TONN Nominal on time VLL = 12 V, VOUT = 2.5 V, RTON = 250 kΩ 750 ns TONF Fast on time VLL = 12 V, VOUT = 2.5 V, RTON = 100 kΩ 264 330 396 ns TONS Slow on time VLL = 12 V, VOUT = 2.5 V, RTON = 400 kΩ 1169 ns TON(MIN) Minimum on time VOUT = 0.75 V, RTON = 100 kΩto 28 V(1) 110 140 ns VFB = 0.7 V, LL = -0.1 V, TOFF(MIN) Minimum off time 440 ns TRIP = open Time from EN_PSV > 3 V to VFB regulation TSS Internal soft start time 0.82 1.2 1.5 ms value = 0.735 V OUTPUT DRIVERS Source, VVBST-DRVH = 0.5 V Ω RDRVH DRVH resistance Sink, VDRVH-LL = 0.5 V 1.5 2.5 Ω Source, VV5DRV-DRVL = 0.5 V Ω RDRVL DRVL resistance Sink, VDRVL-PGND = 0.5 V 1.5 2.5 Ω DRVH-low (DRVH = 1 V) to DRVL-high ns (DRVL = 4 V), LL = –0.05 V TD Dead time DRVL-low (DRVL = 1 V) to DRVH-high ns (DRVH = 4V), LL = –0.05 V INTERNAL BST DIODE VFBST Forward voltage VV5DRV-VBST, IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V IVBSTLK VBST leakage current VBST = 34 V, LL = 28 V 0.1 µ A (1) Design constraint, ensure actual on-time is larger than the max value (i.e., design RTON such that the min tolerance is 100 kΩ).

www.ti.com ELECTRICAL CHARACTERISTICS (Continued) TPS51117 SLVS631–DECEMBER 2005 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UVLO/LOGIC THRESHOLD Wake up 3.7 3.9 4.1 V VUVLO V5FILT UVLO Threshold Hysteresis 200 300 400 mV EN_PSV low 0.7 1.0 1.3 V Hysteresis 150 200 250 mV EN_PSV logic input VEN_PSV EN_PSV float (set PWM_only mode) 1.7 1.95 2.25 V voltage EN_PSV high (set Auto_skip mode) 2.4 2.65 2.9 V Hysteresis 100 175 250 mV IEN_PSV EN_PSV source current EN_PSV = GND, absolute value(1) µA POWERGOOD COMPARATOR PG in from lower (PGOOD goes high) 92.5% 95% 97.5% PG low hysteresis (PGOOD goes low) –4% –5.5% –7% VTHPG PG threshold PG in from higher (PGOOD goes high) 102% 105% 107% PG high hysteresis (PGOOD goes low) 5.5% IPGMAX PG sink current PGOOD = 0.5 V 2.5 7.5 mA TPGDEL PG delay Delay for PGOOD in µs CURRENT SENSE ITRIP TRIP source current VTRIP < 0.3 V, TA = 25°C µA ITRIP temperature TCITRIP On the basis of 25°C 4500 ppm/°C coefffecient Current limit threshold VRtrip VTRIP-GND voltage(1), all temperatures 200 mV range setting range Overcurrent limit VOCLoff (VTRIP-GND-VPGND-LL) voltage VTRIP-GND = 60 mV –10 mV comparator offset Negative overcurrent limit (VTRIP-GND-VLL-PGND) voltage VTRIP-GND = 60 mV, VUCLoff –9.5 0.5 10.5 mV comparator offset EN_PSV = float Zero crossing comparator VZCoff VPGND-LL voltage, EN_PSV = 3.3 V –9.5 0.5 10.5 mV offset UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP VFB OVP trip threshold OVP detect 111% 115% 119% VFB OVP propagation TOVPDEL See (1) 1.5 µs delay UVP detect 65% 70% 75% VUVP VFB UVP trip threshold Hysteresis 10% TUVPDEL VFB UVP delay µs TUVPEN UVP enable delay After 1.7 × TSS, UVP protection engaged 1.4 2.6 ms THERMAL SHUTDOWN Shutdown temperature(1) 160 Thermal shutdown TSDN threshold Hysteresis(1) (1) Ensured by design. Not production tested.

www.ti.com DEVICE INFORMATION VBST LL V5DRV EN_PSV TON PGOOD DRVH DRVL VFB VOUT V5FILT TRIP GND PGND TSSOP (PW) PACKAGE (TOP VIEW) TPS51117 SLVS631–DECEMBER 2005 TERMINAL FUNCTIONS TERMINAL I/O NO. High-side NFET gate driver output. Source 5 Ω, sink 1.5 ΩLL-node referenced driver. Drive voltage DRVH O corresponds to VBST to LL voltage. Rectifying (low-side) NFET gate driver output. Source 5 Ω, sink 1.5 ΩPGND referenced driver. Drive voltage DRVL O is V5DRV voltage. Enable/power save pin. Connect to ground to disable SMPS. Connect to 3.3 V or 5 V to turn on SMPS and EN_PSV I activate skip mode. Float to turn on SMPS but disable skip mode (forced continuous conduction mode). GND I Signal ground pin. LL I/O High-side NFET gate driver return. Also serves as anode of overcurrent comparator. Ground return for rectifying NFET gate driver. Also cathode of overcurrent protection and source node of the PGND I/O output discharge switch. Power-good window comparator, open-drain, output. Pull up to 5-V rail with a pull-up resistor. Current PGOOD O capability is 7.5 mA. TON I On-time / frequency adjustment pin. Connect to LL with 100-kΩto 600-kΩresistor. Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both TRIP I overcurrent and negative overcurrent limit. Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An VBST I internal PN diode is connected between V5DRV to this pin. Designer can add external schottky diode if forward drop is critical to drive the power NFET. VFB I SMPS voltage feedback input. Connect the resistor divider here for adjustable output. Connect to SMPS output. This terminal serves two functions: output voltage monitor for on-time adjustment, VOUT I and input for the output discharge switch. 5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect 1 µF or V5DRV I more between this pin and PGND to support instantaneous current for gate drivers. 5-V Power supply input for all the control circuitry except gate drivers. Supply 5-V ramp rate should be 17 V5FILT I mV/us or less and TJ < 85°C to secure safe start-up of the internal reference circuit. Apply RC filter consists of 300 Ω+ 1 µF or 100 Ω+ 4.7 µF at the pin input.

www.ti.com FUNCTIONAL BLOCK DIAGRAM 2.9 3.9 /3.6 TPS51117 SLVS631–DECEMBER 2005

www.ti.com DETAILED DESCRIPTION PWM OPERATION VOUT 1 R2 0.75 V (1) LIGHT LOAD CONDITION WITH AUTO-SKIP FUNCTION IOUT(LL)

2 L ƒsw

(2) TPS51117 SLVS631–DECEMBER 2005 The main control loop of the TPS51117 is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports proprietary D-CAP™Mode that uses an internal compensation circuit and is suitable for minimal external component count configuration when an appropriate amount of ESR at the output capacitor(s) is allowed. Basic operation of D-CAP Mode can be described as follows. At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after the internal one shot timer expires. This one shot is determined by VIN and VOUT to keep the frequency fairly constant over the input voltage range at steady state, hence it is called adaptive on-time control or fixed frequency emulated on-time control (see PWM frequency and Adaptive On-Time Control). The MOSFET is turned on again when both feedback information, monitored at VFB voltage, indicates insufficient output voltage AND inductor current information indicates below the overcurrent limit. Repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side or rectifying MOSFET is turned on each OFF state to keep the conduction loss to a minimum. The TPS51117 supports selectable PWM-only and auto-skip operation modes. If EN_PSV is grounded, the switching regulator is disabled. If the EN_PSV pin is connected to 3.3 V or 5 V, the regulator is enabled with auto-skip mode selected. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables a seamless transition to reduced frequency operation during a light load condition so that high efficiency is maintained over a broad range of load currents. If the EN_PSV pin is floated, it is internally pulled up to 1.95 V, and the regulator is enabled with PWM-only mode selected. The rectifying MOSFET is not turned off when inductor current reaches zero. The converter runs forced continuous conduction mode for the entire load range. System designers may want to use this mode to avoid a certain frequency during a light load condition but with the cost of low efficiency. However, be aware the output has the capability to both source and sink current in this mode. If the output terminal is connected to a voltage source higher than the regulator’s target, the converter sinks current from the output and boosts the charge into the input capacitor. This may cause unexpected high voltage at VIN and may damage the power FETs. DC output voltage can be set by the external resistor divider as follows (refer to Figure 22 and Figure 23). If auto-skip mode is selected, the TPS51117 automatically reduces the switching frequency during a light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase of Vout ripple or load regulation. Detailed operation is described as follows. As the output current decreases from a heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. Since the output voltage is still higher than the reference at this moment, both high-side and low-side MOSFETs are turned off and wait for the next cycle. As the load current decreases further, the converter runs in discontinuous conduction mode, taking longer time to discharge the output capacitor below the reference voltage. Note the ON time is kept the same as during the heavy load condition. In reverse, when the output current increases from a light load to a heavy load, the switching frequency increases to the preset value as the inductor current reaches to the continuous conduction. The transition load point to light load operation, IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode), can be calculated as follows: where fsw is the PWM switching frequency. Switching frequency versus output current in the light load condition is a function of L, fsw, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is about 60 kHz at IOUT(LL)/5 if the PWM switching frequency is 300 kHz.

www.ti.com HIGH-SIDE DRIVER SOFTSTART POWERGOOD OUTPUT DISCHARGE CONTROL (SOFTSTOP) OVERCURRENT LIMIT VTRIP(mV) RTRIP(k ) 10 (A) (4) Iocp VTRIPRDS(on) Iripple2 VTRIP RDS(on)

2 L ƒ VIN VOUT VOUT

(5) TPS51117 SLVS631–DECEMBER 2005 DETAILED DESCRIPTION (continued) The high-side driver is designed to drive high-current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5DRV supply. An internal PN diode is connected between V5DRV to this pin. The designer can add an external schottky diode if forward drop is critical to drive the high-side NFET or to achieve the last one percent efficiency improvement. The average drive current is also estimated by the gate charge at Vgs = 5 V times the switching frequency. The instantaneous drive current is supplied by the flying capacitor between the VBST pin and LL pin. The drive capability is represented by its internal resistance, which is 5 Ωfor VBST to DRVH and 1.5 Ωfor DRVH to LL. The TPS51117 has an internal, 1.2-ms, voltage servo softstart with overcurrent limit. When the EN_PSV pin becomes high, an internal DAC begins ramping up the reference voltage to the error amplifier. Smooth control of the output voltage is maintained during start up. The TPS51117 has power-good output. PGOOD is an open drain 7.5-mA pull-down output. This pin should be typically connected to a 5-V power supply node through a 100-kΩresistor. The power-good function is activated after the soft start has finished. If the output voltage becomes within ±5% of the target value, internal comparators detect the power-good state and the power-good signal becomes high after a 64-µs internal delay. If the output voltage goes outside ±10% of the target value, the power-good signal becomes low immediately. The TPS51117 discharges output when EN_PSV is low or the converter is in a fault condition (UVP, OVP, UVLO, or thermal shutdown). The TPS51117 discharges output using an internal 20-ΩMOSFET which is connected to VOUT and PGND. The discharge time-constant is a function of the output capacitance and resistance of the discharge transistor. The TPS51117 has cycle-by-cycle overcurrent limiting control. Inductor current is monitored during the OFF state and the controller keeps the OFF state when inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and a cost effective solution, the TPS51117 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP terminal sources 10-µA ITRIP current, and the trip level is set to the OCL trip voltage, VTRIP as in the following equation. Inductor current is monitored by the voltage between the PGND pin and the LL pin so the LL pin should be connected to the drain terminal of the low-side MOSFET. ITRIP has 4500 ppm/°C temperature coefficient to compensate the temperature dependency of the RDS(on). PGND is used as the positive current sensing node so PGND should be connected to the source terminal of the bottom MOSFET. As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at overcurrent threshold, Iocp, can be calculated as follows; In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall. Eventually it crosses the undervoltage protection threshold and shutdown.

www.ti.com NEGATIVE OVERCURRENT LIMIT (PWM-ONLY MODE) OVERVOLTAGE PROTECTION UNDERVOLTAGE PROTECTION UVLO PROTECTION THERMAL SHUTDOWN TPS51117 SLVS631–DECEMBER 2005 DETAILED DESCRIPTION (continued) The TPS51117 also supports cycle-by-cycle negative overcurrent limiting in PWM-only mode. The overcurrent limit is set to be negative but is the same absolute value as the positive overcurrent limit. If output voltage continues to rise, the bottom MOSFET stays on, thus inductor current is reduced and reverses direction after it reaches zero. When there is too much negative current in the inductor, the bottom MOSFET is turned off and the current flows to VIN through the body diode of the top MOSFET. Because this protection reduces current to discharge the output capacitor, output voltage tends to rise, eventually hitting the overvoltage protection threshold and shutdown. In order to prevent false OVP from triggering, the bottom MOSFET is turned on again 400 ns after it is turned off. If the device hits the negative overcurrent threshold again before output voltage is discharged to the target level, the bottom MOSFET is turned off and the process repeats, which is called NOCL Buzz. It ensures maximum allowable discharge capability when output voltage continues to rise. On the other hand, if the output voltage is discharged to the target level before the NOCL threshold is reached, the bottom MOSFET is turned off, the top MOSFET is then turned on, and the device resumes normal operation. The TPS51117 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage condition. When the feedback voltage becomes higher than 115% of the target value, the top MOSFET is turned off and the bottom MOSFET is turned on immediately. The output is also discharged by the internal 20-Ωtransistor. Also, the TPS51117 monitors VOUT terminal voltage directly and if it becomes greater than 5.75 V, it turns off the top MOSFET driver. When the feedback voltage becomes lower than 70% of the target value, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 µs, the TPS51117 latches off the high-side and low-side MOSFETs and discharges the output with the internal 20-Ωtransistor. This function is enabled after 2 ms from when EN_PSV is brought high, i.e., UVP is disabled during start up. The TPS51117 has V5FILT undervoltage lockout protection (UVLO). When the V5FILT voltage is lower than the UVLO threshold voltage, the TPS51117 is shut off. This is a nonlatched protection. The TPS51117 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C), the TPS51117 shuts itself off. Both top and bottom gate drivers are tied low with output discharged through the VOUT terminal. This is also a nonlatched protection. The device recovers once the temperature has decreased approximately 12°C.

www.ti.com 1.03 1.04 1.05 1.06 1.07 PWM Only Skip Mode V - Output Voltage - V O I - Output Current - A O 2.46 2.48 2.50 2.52 2.54 PWM Only Auto Skip V - Output Voltage - V O I - Output Current - A O 1.03 1.04 1.05 1.06 1.07 I = 10 A O I = 0 A O V - Output Voltage - V O V - Input Voltage - V I Auto Skip 2.46 2.48 2.50 2.52 2.54 I = 10 A O I = 0 A O V - Output Voltage - V O V - Input Voltage - V I Auto Skip TPS51117 SLVS631–DECEMBER 2005 TYPICAL CHARACTERISTICS (continued)

1.05 V OUTPUT VOLTAGE

2.5 V OUTPUT VOLTAGE

Figure 10. Figure 11. Figure 12. Figure 13.

www.ti.com 100 0.001 0.01 0.1 h - Efficiency - % V = 8 V I V = 12 V I V = 20 V I V = 8 V I V = 12 V I V = 20 V I PWM Only f = 350 kHz sw Auto Skip I - Output Current - A O 100 0.001 0.01 0.1 h- Efficiency - % V = 20 V I V = 8 V I V = 12 V I V = 20 V I V = 8 V I V = 12 V I PWM Only f = 300 kHz sw I - Output Current - A O t - Time - 10 s/div m I (5 A/div) IND I (5 A/div) O V (50 mV/div) O t - Time - 10 s/div m V (50 mV/div) O I (5 A/div) IND I (5 A/div) O TPS51117 SLVS631–DECEMBER 2005 TYPICAL CHARACTERISTICS (continued)

1.05 V EFFICIENCY

2.5 V EFFICIENCY

Figure 14. Figure 15.

1.05 V LOAD TRANSIENT RESPONSE

2.5 V LOAD TRANSIENT RESPONSE

Figure 16. Figure 17.

www.ti.com V (20 mV/div) O LL (10 V/div) DRVL (5 V/div) EN_PSV (5 V/div) V (20 mV/div) O LL (10 V/div) DRVL (5 V/div) EN_PSV (5 V/div) EN_PSV (2 V/div) V (1 V/div) O PGOOD (5 V/div) t - Time - 1 ms/div EN_PSV (2 V/div) V (1 V/div) O PDOOD (5 V/div) DRVL (5 V/div) t - Time - 10 ms/div TPS51117 SLVS631–DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) MODE TRANSITION MODE TRANSITION AUTO-SKIP TO PWM PWM TO AUTO-SKIP Figure 18. Figure 19.

2.5 V START-UP WAVEFORMS

2.5 SHUTDOWN WAVEFORMS

Figure 20. Figure 21.

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APPLICATION INFORMATION

LOOP COMPENSATION AND EXTERNAL PARTS SELECTION D-CAP™Mode Operation Control Logic and Driver VFB DRVL IL Voltage Divider PWM VIN Lx DRVH Io Vc Co ESR RL Ic Switching Modulator 0.75V Output Capacitor ƒo

2 ESR Co ƒsw

(6) R1 VOUT 0.75 0.75 (7) TPS51117 SLVS631–DECEMBER 2005 A buck converter system using D-CAP™Mode can be simplified as shown in Figure 22. Figure 22. Simplified Diagram of the Modulator voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases. µF and ESR in range of 10 mΩ. These values make f0 in the order of 100 kHz or less and the loop is stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode. approximately 15 mV at the comparing point. This generates Vripple = (VOUT/0.75) × 15 mV at the output node. The output capacitor ESR should meet this requirement.

1. Determine the value of R1 and R2

The recommended R2 value is 10 kΩto 100 kΩ. Calculate R1 by Equation 7.

www.ti.com TON(max) 1 ƒ VOUT VIN(min) (8) RTON

2 TON(max) 50 ns

VIN(min) VOUT 150 mV [ ] (9) LIND IIND(ripple) ƒ VIN(max) VOUT VOUT VIN(max) IOUT(max) ƒ VIN(max) VOUT VOUT VIN(max) (10) IIND(peak) VTRIP RDS(on) L ƒ VIN(max) VOUT VOUT VIN(max) (11) ESR VOUT 0.015 Iripple 0.75 VOUT IOUT(max) 60 [m ] (12) 30 mV 1.2 IOUT(max) 0.5 Iripple RDS(on) 200 mV 1.2 IOUT(max) 0.5 Iripple (13) TPS51117 SLVS631–DECEMBER 2005 APPLICATION INFORMATION (continued) Switching frequency is usually determined by the overall view of the DC-DC converter design of: size, efficiency or cost, and mostly dictated by external component constraints such as the size of inductor and/or output capacitor. In the case where an extremely low or high duty factor is expected, the minimum on-time or off-time also needs to be considered to satisfy the required duty factor. Once the switching frequency is decided, RTON can be determined by Equation 8 and Equation 9, 3. Choose inductor A good starting point inductance value is where the ripple current is approximately 1/4 to 1/2 of the maximum output current. For applications that require fast transient response with minimum VOUT overshoot, consider a smaller inductance than above. The cost of a small inductance value is higher steady state ripple, larger line regulation, and higher switching loss. The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as follows. 4. Choose output capacitor(s) Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet the required ripple voltage above. A quick approximation is shown in Equation 12. 5. Choose MOSFETs Loss-less current sensing and overcurrent protection of the TPS51117 is determined by RDS(on) of the low-side MOSFET. So, RDS(on) times the inductor current value at the overcurrent point should be in the range of 30 mV to 200 mV for the entire operational temperature range. Assuming a 20% guard band, RDS(on) in the following equation should satisfy the full temperature range. 6. Choose Rtrip Once the low-side FET is decided, select an appropriate Rtrip value that provides Vtrip equal to RDS(on) times Ipeak. 7. LPF for V5FILT In order to reject high frequency noise and also secure safe start-up of the internal reference circuit, apply 1 µF of MLCC closely at the V5FILT pin with a 300-Ωresistor to create a LPF between +5-V supply and the pin. 8. VBST capacitor, VBST diode

www.ti.com THERMAL CONSIDERATION IG Qg ƒsw (14) WDRIVE VV5DRV Qg(top) Qg(btm) ƒsw (15) WPKG TJ(max) TA(max) JA (16) LAYOUT CONSIDERATIONS TPS51117 SLVS631–DECEMBER 2005 APPLICATION INFORMATION (continued) Apply 0.1-µF MLCC between VBST and the LL node as the flying capacitor for the high-side FET driver. The TPS51117 has its own boost diode on-board between V5DRV and VBST. This is a PN junction diode and strong enough for most typical applications. However, in case efficiency has priority over cost, the designer may add a Schottky diode externally to improve gate drive voltage of the high-side FET. A Schottky diode has a higher leakage current, especially at high temperature, than a PN junction diode. A low leakage diode should be selected in order to maintain VBST voltage during low frequency operation in skip mode. Power dissipation of the TPS51117 is mainly generated from the FET drivers. Average drive current can be estimated by gate charge, Qg, times the switching frequency. Qg is the charge needed to charge gate capacitance up to the V5DRV voltage of 5 V. Actual values are shown on MOSFET datasheets provided by the manufacturer. Total power dissipation, therefore, to drive the top and bottom MOSFETs can be calculated by the following equation Equation 15. This power plus a small amount of dissipation (less than 5 mW) from controller circuitry needs to be effectively dissipated from the package. Maximum power dissipation allowed for the package is calculated by: Where TJ(max) is 125°C TA(max) is the maximum ambient temperature in the system θJA is the thermal resistance from the silicon junction to the ambient This thermal resistance strongly depends on board layout. The TPS51117 is assembled in a standard TSSOP package and the heat mainly moves to the board through its leads. Certain points must be considered before starting a layout work using the TPS51117. Connect the RC low-pass filter from 5-V supply to V5FILT, 300 kΩand 1 µF are recommended. Place the filter capacitor close to the IC, within 12 mm (0.5 inches) if possible. Connect the overcurrent setting resistors from TRIP to GND close to the IC, right next to the IC, if possible. The trace from TRIP to resistor and resistor to GND should avoid coupling to a high voltage switching node. The discharge path (VOUT) should have a dedicated trace to the output capacitor(s); separate from the output voltage sensing trace, and use a 1,5 mm (60 mils) or wider trace with no loops. Make sure the feedback current setting resistor (the resistor between VFB to GND) is tied close to the IC GND. The trace from this resistor to the VFB pin should be short and thin. Place on the component side and avoid vias between this resistor and the IC. Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use a 0.65 mm (25 mils) or wider trace. All sensitive analog traces and components such as VOUT, VFB, GND, EN_PSV, PGOOD, TRIP, V5FILT, and TON should be placed away from high-voltage switching nodes such as LL, DRVL, DRVH or VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. Gather the ground terminals of the VIN capacitor(s), VOUT capacitor(s), and the source of the low-side MOSFETs as close as possible. GND (signal ground) and PGND (power ground) should be connected strongly together near the IC. The PCB trace defined as LL node, which connects to the source of the high-side MOSFET, the drain of the low-side MOSFET, and the high-voltage side of the inductor, should be as short and wide as possible.

Figure 23. 1.05-V/10-A Application From VBAT Table 1. Typical Application Circuit Components

Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) TPS51117PW ACTIVE TSSOP PW Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS51117PWG4 ACTIVE TSSOP PW Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS51117PWR ACTIVE TSSOP PW 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS51117PWRG4 ACTIVE TSSOP PW 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2006 Addendum-Page 1

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M 0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153

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