TPS51116PWP

TPS51116_16 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 45

Technical content

0.9 V 10 mA VTT 0.9 V 2 A TPS51116RGE 20 19 VBST DRVH LL DRVL V5FILT VLDOIN VTTGND VTTSNS 7 8 VTT CS_GND 9 10 VDDQSET CS VDDQSNS 13PGOOD 1211 S5S3 GND MODE VTTREF COMP NC NC V5IN PGND 22 2124 23 5V_IN VDDQ 1.8 V 10 A VIN IRF7832 IRF7821 Ceramic 2/C012110 µF Ceramic 0.033 µF Ceramic 0.1 µF 1 µH SP−CAP 2/C0121150 µF Ceramic 2/C012110 µF Ceramic 1 µF Ceramic 1 µF 100 kΩ 5.1 kΩ 5.1 Ω UDG−04153 TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 CompleteDDR,DDR2,DDR3,andLPDDR3MemoryPowerSolution SynchronousBuckController,3-ALDO,BufferedReference Check for Samples: TPS51116 1FEATURES DESCRIPTION The TPS51116 provides a complete power supply for 2• Synchronous Buck Controller (VDDQ) DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, and– Wide-Input Voltage Range: 3.0-V to 28-V LPDDR3 memory systems. It integrates a – D−CAP™ Mode with 100-ns Load Step synchronous buck controller with a 3-A sink/source Response tracking linear regulator and buffered low noise reference. The TPS51116 offers the lowest total– Current Mode Option Supports Ceramic solution cost in systems where space is at aOutput Capacitors premium. The TPS51116 synchronous controller runs– Supports Soft-Off in S4/S5 States fixed 400-kHz, pseudo-constant frequency PWM with – Current Sensing from RDS(on) or Resistor an adaptive on-time control that can be configured in – Equipped with Powergood, Overvoltage (2 × 10 μF) of ceramic output capacitance. In Protection and Undervoltage Protection addition, the LDO supply input is available externally to significantly reduce the total power losses. The• 3-A LDO (VTT), Buffered Reference (VREF) TPS51116 supports all of the sleep state controls– Capable to Sink and Source 3 A placing VTT at high-Z in S3 (suspend to RAM) and – LDO Input Available to Optimize Power discharging VDDQ, VTT and VTTREF (soft-off) in Losses S4/S5 (suspend to disk). TPS51116 has all of the protection features including thermal shutdown and is– Requires only 20-μF Ceramic Output offered in both a 20-pin HTSSOP PowerPAD™Capacitor package and 24-pin 4×4 QFN.– Buffered Low Noise 10-mA VREF Output – Accuracy ±20 mV for both VREF and VTT APPLICATIONS – Supports High-Z in S3 and Soft-Off in S4/S5 • DDR/DDR2/DDR3/LPDDR3 Memory Power – Thermal Shutdown Supplies

• SSTL-2, SSTL-18, SSTL-15 and HSTL Termination Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2D-CAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2014, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) MINIMUMORDERABLE PART OUTPUTTA PACKAGE PINS ORDERNUMBER SUPPLY QUANTITY TPS51116PWP Tube 70 Plastic HTSSOP TPS51116PWPR 20 Tape-and-reel 2000PowerPAD (PWP) TPS51116PWPRG4 Tape-and-reel 2000 TPS51116RGE Tube 90-40°C to 85°C LargePlastic QUAD Flat Pack TPS51116RGER 300024 tape-and-reel(QFN) SmallTPS51116RGET 250tape-and-reel (1) All packaging options have Cu NIPDAU lead/ball finish. ABSOLUTE MAXIMUM RATINGS(1) over operating free-air temperature range unless otherwise noted MIN MAX UNIT VBST –0.3 36 VBST wrt LL –0.3 6 VIN Input voltage range VCS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET, –0.3 6V5FILT PGND, VTTGND, CS_GND –0.3 0.3 DRVH –1.0 36 VOUT Output voltage range LL –1.0 30 V COMP, DRVL, PGOOD, VTT, VTTREF –0.3 6 TA Operating ambient temperature range –40 85 Tstg Storage temperature –55 150 (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. DISSIPATION RATINGS DERATING FACTOR ABOVETA < 25°C POWER RATING TA = 85°C POWER RATINGPACKAGE TA = 25°C(W) (W)(mW/°C) 20-pin PWP 2.53 25.3 1.01 24-pin RGE 2.20 22.0 0.88

2 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Supply voltage, V5IN, V5FILT 4.75 5.25 V VBST, DRVH –0.1 34 LL –0.6 28 VLDOIN, VTT, VTTSNS, VDDQSNS –0.1 3.6 Voltage range VVTTREF –0.1 1.8 PGND, VTTGND, CS_GND –0.1 0.1 S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, –0.1 5.25DRVL Operating free-air temperature, TA –40 85 °C Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT TA = 25°C, No load, VS3 = VS5 = 5 V,IV5IN1 Supply current 1, V5IN(1) 0.8 2 mACOMP connected to capacitor TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,IV5IN2 Supply current 2, V5IN(1) 300 600COMP connected to capacitor TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V,IV5IN3 Supply current 3, V5IN(1) 240 500VCOMP = 5 V μAIV5INSDN Shutdown current, V5IN(1) TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0 IVLDOIN1 Supply current 1, VLDOIN TA = 25°C, No load, VS3 = VS5 = 5 V 1 10 IVLDOIN2 Supply current 2, VLDOIN TA = 25°C, No load, VS3 = 5 V, VS5 = 0 V, 0.1 10 IVLDOINSDN Standby current, VLDOIN TA = 25°C, No load, VS3 = VS5 = 0 V 0.1 1.0 VTTREF OUTPUT VVTTREF Output voltage, VTTREF VVDDQSNS/2 V -10 mA < IVTTREF < 10 mA, VVDDQSNS = 2.5 V, -20 20Tolerance to VVDDQSNS/2 -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.8 V, -18 18Tolerance to VVDDQSNS/2 VVTTREFTOL Output voltage tolerance mV -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.5 V, -15 15Tolerance to VVDDQSNS/2 -10 mA < IVTTREF < 10 mA, VVDDQSNS = 1.2 V, –12 12Tolerance to VVDDQSNS/2 VVTTREFSRC Source current VVDDQSNS = 2.5 V, VVTTREF = 0 V -20 -40 -80 mA VVTTREFSNK Sink current VVDDQSNS = 2.5 V, VVTTREF = 2.5 V 20 40 80 VDDQ OUTPUT TA = 25°C, VVDDQSET = 0 V, No load 2.465 2.500 2.535 0°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load(2) 2.457 2.500 2.543 -40°C ≤ TA ≤ 85°C, VVDDQSET = 0 V, No load (2) 2.440 2.500 2.550 TA = 25°C, VVDDQSET = 5 V, No load (2) 1.776 1.800 1.824VVDDQ Output voltage, VDDQ V 0°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.769 1.800 1.831 -40°C ≤ TA ≤ 85°C, VVDDQSET = 5V, No load(2) 1.764 1.800 1.836 -40°C ≤ TA ≤ 85°C, Adjustable mode, No 0.75 3.0load(2) TA = 25°C, Adjustable mode 742.5 750.0 757.5 mV VVDDQSET VDDQSET regulation voltage 0°C ≤ TA ≤ 85°C, Adjustable mode 740.2 750.0 759.8 -40°C ≤ TA ≤ 85°C, Adjustable mode 738.0 750.0 762.0 VVDDQSET = 0 V 215 kΩ RVDDQSNS Input impedance, VDDQSNS VVDDQSET = 5 V 180 Adjustable mode 460 VVDDQSET = 0.78 V, COMP = Open -0.04 IVDDQSET Input current, VDDQSET μA VVDDQSET = 0.78 V, COMP = 5 V -0.06 VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,IVDDQDisch Discharge current, VDDQ 10 40 mAVMODE = 0 V VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V,IVLDOINDisch Discharge current, VLDOIN 700 mAVMODE = 0.5 V VTT OUTPUT VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V 1.25 VVTTSNS Output voltage, VTT VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V 0.9 V VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.5 V 0.75 (1) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices. (2) Specified by design. Not production tested.

4 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, -20 20IVTT = 0 A VTT output voltage tolerance VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V,VVTTTOL25 -30 30 mVto VTTREF |IVTT| < 1.5 A VVDDQSNS = VVLDOIN = 2.5 V, VS3 = VS5 = 5 V, -40 40|IVTT| < 3 A VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, -20 20IVTT = 0 A VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V,VVTTTOL18 -30 30 mVto VTTREF |IVTT| < 1 A VVDDQSNS = VVLDOIN = 1.8 V, VS3 = VS5 = 5 V, -40 40|IVTT| < 2 A VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, -20 20IVTT = 0 A VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V,VVTTTOL15 -30 30 mVto VTTREF |IVTT| < 1 A VVDDQSNS = VVLDOIN = 1.5 V, VS3 = VS5 = 5 V, -40 40|IVTT| < 2 A VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, -20 20IVTT = 0 A VTT output voltage tolerance VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V,VVTTTOL12 -30 30 mVto VTTREF |IVTT| < 1 A VVDDQSNS = VVLDOIN = 1.2 V, VS3 = VS5 = 5 V, -40 40|IVTT| < 1.5 A VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V 1.5 2.2 3.0 A VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ 1.5 2.2 3.0 IVTTLK Leakage current, VTT VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 -10 10 IVTTBIAS Input bias current, VTTSNS VS3 = 5 V, VVTTSNS = VVDDQSNS /2 -1 -0.1 1 μA IVTTSNSLK Leakage current, VTTSNS VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 -1 1 TA = 25°C, VS3 = VS5 = VVDDQSNS = 0 V,IVTTDisch Discharge current, VTT 10 17 mAVVTT = 0.5 V TRANSCONDUCTANCE AMPLIFIER gm Gain TA = 25°C 240 300 360 μS COMP maximum sink VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,ICOMPSNK 13current VVDDQSNS = 2.7 V, VCOMP = 1.28 V μA COMP maximum source VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,ICOMPSRC -13current VVDDQSNS = 2.3 V, VCOMP = 1.28 V VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,VCOMPHI COMP high clamp voltage 1.31 1.34 1.37VVDDQSNS = 2.3 V, VCS = 0 V V VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V,VCOMPLO COMP low clamp voltage 1.18 1.21 1.24VVDDQSNS = 2.7 V, VCS = 0 V Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DUTY CONTROL tON Operating on-time VIN = 12 V, VVDDQSET = 0 V 520 tON0 Startup on-time VIN = 12 V, VVDDQSNS = 0 V 125 ns tON(min) Minimum on-time TA = 25°C (3) 100 tOFF(min) Minimum off-time TA = 25°C(3) 350 ZERO CURRENT COMPARATOR Zero current comparatorVZC -6 0 6 mVoffset OUTPUT DRIVERS Source, IDRVH = –100 mA 3 6 RDRVH DRVH resistance Sink, IDRVH = 100 mA 0.9 3 Ω Source, IDRVL = –100 mA 3 6 RDRVL DRVL resistance Sink, IDRVL = 100 mA 0.9 3 LL-low to DRVL-on(3) 10 tD Dead time ns DRVL-off to DRVH-on(3) 20 INTERNAL BST DIODE VFBST Forward voltage VV5IN-VBST , IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V,IVBSTLK VBST leakage current 0.1 1.0 μATA = 25°C PROTECTIONS VPGND-CS , PGOOD = HI, VCS < 0.5 V 50 60 70 VOCL Current limit threshold mV VPGND-CS , PGOOD = LO, VCS < 0.5 V 20 30 40 TA = 25°C, VCS > 4.5 V, PGOOD = HI 9 10 11 ITRIP Current sense sink current μA TA = 25°C, VCS > 4.5 V, PGOOD = LO 4 5 6 TRIP current temperature RDS(on) sense scheme, On the basisTCITRIP 4500 ppm/°Ccoefficient of TA = 25°C(3) Overcurrent protection (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV,VOCL(off) -5 0 5COMP offset VCS > 4.5 V (3) mV Current limit threshold settingVR(trip) VV5IN-CS (3) (4) 30 150range POWERGOOD COMPARATOR PG in from lower 92.5% 95.0% 97.5% VTVDDQPG VDDQ powergood threshold PG in from higher 102.5% 105.0% 107.5% PG hysteresis 5% IPG(max) PGOOD sink current VVTT = 0 V, VPGOOD = 0.5 V 2.5 7.5 mA tPG(del) PGOOD delay time Delay for PG in 80 130 200 μs (3) Specified by design. Not production tested. (4) V5IN references to PWP packaged devices should be interpreted as V5FILT references to RGE packaged devices.

6 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD No discharge 4.7 VTHMODE MODE threshold Non-tracking discharge 0.1 2.5 V output 0.08 0.15 0.25 V VTHVDDQSET VDDQSET threshold voltage 1.8 V output 3.5 4.0 4.5 VIH High-level input voltage S3, S5 2.2 VIL Low-level input voltage S3, S5 0.3 VIHYST Hysteresis voltage S3, S5 0.2 VINLEAK Logic input leakage current S3, S5, MODE -1 1 μA VINVDDQSET Input leakage/ bias current VDDQSET -1 1 UNDERVOLTAGE AND OVERVOLTAGE PROTECTION OVP detect 110% 115% 120%VDDQ OVP trip thresholdVOVP voltage Hysteresis 5% VDDQ OVP propagationtOVPDEL 1.5 μsdelay (5) UVP detect 70% VUVP Output UVP trip threshold Hysteresis 10% Output UVP propagationtUVPDEL 32delay(5) cycle tUVPEN Output UVP enable delay(5) 1007 THERMAL SHUTDOWN Shutdown temperature 160 TSDN Thermal SDN threshold (5) °C Hysteresis 10 (5) Specified by design. Not production tested. Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NO. I/O DESCRIPTION NAME PWP RGE Output of the transconductance amplifier for phase compensation. Connect to V5IN to disableCOMP 8 6 I/O gm amplifier and use D-CAP™ mode. Current sense comparator input (-) for resistor current sense scheme. Or overcurrent trip CS 15 16 I/O voltage setting input for RDS(on) current sense scheme if connected to V5IN (PWP), V5FILT (RGE) through the voltage setting resistor. DRVH 19 21 O Switching (top) MOSFET gate drive output. DRVL 17 19 O Rectifying (bottom) MOSFET gate drive output. GND 5 3 - Signal ground. Connect to minus terminal of the VTT LDO output capacitor. CS_GND - 17 – Current sense comparator input (+) and ground for powergood circuit. Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on)LL 18 20 I/O current sense. MODE 6 4 I Discharge mode setting pin. See VDDQ and VTT Discharge Control section. – 7 – NC No connect. – 12 – Ground for rectifying (bottom) MOSFET gate driver (PWP, RGE). Also current sensePGND 16 18 – comparator input(+) and ground for powergood circuit (PWP). Powergood signal open drain output, In HIGH state when VDDQ output voltage is within thePGOOD 13 13 O target range. S3 11 10 I S3 signal input. S5 12 11 I S5 signal input. V5IN 14 15 I 5-V power supply input for internal circuits (PWP) and MOSFET gate drivers (PWP, RGE). Filtered 5-V power supply input for internal circuits. Connect R-C network from V5IN toV5FILT - 14 I V5FILT. VBST 20 22 I/O Switching (top) MOSFET driver bootstrap voltage input. VDDQSET 10 9 I VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section. VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge VDDQSNS 9 8 I/O current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to V5IN or GND. VLDOIN 1 23 I Power supply for the VTT LDO. VTT 2 24 O Power output for the VTT LDO. VTTGND 3 1 - Power ground output for the VTT LDO. VTTREF 7 5 O VTTREF buffered reference output. Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO outputVTTSNS 4 2 I capacitor.

8 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

(TOP VIEW) NC VDDQSNS VDDQSET NC RGE P ACKAGE (BOTT OM VIEW) VTT VLDOIN VBST DRVH LL DRVL 1 2 3 4 5 6 18 17 16 15 14 13 VTTGND VTTSNS GND MODE VTTREF COMP PGND CS_GND CS V5IN V5FILT PGOOD TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com FUNCTIONAL BLOCK DIAGRAM (PWP)

10 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 FUNCTIONAL BLOCK DIAGRAM (RGE) Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a 10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin HTSSOP package or a 24-pin QFN package. Each of these rails generates VDDQ, VTTREF and VTT that required with DDR/DDR2/DDR3/LPDDR3 memory systems. The switch mode power supply (SMPS) portion employs external N-channel MOSFETs to support high current for DDR/DDR2/DDR3/LPDDR3 memory VDD/VDDQ. The preset output voltage is selectable from 2.5 V or 1.8 V. User-defined output voltage is also possible and can be adjustable from 0.75 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-μF (two 10-μF in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within ±1% of VDDQ. VTT output tracks VTTREF within ±20 mV at no load condition while ±40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge functions can be disabled by selecting non-discharge mode. VDDQ SMPS, Dual PWM Operation Modes The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports two control schemes which are a current mode and a proprietary D-CAP™ mode. D-CAP™ mode uses internal compensation circuit and is suitable for low external component count configuration with an appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as ceramic or specialty polymer capacitors. These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN, TPS51116 works in the D-CAP™ mode, otherwise it works in the current mode. VDDQ output voltage is monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section). At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback information indicates insufficient output voltage and inductor current information indicates below the overcurrent limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. In the current mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and when the inductor current signal comes lower than the target current level, the comparator provides SET signal to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support various types of output MOSFETs and capacitors. In the D-CAP™ mode, the transconductance amplifier is disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides SET signal to initiate the next ON state.

12 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

IOUT(LL) /C00431 2 /C0032L /C0032f/C0032 (VIN /C0042V OUT )/C0032V OUT V IN TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 VDDQ SMPS, Light Load Condition TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1: where

• f is the PWM switching frequency (400 kHz) (1) Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at IOUT(LL)/10 and 4 kHz at IOUT(LL)/100. Low-Side Driver The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is represented by the internal resistance, which is 3 Ω for V5IN to DRVL and 0.9 Ω for DRVL to PGND. A dead- time to prevent shoot through is internally generated between high-side MOSFET off to low-side MOSFET on, and low-side MOSFET off to high-side MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package. High-Side Driver The high-side driver is designed to drive high-current, low on-resistance, N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and LL pins. The drive capability is represented by the internal resistance, which is 3 Ω for VBST to DRVH and 0.9 Ω for DRVH to LL. Current Sensing Scheme In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the low-side MOSFET and PGND. CS pin is connected to the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin. For RDS(on) sensing scheme, CS pin should be connected to V5IN (PWP), or V5FILT (RGE) through the trip voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-μA ITRIP current and the trip level is set to the voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that LL pin should be connected to the drain terminal of the low-side MOSFET. ITRIP has 4500ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the low-side MOSFET. Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPS51116

TPS51116 includes an adaptive on-time control scheme and does not have a dedicated oscillator on board. proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. output voltage scheme for a DDR3 (VVDDQ= 1.5 V) or LPDDR3 (VVDDQ= 1.2 V) application. Table 1. VDDQSET and Output Voltages capacitors are enough to keep tracking the VTTREF within ±40 mV at all conditions including fast load transient. When VTT is not required in the design, following treatment is strongly recommended.

• Connect VLDOIN to VDDQSNS.
• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND and MODE to GND (Non-tracking discharge mode as shown in Table 3)
• Maintain a 0.033-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1 kΩ of resistance. A typical circuit for this application is shown in Figure 1 (1) VVDDQ≥ 1.2 V when used as VLDOIN. (2) Including DDR3 and LPDDR3

14 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

4 VTTSNS

Figure 1. Application Circuit When VTT Is Not Required Table 2. Sleep Mode Control Using the S3 and S5 Pins target voltage), then turns off powergood open-drain MOSFET.

Figure 2. VDDQ Soft-Start and Powergood Timing Soft-start duration, tVDDQSS, tVTTSS are functions of output capacitances.

• IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5 (2) where
• IVTTOCL = 2.2 A (typ) (3) In both Equation 2 and Equation 3 , no load current during start-up are assumed. Note that both switchers and the LDO do not start up with full load condition.

16 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3. Table 3. Discharge Selection and the operation mode is changed to the non-tracking-discharge mode. connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly. TPS51116 does not discharge any output charge. section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV. current at overcurrent threshold, IOCP, can be calculated as shown in Equation 5.

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com Overvoltage and Undervoltage Protection for VDDQ TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON. Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the high-side MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116 latches OFF both top and low-side MOSFETs. This function is enabled after 1007 cycles of SMPS operation to ensure startup. V5IN (PWP), V5FILT (RGE) Undervoltage Lockout (UVLO) Protection TPS51116 has 5-V supply undervoltage lockout protection (UVLO). When the V5IN (PWP) voltage or V5FILT (RGE) voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a non- latch protection. V5IN (PWP), V5FILT (RGE) Input Capacitor Add a ceramic capacitor with a value between 1.0 μF and 4.7 μF placed close to the V5IN (PWP) pin or V5FILT (RGE) pin to stabilize 5 V from any parasitic impedance from the supply. Thermal Shutdown TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160°C (typ), SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the device is cooled down by about 10°C.

18 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

/C0119P2 /C00431 /C0466C O /C0032RL /C0467 /C0119P1 /C00431 /C0466C C /C0032R O /C0467 H 3(s)/C0043 (1/C0041s /C0032C O /C0032ESR) /C04661 /C0041s /C0032C O /C0032RL /C0467/C0032RL R S H 2(s)/C0043 /C0042gm /C0032 R O /C04661 /C0041s /C0032C C /C0032R C /C0467 /C04661 /C0041s /C0032C C /C0032R O /C0467 /C04661 /C0041s /C0032C C2 /C0032R C /C0467 H 1(s)/C0043R2 (R2 /C0041R1 ) H(s)/C0043H 1(s)/C0032H 2(s)/C0032H 3(s) TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014

APPLICATION INFORMATION

Loop Compensation and External Parts Selection Current Mode Operation A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the transfer function of the whole system. Because current mode scheme directly controls the inductor current, the modulator can be linearized as shown in Figure 3. Figure 3. Linearizing the Modulator behaviors, can be improved by using smaller inductance without affecting the loop stability. Total open loop transfer function of the whole system is given by Equation 6. There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.

O C C ESRC R /c180/c61 /C0119z2 /C00431 /C0466C O /C0032ESR /C0467/C0043/C0119p3 /C00431 /C0466C C2 /C0032R C /C0467 R C /C00432.8/C0032V OUT /C0032C O [/C0109F]/C0032R S [m/C0087] R C /C01182/C0112/C0032f0 /C0032 V OUT 0.75 /C0032 C O gm /C0032R S IIND(peak)/C0043 V TRIP R DS(on) /C00411 L /C0032f/C0032 /C0466V IN(max)/C0042V OUT /C0467/C0032V OUT V IN(max) L /C00431 IIND(ripple)/C0032f/C0032 /C0466V IN(max)/C0042V OUT /C0467/C0032V OUT V IN(max) /C00432 IOUT(max) /C0032f/C0032 /C0466V IN(max)/C0042V OUT /C0467/C0032V OUT V IN(max) f0 /C00431 2/C0112/C0032R1 R1 /C0041R2 /C0032gm C O /C0032 R C R S /C00431 2/C0112/C00320.75 V OUT /C0032gm C O /C0032 R C R S /C0119Z2 /C00431 /C0466C O /C0032ESR /C0467 /C0119Z1 /C00431 /C0466C C /C0032R C /C0467 /C0119P3 /C00431 /C0466C C2 /C0032R C /C0467 TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com (12) (13) (14) Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by Equation 15. (15) Based on small signal analysis above, the external components can be selected by following manner. 1. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. (16) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17. (17) 2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency more at high-load conditions. When using external resistor current sensing, there is no restriction for low RDS(on). However, the current sensing resistance RS itself affects the efficiency 3. Choose output capacitor(s). When organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP) are used, ESR to achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR times the load current step for a fast transient load response. When ceramic capacitor(s) are used, the ESR is usually small enough to meet ripple requirement. In contrast, transient undershoot and overshoot driven by output capacitance becomes the key factor in determining the capacitor(s) required. 4. Determine f0 and calculate RC using Equation 18. Note that higher RC shows faster transient response in cost of unstableness. If the transient response is not enough even with high RC value, try increasing the out put capacitance. Recommended f0 is fOSC/4. Then RC can be derived by Equation 19. (18) (19) 5. Calculate CC2 . Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. When ceramic capacitor(s) are used, no need for CC2. (20) (21)

20 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

1. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it

by Cc and Rc. Recommended ωz1 is 10 times lower to the f0 frequency.

1. When using adjustable mode, determine the value of R1 and R2. .

A buck converter system using D-CAP™ Mode can be simplified as below. Figure 4. Linearizing the Modulator For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency. amount of feedback signal needs to be provided by external circuit to reduce jitter level. at the output node. The output capacitor’s ESR should meet this requirement. The external components selection is much simple in D-CAP™ mode.

1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the

Current Mode Operation section.

1. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are

TJ(max)/C0042TA(max) /C0113JA W DSNK /C0043V VTT /C0032IVTT W DSRC /C0043/C0466V VLDOIN /C0042V VTT /C0467/C0032IVTT ESR /C0043 V OUT /C00320.015 IRIPPLE /C00320.75/C0091VOUT IOUT(max) /C003260 [m/C0087] TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com Equation 25. (25) Thermal Design Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and sink directions generate power dissipation from the part. In the source phase, potential difference between VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC. (26) In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK, is calculated by Equation 27: (27) Because this device does not sink AND source the current at the same time and IVTT varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value. Another power consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN supply can be estimated as 1.5 mA or less at normal operational conditions. These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by Equation 28, (28) where

• TJ(max) is 125°C
• TA(max) is the maximum ambient temperature in the system
• θJA is the thermal resistance from the silicon junction to the ambient This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced PowerPAD™ package that has exposed die pad underneath the body. For improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 39.6°C/W, is achieved based on a 6.5 mm × 3.4 mm thermal land with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. Further information about PowerPAD™ and its recommended board layout is described in (SLMA002). This document is available at http:\\\\www.ti.com.

22 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 Layout Considerations Certain points must be considered before designing a layout using the TPS51116.

• PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET and high-voltage side of the inductor, should be as short and wide as possible.
• Consider adding a small snubber circuit, consisting of a 3-Ω resitor and a 1-nF capacitor, between LL and PGND in case a high-frequency surge is observed on the LL voltage waveform.
• All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage switching nodes such as LL, DRVL or DRVH nodes to avoid coupling.
• VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide connection.
• The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s).
• Consider adding LPF at VTTSNS when the ESR of the VTT output capacitor(s) is larger than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines.
• Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current.
• GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point.
• Connect CS_GND (RGE) to source of rectifying MOSFET using Kevin connection. Avoid common trace for high-current paths such as the MOSFET to the output capacitors or the PGND to the MOSFET trace. When using an external current sense resistor, apply the same care and connect it to the positive side (ground side) of the resistor.
• PGND is the return path for rectifying MOSFET gate drive. Use 0.65 mm (25mil) or wider trace. Connect to source of rectifying MOSFET with shortest possible path.
• Place a V5FILT filter capacitor (RGE) close to the TPS51116, within 12 mm (0.5 inches) if possible.
• The trace from the CS pin should avoid high-voltage switching nodes such as those for LL, VBST, DRVH, DRVL or PGOOD.
• In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the package. Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPS51116

Figure 5. D-CAP™ Mode, PWP Package Figure 6. D-CAP™ Mode, RGE Package Table 4. D-CAP™ Mode Schematic Components

24 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

All data in the following graphs are measured from the PWP packaged device. Figure 9. Figure 10. Figure 11. Figure 12.

26 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Figure 17. Figure 18. Figure 19. Figure 20.

28 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Figure 25. Figure 26. Figure 27. Figure 28.

30 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Figure 33. Soft-Start Waveforms Tracking Discharge Figure 34. Soft-Stop Waveforms Non-Tracking Discharge Figure 35. Figure 36.

32 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

−40 −80 100 k 1 M 10 M −60 −20 −90 −45 180 135 −180 −135 f − Frequency − Hz Gain − dB Phase Gain IVTT = 1 A Phase − ° TI Information — Selective Disclosure TPS51116 www.ti.com SLUS609I –MAY 2004–REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) VTT BODE PLOT, SINK (DDR2) GAIN AND PHASE vs FREQUENCY Figure 37. Copyright © 2004–2014, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: TPS51116

TI Information — Selective Disclosure TPS51116 SLUS609I –MAY 2004–REVISED JANUARY 2014 www.ti.com Changes from Revision H (JULY 2009) to Revision I Page

34 Submit Documentation Feedback Copyright © 2004–2014, Texas Instruments Incorporated

Product Folder Links: TPS51116

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples TPS51116PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS51116 TPS51116PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS51116 TPS51116PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS51116 TPS51116PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS51116 TPS51116RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 51116 TPS51116RGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 51116 TPS51116RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 51116 TPS51116RGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS 51116 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 11-Apr-2013 Addendum-Page 2 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS51116 :

• Enhanced Product: TPS51116-EP NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51116PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS51116RGER VQFN RGE 24 3000 370.0 355.0 55.0 TPS51116RGER VQFN RGE 24 3000 367.0 367.0 35.0 TPS51116RGET VQFN RGE 24 250 195.0 200.0 45.0 TPS51116RGET VQFN RGE 24 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2016 Pack Materials-Page 2

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated