TPS5110PW

TPS5110_16 TI1 | Alldatasheet

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Technical content

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083/C0262/C0066/C0085/C0067/C0075 /C0080/C0087/C0077 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 /C0087/C0073/C0084/C0072 /C0078/C0077/C0079/C0083 /C0076/C0068/C0079 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 1www.ti.com

FEATURES

/C0068Switching Mode Step-Down dc-to-dc Controller With Fast LDO Controller /C0068Input Voltage Range Switcher: 4.5 V to 28 V LDO: 1.1 V to 3.6 V /C0068Output Voltage Range Switcher: 0.9 V to 3.5 V LDO: 0.9 V to 2.5 V /C0068Synchronous for High Efficiency /C0068Precision VREF (±1 % ) /C0068PWM Mode Control: Max. 500-kHz Operation /C0068High-Speed Error Amplifier /C0068Overcurrent Protection With Temperature Compensation Circuit /C0068Overvoltage and Undervoltage Protection /C0068Programmable Short-Circuit Protection

APPLICATIONS

/C0068Notebook PCs, PDAs /C0068Consumer Game Systems /C0068DSP Application SIMPLIFIED APPLICATION

DESCRIPTION

The TPS5110 provides one PWM-mode synchronous buck regulator controller (SBRC) and one low drop-out (LDO) regulator controller. The TPS5110 supports a low-voltage/high-current power supply for I/O and other peripherals in modern digital systems. The SBRC of the TPS5110 automatically adjusts from PWM mode to SKIP mode to maintain high efficiency under all load conditions. The LDO controller drives an external N-channel power MOSFET that realizes fast response and ultra-low dropout voltage. A unique overshoot protection circuit prevents a voltage hump at fast load decreasing transients. The current protection circuit for SBRC detects the drain-to-source voltage drop across the low-side and high-side power MOSFET while it is conducting. Also, the current protection circuit has a temperature coefficient to compensate for the R DS(on) variation of the MOSFET. This resistor-less current protection simplifies the system design and reduces the external parts count. The LDO controller includes current-limit protection. Other features, such as undervoltage lockout, power good, overvoltage, undervoltage, and programmable short-circuit protection promote system reliability. t− time 100 µs/div IOUT = 0 A to 3 A (1 A/ div) C OUT = 47 µF VOUT = 1.5 V (50 mV/ div) LDO Load Transient Response UDG-02052

1 INV

6 GND

12 INV_LDO

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN VO1 5 V INPUT VO2 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  2002, Texas Instruments Incorporated

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 2 www.ti.com

ORDERING INFORMATION

PACKAGED DEVICES (1) TA PLASTIC TSSOP (PW) −40°C to 85°C TPS5110PW (24) (1) The PW package is also available taped and reeled. Add an R suffix to the device type (i.e. TPS5110PWR) INV FB SOFTSTART PWM_SEL CT GND REF STBY STBY_LDO FLT POWERGOOD INV_LDO LH OUT_u LL OUT_d OUTGND TRIP VIN_SENS E REG5V_IN LDO_IN LDO_CUR LDO_GAT E LDO_OUT PW PACKAGE (TOP VIEW)

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 3www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS5110 UNIT VIN_SENSE , STBY, STBY_LDO , TRIP, LL −0.3 to 30 Input voltage range, VI INV, SOFTSTART, PWM_SEL, CT, FLT, INV_LDO, LDO_OUT, LDO_CUR, LDO_IN, REG5V_IN −0.3 to 7 V LH −0.3 to 35 REF −0.3 to 3 V Output voltage range, VO FB, POWERGOOD, OUT_d −0.3 to 7 V Output voltage range, VO LDO_GATE −0.3 to 9 V OUT_u −0.3 to 35 V Continuous total power dissipation See dissipation rating table Operating ambient temperature range, TA −40 to 85 °CStorage temperature range, Tstg −55 to 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage REG5V_IN 4.5 5.5 Supply voltage LDO_IN 1.1 3.6 VIN_SENSE 4.5 28 INV, INV_LDO, CT, PWM_SEL, SOFTSTART, FLT −0.1 6 POWERGOOD, FB, OUT_d −0.1 5.5 V Input voltage, VI LDO_CUR, LDO_OUT −0.1 3.5 V Input voltage, VI STBY, STBY_LDO, LL −0.1 28 OUT_u, LH −0.1 33 TRIP −0.1 28 LDO_GATE −0.1 8 Oscillator frequency, fOSC 300 500 kHz Operating free-air temperature, TA −40 85 /C0095C DISSIPATION RATINGS (THERMAL RESISTANCE = °C/W) PACKAGE (1) DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 85°C POWER RATING 24-PW 11.24 mW/°C 1404 mW 730 mW (2) These devices are mounted on a JEDEC high-k board (2 oz. traces on surface, 2-layer 1-oz plane inside). (Assume the maximum junction temperature is 150°C)

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 4 www.ti.com

ELECTRICAL CHARACTERISTICS

Over recommended free-air temperature range, VVIN_SENSE = 12 V and VREG5V_IN = 5 V (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT SECTION ICC Supply current REG5V_IN current, TA = 25/C0095C, VLDO_IN = 3.6 V, VCT = VINV = VINV_LDO = VPWM_SEL = 0 V 0.9 1.4 mA ICC(S)Shutdown current REG5V_IN current, VSTBY = VSTBY_LDO = 0 V 0.001 10.00 µA UNDERVOLTAGE LOCKOUT SECTION V(TLH)Low-to-high threshold voltage REG5V_IN voltage 3.6 4.2 V V(TLL)High-to-low threshold voltage REG5V_IN voltage 3.5 4.1 V VHYS Hysteresis REG5V_IN voltage 30 200 mV REFERENCE VOLTAGE SECTION VREF Reference voltage 0.85 V TA = 25/C0095C, I REF = 50 µA −1% 1% VREF (tol) Reference voltage tolerance 0/C0095C ≤ TA ≤ 85/C0095C, I REF = 50 µA -1.5% 1.5%VREF (tol) Reference voltage tolerance −40/C0095C ≤ TA ≤ 85/C0095C, I REF = 50 µA −2% 2% Reg(line) Line regulation IREF = 50 µA, 4.5 V ≤ V(REG5V_IN) ≤ 5.5 V 0.05 5 mV Reg(load) Load regulation 0.1 µA ≤ IREF ≤ 1 mA 0.15 5 mV CONTROL SECTION VIH High-level input voltage STBY, STBY_LDO, PWM_SEL 2.2 V VIL Low-level input voltage STBY, STBY_LDO, PWM_SEL 0.3 V OUTPUT VOLTAGE MONITOR SECTION OVP comparator threshold voltage SBRC, LDO 0.91 0.95 0.99 UVP comparator threshold voltage SBRC, LDO 0.51 0.55 0.59 V Powergood comparator 1, 4 threshold voltage 0.75 0.79 0.81 V Powergood comparator 2, 3 threshold voltage 0.88 0.91 0.94 Powergood propagation delay from INV and POWERGOOD high-to-low 1.2 sPowergood propagation delay from INV and INV_LDO to POWERGOOD POWERGOOD low-to-high 4 µs Timer latch current source UVP protection −1.5 −2.3 −3.1 ATimer latch current source OVP protection −80 −125 −180 µA OSCILLATOR SECTION fOSC Oscillator frequency PWM mode, C CT = 44 pF TA = 25/C0095C 300 kHz VOH CT high-level output voltage dc 1.0 1.1 1.2 VOH CT high-level output voltage fOSC = 300 kHz 1.17 V VOL CT low-level output voltage dc 0.4 0.5 0.6 V VOL CT low-level output voltage fOSC = 300 kHz 0.43

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 5www.ti.com Over recommended free-air temperature range, VVIN_SENSE = 12 V and VREG5V_IN = 5 V (unless otherwise specified). SBRC ERROR AMPLIFIER SECTION VIO Input offset voltage TA = 25/C0095C 2 10 mV Open loop voltage gain 50 dB Unity gain bandwidth 2.5 MHz ISNK Output sink current VFB = 1 V 0.2 0.7 mA ISRC Output source current VFB = 1 V −0.2 −0.9 mA DUTY CONTROL SECTION DUTY Maximum duty control fOSC = 300 kHz, V INV = 0 V 82% OUTPUT DRIVERS SECTION OUT_u sink current VOUT_u − VLL = 3 V 1.2 OUT_u source current VLH − VOUT_u = 3 V −1.2 A OUT_d sink current VOUT_d = 3 V 1.5 A OUT_d source current VOUT_d = 2 V −1.5 LDO_GATE sink current VLDO_GATE = 2 V 1.5 mA LDO_GATE source current VLDO_GATE = 2 V −1.4 mA ITRIP TRIP current TA = 25/C0095C 11.5 13.0 14.5 µA SOFT-START SECTION ISOFT Soft-start current −1.6 −2.3 −2.9 µA LDO ERROR AMPLIFIER SECTION VIO Input offset voltage TA = 25/C0095C, V LDO_IN = 3.3 V 2 10 mV Open loop voltage gain VLDO_IN = 3.3 V 50 dB Unity-gain bandwidth VLDO_IN = 3.3 V, C LOAD = 2000 pF 1.4 MHz LDO CURRENT LIMIT SECTION Current limit comparator threshold voltageVLDO_IN = 3.3 V 40 50 60 mV LDO OVERSHOOT PROTECTION SECTION LDO_OUT sink current VLDO_OUT = VLDO_GATE = 1.5 V 25 mA

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 6 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION NAME NO. I/O DESCRIPTION CT 5 I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator. FB 2 O Feedback output of error amplifier FLT 10 I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time up. GND 6 − Signal GND INV 1 I Inverting input of the SBRC error amplifier, skip comparator, OVP/UVP comparators and POWERGOOD comparator INV_LDO 12 I Inverting input of the LDO regulator, OVP/UVP comparators and POWERGOOD comparator LDO_CUR 15 I Current sense input of the LDO regulator. LDO_GATE 14 O Gate control output of an external MOSFET for LDO LDO_OUT 13 I/O LDO regulator’s output connection. If output voltage causes an over shoot at output current changes high to low quickly, it pulls out electrical charge from this pin. LDO_IN 16 I Input of LDO regulator and current sense input of LDO regulator LH 24 I/O Bootstrap capacitor connection for high-side gate driver LL 22 I/O High side gate driving return. Connect this pin to the junction of the high side and low side MOSFET(s) for floating drive configuration. This pin also is an input terminal for current comparator. OUT_d 21 O Gate drive output for low-side MOSFET(s) OUT_u 23 O Gate drive output for high-side MOSFET(s). OUTGND 20 − Ground for FET drivers. It is connected to the current limiting comparator’s negative input. POWERGOOD 11 O Power good open-drain output. PG comparators monitor both SBRC’s and LDO’s over voltage and under voltage. The threshold is ±7%. When either output is beyond this condition, POWERGOOD output goes low. When STBY or STBY_LDO goes high, the POWERGOOD pin’s output starts with high. POWER- GOOD also monitors REG5V_IN’s UVLO output. PWM_SEL 4 I PWM or auto PWM/SKIP modes select. H: auto PWM/SKIP L: PWM fixed REF 7 O 0.85-V reference voltage output. This 0.85-V reference voltage is used for setting the output voltage and the voltage protections. This reference voltage is regulated from REG5V_IN power supply. REG5V_IN 17 I External 5-V input. This input is a supply voltage for internal circuits. SOFTSTART 3 I/O External capacitor between SOFTSTART and GND sets SBRC soft−start time. STBY 8 I Standby control input for SBRC. SBRC can be switched into standby mode by grounding the STBY pin. STBY_LDO 9 I Standby control input for LDO regulator. LDO regulator can be switched into standby mode by grounding the STBY_LDO pin. TRIP 19 I External resistor connection for SBRC’s output current protection control. VIN_SENSE 18 I SBRC supply voltage monitor. Input range is 4.5 V to 28 V. This pin is for reference of current limit.

0.85 V UVLO

0.85 V +12 %

0.85 V −35 %

0.85 V −7 %

0.85 V +7 %

Figure 1. Block Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 8 www.ti.com DETAILED DESCRIPTION PWM operation The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. The output voltage of the SBRC is fed back to the inverting input (INV) of the error amplifier. The noninverting input is internally connected to a 0.85 V precise band gap reference circuit. The unity-gain bandwidth of the amplifier is 2.5 MHz. This decreases the amplifier delay during fast-load transients and contributes to a fast response. Loop gain and phase compensation is programmable by an external C, R network between the FB and INV pins. The output signal of the error amplifier is compared with a triangular wave to achieve the PWM control signal. The oscillation frequency of this triangular wave sets the switching frequency of the SBRC and is determined by the capacitor connected between the CT and GND pins. The PWM mode is used for the entire load range if the PWM_SEL pin is set LOW, or used in high-output current condition if auto PWM/SKIP mode is selected by setting the same pin to HIGH. SKIP mode operation The PWM_SEL pin selects either the auto PWM/SKIP mode or fixed PWM mode. If this pin is lower than 0.3 V, the SBRC operates in the fixed PWM mode. If 2.5 V (min.) or higher is applied, it operates in auto PWM/SKIP mode. In the auto PWM/SKIP mode, the operation changes from constant frequency PWM mode to an energy-saving SKIP mode automatically in accordance with load conditions. Using a MOSFET with ultra-low R DS(on) if the auto SKIP function is implemented is not recommended. The SBRC block has a hysteretic comparator to regulate the output voltage of the synchronous buck converter during SKIP mode. The delay from the comparator input to the driver output is typically 1.2 µs. In the SKIP mode, the frequency varies with load current and input voltage. high-side driver The high-side driver is designed to drive high current and low RDS(on) N-channel MOSFET(s). The current rating of the driver is 1.2 A at source and sink. When configured as a floating driver a 5-V bias voltage is delivered from external REG5V_IN supply. The instantaneous-drive current is supplied by the flying capacitor between the LH and LL pins since a 5-V power supply does not usually have low impedance. It is recommended to add a 5-Ω to 10-Ω resistor between the gate of the high-side MOSFET(s) and the OUT_u pin to suppress noise. The maximum voltage that can be applied between the LH and OUTGND pins is 33 V. When selecting the high-current rating MOSFET(s), it is important to pay attention to both gate-drive power dissipation and the rise/fall time against the dead-time between high-side and low-side drivers. The gate-drive power is dissipated from the controller device and it is proportional to the gate charge at Vgs = 5 V, PWM switching frequency and the numbers of all MOSFETs used for low-side and high-side switches. This gate drive loss should not exceed the maximum power dissipation of the device. low-side driver The low-side driver is designed to drive high-current and low RDS(on) N-channel MOSFET(s). The maximum drive voltage is 5 V from REG5V_IN pin. The current rating of the driver is typically 1.5 A at source and sink. Gate resistance is not necessary for the low-side MOSFET for switching noise suppression since it turns on after the parallel diode is turned on (ZVS). It needs the same dissipation consideration when using high-current rating MOSFET(s). Another issue that needs precaution is the gate threshold voltage. Even though the OUT_d pin is shorted to the OUTGND pin with low resistance when the low-side MOSFET(s) is OFF, high dv/dt at the LL pin during turnon of the high side arm generates voltage peak at the OUT_d pin through the drain to gate capacitance, Cdg, of the low-side MOSFET(s). To prevent a short period shoot-through during this switching event, the application designer should select MOSFET(s) with adequate threshold voltage.

during switching transitions. Typical value of the dead-time is 100 ns. and/or SYBY_LDO pins. The standby-mode current, when both controllers are off, can be as low as 1 nA. Table 1. Standby Logic (V soft-start time is easily calculated by the supply current and the capacitance value (see application information). voltages rise to the HIGH level simultaneously, then the LDO’s output follows the ramp of the SBRC’s output. external resistor connected between the VIN_SENSE and TRIP pins. ITRIP has a typical value of 13 µA at 25°C. compensate for temperature drift of the MOSFET on-resistance.

share the same FLT capacitor. high-side and low-side MOSFET drivers and the LDO. The latched state of each block is summarized in Table 2. timer is designed to be 50 times faster than the undervoltage protection timer described below. Table 2. Overvoltage Protection Logic controller is disabled when voltage across the pass transistor is less than 0.23 V (typ.).

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 11www.ti.com DETAILED DESCRIPTION undervoltage lockout (UVLO) When the REG5V_IN voltage decreases below about 4 V, the output stages of both the SBRC and the LDO are turned off. This state is not latched and the operation recovers immediately after the input voltage becomes higher than the turn-on value again. The typical hysteresis voltage is 100 mV. UVLO for LDO The LDO_IN voltage is monitored with a hysteretic comparator. When this voltage is less than 1 V, the UVLO circuit disables the UVP/OVP comparators that monitor the INV_LDO voltage. In case the SBRC over current protection is activated prior to that of the LDO’s, this protection function may also be observed. LDO control The LDO controller can drive an external N-channel MOSFET. This realizes a fast response as well as an ultra-low dropout voltage regulator. For example, it is easy to configure both a 1.8-V and a 1.5-V high-current power supply for core and I/O of modern digital processors, one from the SBRC and the other from the LDO. The LDO_IN voltage range is from 1.1 V to 3.6 V, and the output voltage is adjustable from 0.9 V to 2.5 V by an external resistor divider. Gain and phase of the high-speed error amplifier for this LDO control is internally compensated and is connected to the 0.85-V band-gap reference circuit. The gate driver buffer is supplied by VIN_SENSE voltage. In the relatively high-output voltage applications, make sure that output voltage plus threshold voltage of the pass transistor is less than the minimum VIN. More precisely, V VIN_SENSE /C00420.7 V/C0119V THN /C0041V LDO_OUT where V THN is the threshold voltage of N-channel MOSFET. The LDO controller is also equipped with OVP, UVP, over current limit and overshoot protection functions. overshoot protection − LDO In the event that load current changes from high to low very quickly, the LDO regulator output voltage may start to overshoot. In order to resist this phenomenon, the LDO controller has an overshoot protection function. If the LDO regulator output overshoots, the controller draws electrical charge out from LDO_OUT pin to hold it stable.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 16 www.ti.com TYPICAL CHARACTERISTICS Figure 16 −50 TJ − Junction Temperature − 0 50 100 150 0.0 0.2 0.6 0.8 1.2 0.4 1.0 VINV_LDO = 0.50 V VTLH VTHL LDO UVLO THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE Threshold Voltage − V NOTE: V VIN_SENSE = 12 V, VREG5V_IN = 5 V unless otherwise noted.

APPLICATION INFORMATION

The design shown in this application information is a reference design for a notebook PC application. An evaluation module (EVM) is available for customer testing and evaluation. This information allows a customer to fully evaluate the given design using the plug-in EVM shown in Figure17. For subsequent board revisions, the EVM design can be copied onto the system PCB to shorten the design cycle. The following key design procedures aid in the design of the notebook PC power supply using TPS5110. An optional circuit composed of Q04, R16, R22 and R24 can be used to increase temperature coefficient of the trip current, which is at the top in the page 18.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 17www.ti.com INV_LDO POWERGOOD FLT STBY_LDO STBY REF GND CT PWM_SEL SOFTSTART FB INV LDO_OUT LDO_GATE LDO_CUR LDO_IN REG5V_IN VIN_SENSE TRIP OUTGND OUT_d LL OUT_u LH U01 TPS5110PW OUT GND IN3 UA78M05 EXGND EX5V VO2 VOGND VO1 VINGND VIN C01A C01B D03 C19 C17C16 L01 D02C14(DUMMY) C15 Q01A Q01B Q02A Q02B D01 C13 R14 R13 C12 C24 Q03A Q03B R12A R12B R12C R24 R16 R22 Q04 NPN_2SC4617 R23 0 ohm R10 R11 C08 R09 R08 C07 C06 C05 C04 C03 R04 R07 0 ohm R01A R01B R02 C02 R03 R05 JP01 JP02 JP03 C10 C25 C26 C09 R15A R15B R15C C11 PWR_GOOD R15 0 ohm C01C JP04 Figure 17. EVM Typical Design

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 18 www.ti.com Table 4. EVM Input and Outputs

0.85 V, and the divider is composed of three resistors in the EVM design that are R01A, R01B and R03 for

switching regulator output; R10, R11 and R09 for LDO regulator output. of ohms for R11 can then be added to generate the desired final value.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 19www.ti.com The required value for the output-filter inductor can be calculated by using the equation: LOUT /C0043 /C0466VIN /C0042V O /C0467 k /C0032IOUT /C0032 V O VIN /C00321 fS Where LOUT is output filter inductor value (H), VIN is the input voltage (V), Iout is the maximum output current (A), fS is the switching frequency (Hz). Constant value k, a ratio of ripple current to output current, is typically in the range 0.2 to 0.3. For VO 1, the calculation for the maximum input voltage of 20 V, yields a value for L01 output inductor ripple current The output-inductor current can affect not only the efficiency, but also the output voltage ripple. The equation is exhibited below: IRIPPLE /C0043 VIN /C0042V O /C0042IO /C0032/C0466R DS(on)/C0041RI/C0467 LOUT /C0032 V O VIN /C00321 fS where IRIPPLE is the peak-to-peak ripple current (A) through the inductor; IO is the output current; RDS(on) is the on-time resistance of MOSFET (Ω); Rl is the inductor dc resistance (Ω). From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value. For the EVM design, the worst-case output ripple occurs with VIN = 20 V: Example: VIN = 20 V; V O = 1.8 V; IO = 6 A; RDS(on) = 25 mΩ; Rl = 10 mΩ; Fs = 300 kHz; LOUT = 2.8 µH. Then, the ripple current IRIPPLE = 1.93 A output capacitor selection (SBRC) Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the output filter sees the entire inductor-ripple current then: V PP /C0043IRIPPLE /C0032R ESR And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for the application.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 20 www.ti.com output capacitor RMS current (SBRC) Assuming the inductor-ripple current totally goes through the output capacitor to ground, the RMS current in the output capacitor can be calculated as: IO(rms)/C0043 IRIPPLE 12/C0504 where IO(rms) is maximum RMS current in the output capacitor (A); IRIPPLE is the peak-to-peak inductor-ripple current (A). Example: IRIPPLE = 1.93 A, therefore, IO(rms) = 0.56 A input capacitor RMS current (SBRC) Assuming the input current totally goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as: Ii(rms)/C0043IO 2 /C0032D /C0032(1/C0042D) /C00411

12 D /C0032IRIPPLE/C0504

where Ii(rms) is the input RMS current in the input capacitor (A); IO is the output current (A); IRIPPLE is the peak-to-peak output inductor-ripple current; D is the duty cycle and defined as VO /VI in this case. From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input capacitor ripple current. Example: I O = 6 A; D = 22.5 %; IRIPPLE = 1.6 A then, Ii(rms) = 2.5 A The input capacitors must be chosen so that together they can safely handle the input-ripple current. Depending on the input filtering and the dc input voltage source, not all the ripple current flows through the input capacitors, but some may be present on the input leads to the EVM. soft start The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is; C SOFT /C00432.3/C003210−6 /C0032 TSOFT 0.85 where C(soft) is the soft-start capacitor (µF) (C04 in EVM design): TSOFT is the start-up time (s). Example: TSOFT = 5 ms, therefore, CSOFT = 0.0135 µF.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 21www.ti.com current protection (SBRC) The current limit in TPS5110 is set using an internal current source and an external resistor (R13). The current limit protection circuit compares the drain-to-source voltage of the high-side and low-side drivers with respect to the set-point voltage. If the voltage up exceeds the limit during high-side conduction, the current-limit circuit terminates the high-side driver pulse. If the set point voltage is exceeded during low-side conduction, the low-side pulse is extended through the next cycle. Together this action has the effect of decreasing the output voltage until the under voltage protection circuit is activated and the fault latch is set and both the high and low-side MOSFET drivers are shut off. The equation below should be used for calculating the external resistor value for current protection set point: R CL /C0043 R DS(on)/C0032 /C0466ITRIP /C0041 IRIPPLE 2 /C0467 13 /C003210−6 where RCL is the external current limit resistor (R13); RDS(on) is the low-side MOSFET(Q02) on-time resistance. ITRIP is the required current limit. Example: RDS(on) = 25 mΩ, ITRIP = 6 A, IRIPPLE = 1.93 A, therefore, RCL = 13.4 kΩ. It should be noted that RDS(on) of a FET is highly dependent on temperature, so to insure full output at maximum operating temperature, the value of RDS(on) in the above equation should be adjusted. For maximum stability, it is recommended that the high-side MOSFET(s) has same, or slightly higher RDS(on) than the low-side MOSFET(s). If the low-side MOSFET(s) has a higher RDS(on), in certain low duty cycle applications it may be possible for the device to regulate at an output current higher than that set by the above equation by increasing the high side conduction time to compensate for the missed conduction cycle caused by the extension of the previous low-side pulse. timer latch The TPS5110 includes fault latch function with a user adjustable timer to latch the MOSFET drivers in case of a fault condition. When either the OVP or UVP comparator detect a fault condition, the timer starts to charge FLT capacitor (C07), which is connected with FLT pin 10. The circuit is designed so that for any value of FLT capacitor, the under-voltage latch time t (uvplatch) is about 50 times larger than the over-voltage latch time t(ovplatch). The equations needed to calculate the required value of the FLT capacitor for the desired over and under-voltage latch delay times are: C LAT /C00432.3/C003210/C00426 /C0032 t(uvplatch) 1.185 and C LAT /C0043125 /C003210/C00426 /C0032 t(ovplatch) 1.185 where CLAT is the external capacitor, t(uvplatch) is the time from UVP detection to latch. t(ovplatch) is the time from OVP detection to latch. For the EVM, t(uvplatch) = 5 ms and t(ovplatch) = 0.1 ms, so CLAT = 0.01 µF If the voltage on the FLT pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are set as follows: under-voltage protection The under-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage at either pin falls below 65% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If the fault condition persists beyond the time t (uvplatch), the fault latch is set and both the high side and low-side drivers, and LDO regulator drivers are forced OFF.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 22 www.ti.com The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the current-limit circuit limits the output current, then the output voltage goes below the target-output voltage and UVP comparator detects a fault condition as described above. over voltage protection The over-voltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage at either pin rises above 112% of the 0.85-V reference, the timer begins to charge the FLT capacitor. If the fault condition persists beyond the time t (ovplatch), the fault latch is set and the high-side drivers are forced OFF, while the low-side drivers are forced ON, and LDO regulator drivers are forced OFF. CAUTION: Do not set the FLT pin to a lower voltage (or GND) while the device is timing out an OVP or UVP event. If the FLT pin is manually set to a lower voltage during this time, output overshoot may occur. The TPS5110 must be reset by grounding STBY and STBY_LDO, or dropping down REG5V_IN. disablement of the protection function If it is necessary to inhibit the protection functions of the TPS5110 for troubleshooting or other purposes, the OCP , OVP and UVP circuits may be disabled.

• OCP(SBRC): Remove the current-limit resistors R13 to disable the current limit function.
• OCP(LDO): Short-circuit R12 to disable the current limit function.
• OVP , UVP: Grounding the FLT pin can disable OVP and UVP. output capacitor selection for LDO To keep stable operation of the LDO, capacitance of more than 33 µF and RESR of more than 30 mΩ are recommended for the output capacitor. power MOSFET selection for LDO Also, to keep stable operation of the LDO, lower input capacitance is recommended for the external power MOSFET. However, too small input capacitance may lead the feedback loop into unstable region. In such a case, the gate resistor of several hundred ohms keeps the LDO operation in the stable state. current protection for LDO If excess output current flows through sense resistor (R12) and the voltage drop exceeds 50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus activates UVP to start the FLT latch timer. When the set current is 4 A, the value of R12 is 12.5 mΩ.

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 23www.ti.com Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milli-amps to tens of amps, good power supply layout is much more difficult than most general PCB designs. The general design should proceed from the switching node to the output, then back to the driver section and, finally, parallel the low-level components. Below are specific points to consider before the layout of a TPS5110 design begins.

• A four-layer PCB design is recommended for design using the TPS5110. For the EVM design, the top layer contains the interconnection to the TPS5110, plus some additional signal traces. Layer 2 is fully devoted to the DRVGND plane. Layer 3 mainly has wide VIN and V O 1 pattern. The bottom layer is almost devoted to other GND plane including ANAGND, and the rest is to wide signal trace for VO 2.
• All sensitive analog components such as INV, REF, CT, GND, FLT and SOFTSTART should be reference to ANAGND.
• Ideally, all of the area directly under the TPS5110 chip should also be ANAGND.
• ANAGND and DRVGND should be isolated as much as possible, with a single point connection between them. UDG−02069

4 PWM_SEL

7 REF

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T

3 SOFTSTART

8 STBY

STBY_LDO

11 POWERGOOD

18VIN_SENSE V OGND ANAGND DRVGND Figure 18. Four-Layer PCB Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 24 www.ti.com low-side MOSFET(s)

• The source of low-side MOSFET(s) should be referenced to DRVGND, otherwise ANAGND is subject to the noise of the outputs.
• DRVGND should be connected to the main ground plane close to the source of the low-side FET.
• OUTGND should be placed close to the source of low-side MOSFET(s).
• The Schottky diode anode, the returns for the high-frequency bypass capacitor for the MOSFETs, and the source of the low-side MOSFET(s) traces should be routed as close together as possible. UDG−02070

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T

10 FLT

9 STBY_LDO

18VIN_SENSE V OGND ANAGND DRVGND Figure 19. Low-Side MOSFETs Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 25www.ti.com

• Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably reduce the noise at the LL node, improving the performance of the current limit function.
• The connection from LL to the power MOSFETs should be as short and wide as possible. UDG−02071

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T 18VIN_SENSE V OGND ANAGND DRVGND Figure 20. Connections From the Drivers to the Gate Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 26 www.ti.com

• The bypass capacitor for VIN_SENSE should be placed close to the TPS5110.
• The bulk-storage capacitors across VIN should be placed close to the power MOSFETs. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side MOSFET(s) and to the source of the low-side MOSFET(s).
• For aligning phase between the drain of high-side MOSFET(s) and the TRIP pin, and for noise reduction, a 0.1-µF capacitor should be placed in parallel with the trip resistor. UDG−02072

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T 18VIN_SENSE V OGND ANAGND DRVGND Figure 21. Bypass Capacitor Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 27www.ti.com

• The bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5110.
• LH and LL should be routed close to each other to minimize differential-mode noise coupling to these traces.
• LH and LL should not be routed near the control pin area (ex. INV, FB, REF, etc.). UDG−02073

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T 18VIN_SENSE V OGND ANAGND DRVGND Figure 22. Bootstrap Capacitor Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 28 www.ti.com

• The output voltage sensing trace should be isolated by either ground plane.
• The output voltage sensing trace should not be placed under the inductors on same layer.
• The feedback components should be isolated from output components, such as, MOSFETs, inductors, and output capacitors. Otherwise the feedback signal line is susceptible to output noise.
• The resistors for set up output voltage should be referenced to ANAGND.
• The INV trace should be as short as possible. UDG−02074

OUT_u REG5V_IN LL OUT_d LDO_IN LDO_CUR LDO_GATE LDO_OUT TPS5110PW VIN V O1 EX5V V O2 2F B 5C T 18VIN_SENSE V OGND ANAGND DRVGND Figure 23. Output Voltage Diagram

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 33www.ti.com Table 5. Bill of Materials

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 34 www.ti.com Bill of Materials (continued) IC IC01 1 SSOP−24 TI TPS5110PWIC IC02 Removed Jumper JP01 1 Header, straight, 2-pin Morex 22−28−4023Jumper JP01 1 Jumper, shunt Morex 15−29−1025 JP02, JP03 2 SW, 7x4.5mm Nikkai G−12AP JP04 1 Header, straight, 3-pin Morex 22−28−4033 JP04 1 Jumper, shunt Morex 15−29−1025 Contact EX5V, EXGND 4 MKDS1.5/2−5.08 Contact VIN, VINGND 4 Phoenix MKDS1.5/2−5.08 VO1, VO2, VOGND 3 Phoenix MKDS1.5/3−5.08 NOTE: Since the FDS6690S (Q02B) includes an integrated Schottky diode, D02 can be removed. test setup Power SupplyV SBRC Load LDO Load 5 V Power Supply A + V V V EX5V EXGND VO2 VOGND VO1 VINGND VIN TPS5110 EVM A A Figure 40. Schematic Diagram of the Test Setup

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 35www.ti.com Figure 41. EVM Board Top Layer

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 36 www.ti.com Figure 42. EVM Board Second Layer

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 37www.ti.com Figure 43. EVM Board Third Layer

/C0084/C0080/C0083/C0053/C0049/C0049/C0048 SLVS025B − APRIL 2002 − REVISED JULY 2004 38 www.ti.com Figure 44. EVM Board Bottom Layer

www.ti.com 20-Nov-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS5110PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PS5110 TPS5110PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PS5110 TPS5110PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PS5110 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 20-Nov-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5110PWR TSSOP PW 24 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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