TPS5103IDBR

TPS5103_08 TI1 | Alldatasheet

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OUT_u LL OUT_d OUTGND TRIP VCC_SENSE V CC VREF5 VREG5V_IN DB PACKAGE (TOP VIEW) TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 Step-Down DC-DC Converter /C0068 Three Operation-Modes – Heavy Load: – Fixed Frequency PWM – Hysteretic (User Selectable) – Light Load: – Skip Mode /C0068 4.5-V to 25-V Input Voltage Range /C0068 Adjustable Output Voltage Down to 1.2 V /C0068 95% Efficiency /C0068 Standby Control /C0068 Overcurrent Protection /C0068 UVLO for Internal 5-V Regulation /C0068 Low-Standby Current. . . 0.5 mA Typical /C0068 TA = –40°C to 85°C

description

The TPS5103 is a synchronous buck dc/dc controller, designed for notebook PC system power. The controller has three user-selectable operation modes available: hysteretic mode, fixed-frequency PWM control, or SKIP control. In high-current applications, where fast transient response is advantageous for reducing bulk capacitance, the hysteretic mode is selected by connecting the R T pin to VREF5. Selecting the PWM/SKIP modes for less demanding transient applications is ideal for conserving notebook battery life under light load conditions. The device includes high-side and low-side MOSFET drivers capable of driving low r ds(on) N-channel MOSFETs. The user-selectable overcurrent protection (OCP) threshold is set by an external TRIP-pin resistor in order to protect the system. The TPS5103 is configured so that a current-sense resistor is not required, improving the operating efficiency.

1 SOFTSTART2 INV3 FB4

6 GND7 REF8 COMP9 PWM/SKIP10 STBY

OUT_u OUT_d 16OUTGND 15 TRIP 14VCC_SENSE 12VREF5 11 VREG5V_IN 20LH 18LL TPS5103 C3 L1 OUTPUT 5 V Figure 1. Typical Design Copyright  2001, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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1.185 V Error Amp PWM Comp. One Shot ON OSC Disable 1.185 V UVLO VREF 1.185 V SOFTSTART LH FB INV PWM/SKIP C T R T Comp GND VCC STBY REF OUT_u LL OUT_d OUTGND TRIP VCC_SENSE VREF5 VREG5V_IN AVAILABLE OPTIONS TA PACKAGE TA SSOP(DB) EVM 40°Ct o8 5°C TPS5103IDB TPS5103EVM –136 –40°C to 85°C TPS5103IDBR

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION COMP 8 I Comparator input for voltage monitor C T 4 I/O External capacitor from CT to GND for adjusting the triangle oscillator and decreasing the current-limiting voltage FB 3 O Feedback output of error amp GND 6 Control GND INV 2 I Inverting input of both error amp and hysteretic comparator LH 20 I/O Bootstrap. Connect a 1 µF, low-ESR capacitor from LH to LL. LL 18 I/O Bootstrap low. High-side gate driving return and output-current protection. Connect to the junction of the high-side and low-side FETs for a floating drive configuration. OUT_d 17 I/O Gate-drive output for low-side power switching FETs OUTGND 16 Ground for FET drivers OUT_u 19 O Gate-drive output for high-side power switching FETs PWM/SKIP 9 I PWM/SKIP mode select L:PWM mode H:SKIP mode REF 7 O 1.185-V reference voltage output R T 5 I/O External resistor connection for adjusting the triangle oscillator. SOFTSTART 1 I External capacitor from SOFTSTART to GND for soft-start control STBY 10 I Standby control TRIP 15 I External resistor connection for output-current control VCC 13 I Supply-voltage input VCC_SENSE 14 I Supply voltage sense for current protection VREF5 12 O 5-V internal regulator output VREG5V_IN 11 I External 5-V input (input voltage range = 4.5 V to 25 V)

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The reference voltage is used for the output voltage setting and the voltage protection(COMP). The tolerance is 1.5% typically. VREF5 An internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage range is from 4.5 V to 25 V, this voltage offers a fixed voltage for the bootstrap voltage so that the design for the bootstrap is much easier. The tolerance is 6%. hysteretic comparator The hysteretic comparator is used to regulate the output voltage of the synchronous-buck converter. The hysteresis is set internally and is typically 9.7 mV. The total delay time from the comparator input to the driver output is typically 400 ns for going both high and low. error amplifier The error amplifier is used to sense the output voltage of the synchronous buck converter. The negative input of the error amplifier is connected to the VREF (1.185 V) with a resistive divider network. The output of the error amplifier is brought out to the FB terminal to be used for loop-gain compensation. low-side driver The low-side driver is designed to drive low-r ds(on) n-channel MOSFETs. The maximum drive voltage is 5 V from VREF5. The current rating of the driver is typically 1.2 A at sink current, and –1.5 A at source current. high-side driver The high-side driver is designed to drive low-rds(on) n-channel MOSFETs. The current rating of the driver is 1.2 A at sink current, and –1.7 A at source current. When configured as a floating driver, the bias voltage to the driver is developed from VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum voltage that can be applied between LH and OUTGND is 30 V. driver deadtime control The deadtime control prevents shoot-through current from flowing through the main power FETs. During switching transitions the deadtime control actively controls the turnon time of the MOSFET drivers. The typical deadtime from the low-side-driver-off to the high-side-driver-on is 90 ns, and 110 ns from high-side-driver-off to low-side-driver-on. COMP COMP is designed for use with a regulation-output monitor. COMP also functions as an internal comparator used for any voltage protection such as the input under voltage protection. If the input voltage is lower than the setpoint, the comparator turns off and prevents external parts from being damaged. The investing terminal of the comparator is internally connected to REF (1.185 V). current protection Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during on-time through VCC_SENSE and LL terminals. An external resistor between VREG5V_IN and TRIP, with the an internal current source connected to the current comparator negative input, adjusts the current limit. The typical internal current source value is 15 µA in PWM mode, and 5 µA in SKIP mode. When the voltage on the positive terminal is lower than the negative terminal, the current comparator turns on the trigger, and then activates the oscillator. This oscillator repeatedly resets the trigger until the overcurrent condition is removed. The capacitor on the C T terminal can be open or added to adjust the reset frequency.

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description (continued) softstart SOFTSTART sets the sequencing of the output for any possibility. The capacitor value for a start-up time can be calculated by the following equation: C = 2 x T (µF) Where C is the external capacitor value, and T is the required start-up time in (ms). standby The controller can be switched into the standby mode by grounding the STBY terminal. When it is in standby mode, the quiescent current is less than 1.0 µA. UVLO The under-voltage lockout (ULVO) threshold is approximately 3.8 V. The typical hysteresis is 55 mV. 5-V switch If the internal 5-V switch senses a 5-V input from REG5V, the internal 5-V linear regulator will be disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and the high-side bootstrap, thus, increasing the efficiency. PWM/SKIP switch The PWM/SKIP switch selects the output operating mode. This controller has three operational modes, PWM, SKIP , and hysteretic. The PWM and SKIP mode control should be used for slower-transient applications. oscillator The oscillator gives a triangle wave by connecting an external resistor to R T and an external capacitor to CT. The voltage amplitude is 0.43 V ~ 1.17 V. This wave is connected to the noninverting input of the PWM comparator. Table 1. Comparison Table Between PWM Mode and Hysteretic Mode MODE PWM HYSTERETIC Frequency Fixed Not fixed Transient response Normal Very fast Feed back compensation Need Needless

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the network ground terminal. 2. See Dissipation Rating Table for free-air temperature range above 25°C. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 85°C POWER RATING DB 801 mW 6.408mW/°C 416 mW recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage 4.5 25 V INV, CT, RT, COMP, PWM/SKIP, SOFTSTART 6 VI Input voltage VREG5V_IN 5.5 VVI Input voltage STBY 12 V TRIP, VCC_SENSE 25 R (T) Timing register 82 kΩ C (T) Oscillator frequency Timing capacitor 100 pF f Frequency 200 kHz TA Operating temperature range –40 85 °C

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range, VCC = 7 V (unless otherwise noted) reference voltage PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V f Reference voltage TA = 25°C, Ivref = 50 µA 1.167 1.185 1.203 VVref Reference voltage Ivref = 50 µA 1.155 1.215 V Regin† Line regulation VCC = 4.5 V to 25 V, I = 50 µA 0.2 12 mV Regl† Load regulation I = 1 µA to 1 mA 0.5 10 mV † Not a JEDEC symbol. oscillator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f Frequency PWM mode 500 kHz R (T) Timing resistor 47 kΩ fdv† Frequency change VCC = 4.5 V to 25 V 0.1% fdt† Frequency change TA = –40°C to 85°C 2% VOH High level output voltage‡ DC includes internal comparator error 1 1.1 1.2 VVOH High-level output voltage‡ f = 200 kHz, includes internal comparator error 1.17 V VOL Low level output voltage‡ DC includes internal comparator error 0.4 0.5 0.6 VVOL Low -level output voltage‡ f = 200 kHz, includes internal comparator error 0.43 V † Not a JEDEC symbol. ‡ The output voltages of oscillator (f = 200 kHz) are ensured by design. error amp PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage TA = 25°C 2 10 mV Av† Open-loop voltage gain 50 dB GB † Unity-gain bandwidth 0.8 MHz IO Output sink current VO = 0.4 V 30 45 µA IS Output source current VO = 1 V 300 µA † Not a JEDEC symbol. hysteresis comparator§ PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vhys Hysteresis window Hysteretic mode 6 9.7 13 mV Vp-VS Offset voltage 2 mV I Bias current 10 pA tPHL Propagation delay from INV to OUT_U TTL input signal 230 ns tPLH Propagation delay time, low-to-high 10-mV overdrive on hysteresis band signal 400 ns § The numbers in the table include the driver delay. All numbers are ensured by design. control PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIHA High level input voltage STBY 2.5 VVIHA High-level input voltage PWM/SKIP 2 V VILA Low level input voltage STBY 0.5 VVILA Low -level input voltage PWM/SKIP 0.5 V

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electrical characteristics over recommended operating free-air temperature range, VCC = 7 V (unless otherwise noted) (continued) 5-V regulator PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage I = 10 mA 4.7 5.3 V Regin† Line regulation VCC = 5.5 V to 25 V, I = 10 mA 20 mV Regl† Load regulation I = 1 mA to 10 mA, V CC = 5.5 V 40 mV IOS Short-circuit output current Vref = 0 V 70 mA † Not a JEDEC symbol. 5-V switch PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT(high) Threshold voltage 4.2 4.9 V VIT(low) Threshold voltage 4.1 4.8 V Vhys Hysteresis 50 150 250 mV UVLO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIT(high) Threshold voltage 3.6 4.2 V VIT(low) Threshold voltage 3.5 4.1 V Vhys Hysteresis 10 150 mV output PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO OUT_u sink current VO = 3 V 0.5 1.2 A IS OUT_u source current VO = 2 V –1 –1.7 A IO OUT_d sink current VO = 3 V 0.5 1.2 A IS OUT_d source current VO = 2 V –1 –1.5 A I TRIP terminal current PWM mode, V(TRIP) = 7 V 10 15 20 µAI TRIP terminal current SKIP mode, V(TRIP) = 7 V 3 5 7 µA High-side driver is GND referenced. Input: INV = 0 – 3V tr Rise time tr/tf = 10 ns, Frequency = 200 kHz ns C L = 2200 pF 28 C L = 3300 pF 39 High-side driver is GND referenced. Input: INV = 0 – 3 V tf Fall time tr/tf = 10 ns, Frequency = 200 kHz ns C L = 2200 pF 30 C L = 3300 pF 38

Figure 2. Test Circuit

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–40 –20 25 – Quiescent Current – 600 650 QUIESCENT CURRENT vs JUNCTION TEMPERATURE 700 85 125 450 350 ICC Aµ TJ – Junction Temperature – °C VCC = 25 V VCC = 7 V VCC = 4.5 V Figure 4 –40 –20 25 85 125 – Quiescent Current – QUIESCENT CURRENT vs JUNCTION TEMPERATURE ICC Aµ TJ – Junction Temperature – °C VCC = 25 V VCC = 7 V VCC = 4.5 V Figure 5 3.5 0.1 0.7 4.5 DRIVE OUTPUT VOLTAGE vs DRIVE SOURCE CURRENT 5.5 IS(OUT_source) – Drive Source Current – A VCC = 7 V, TJ = 25°C – Drive Output Voltage – VVO(OUT_u) Figure 6 1.5 0.5 0.1 0.7 2.5 DRIVE OUTPUT VOLTAGE vs DRIVE SOURCE CURRENT IS(OUT_sink) – Drive Source Current – A VCC = 7 V, TJ = 25°C – Drive Output Voltage – VVO(OUT_u)

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0.5 –40 –20 25 – Error Amplifier Input Offset Voltage – mV 1.5 ERROR AMPLIFIER INPUT OFFSET VOLTAGE vs JUNCTION TEMPERATURE 2.5 85 125 VCC = 4.5 V, VCC = 7 V, VCC = 25 V TJ – Junction Temperature – °C VIO Figure 12 0.5 –40 –20 25 – Error Amplifier Output Voltage – mV 1.5 ERROR AMPLIFIER OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 2.5 85 125 VCC = 4.5 V, VCC = 7 V, VCC = 25 V TJ – Junction Temperature – °C VO Figure 13 5.2 4.8 4.4 5.8 6.2 5.6 5.4 4.6 –40 –20 25 – Error Amplifier Output Voltage – mV ERROR AMPLIFIER OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 85 125 VCC = 4.5 V, VCC = 7 V, VCC = 25 V TJ – Junction Temperature – °C VO Figure 14 9.75 9.5 9.25 – Hysteresis Comparator Hysteresis Voltage – mV 10.25 HYSTERESIS COMPARATOR HYSTERESIS VOLTAGE vs JUNCTION TEMPERATURE 10.5 Vhys –40 –20 25 85 125 VCC = 7 V TJ – Junction Temperature – °C

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3.85 3.80 3.75 3.70 –40 –20 25 – UVOL Threshold Voltage – V 3.90 3.95 UVLO THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 85 125 VTHL,VTLH TJ – Junction Temperature – °C Figure 20 –40 –20 25 – UVLO Hysteresis Voltage – mV UVLO HYSTERESIS VOLTAGE vs JUNCTION TEMPERATURE 85 125 Vhys TJ – Junction Temperature – °C Figure 21 TJ – Junction Temperature – °C 4.60 4.50 4.40 4.35 –45 –25 25 – 5 VSW Threshold Voltage – V 4.70 4.75

5 VSW THRESHOLD VOLTAGE

4.80 95 135 4.65 4.55 4.45 VTLH VTHL VTHL,VTLH Figure 22 140 –45 –25 25 – 5 VSW Hysteresis Voltage – mV160 180

5 VSW HYSTERESIS VOLTAGE

TJ – Junction Temperature – °C

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VCC = 4.5 V, VCC = 7 V, VCC = 25 V VCC = 4.5 V, VCC = 7 V, VCC = 25 V f = 500 kHz f = 200 kHz 300 200 100 –40 –20 25 – Oscillator Frequency – kHz 400 500 OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 600 85 125 fosc TJ – Junction Temperature – °C Figure 28 VOSCH VOSCL 0.8 0.4 10 100 – Oscillator Output Voltahe – V 1.2 1.4 OSCILLATOR OUTPUT VOLTAGE vs FREQUENCY 1.6 1000 0.6 0.2 VOSCH, VOSCL fOSC – Frequency – kHz Figure 29 Phase Gain –20 1 k 10 k 100 k Error Amplifier Gain – dB f – Frequency – Hz ERROR AMPLIFIER GAIN AND PHASE SHIFT

1 M 10 M

R s = 100 Ω , R f = 10 kΩ –10 100 –60 140 180 –20 Phase Shift – Deg

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4.3 4.2 4.1 4.4 4.5 4.6 VI(TRIP) – Input Voltage Skip Mode – V TA = 125°C TA = 25°C TA = –40°C 4.5 7 CURRENT PROTECTION SOURCE CURRENT vs INPUT VOLTAGE SKIP MODE Figure 34 – Current Protection Source Current –ITRIP Aµ C T = 10 pF C T = 15 pF C T = 22 pF C T = 33 pF C T = 470 pF C T = 680 pF 400 200 100 10 100 500 600 OSCILLATOR FREQUENCY vs RESISTOR 700 1000 300 – Oscillator Frequency – kHzfosc R (T) – Resistor – kΩ Figure 35

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APPLICATION INFORMATION

Resistor (Rg) is moved from the gate of the top FET and placed in series with LL. This allows for a smaller Schottky diode (DX) to be used. OUT_u Q1 LL DX R g Figure 38. High-Current Schottky Diode Removed component count, and board cost. Figure 39. EVM Schematic

/C0466V (z)–V ref/C0467 /C0466V ref–V O /C0467 R1 /C0041 Vref TPS5103 MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 output voltage setpoint calculation The output voltage is set by the reference voltage and the voltage divider. In the TPS5102, the reference voltage is 1.185 V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15. The equation for the setpoint is shown below. R2 /C0043 R1 /C0032 V ref V O /C0042 V ref Where R1 (> 10 kΩ ) is the top resistor R2 is the bottom resistor (kΩ ), VO is the required output voltage, and Vref is the reference voltage (1.185 V in TPS5103). Example: R1 = 1 kΩ ; Vref = 1.185 V; VO = 1.8 V, then R2 = 1.9 kΩ . Some of the most popular output voltage setpoints are calculated in Table 2. Table 2. Output Voltage Setpoints If higher precision resistor is used, the output voltage setpoint can be more accurate. components, this lower voltage can be easily achieved. Figure 40 shows the method for accomplishing this. Figure 40. Application With Extra Components for Lower Output Voltage on INV is still equal to the IC internal voltage (1.185 V), even if the output voltage is regulated at a lower setpoint. O is the required output voltage setpoint.

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With hysteretic control, the switching frequency is a function of the following: /C0068 input voltage /C0068 output voltage /C0068 hysteresis window /C0068 delay of the hysteresis comparator and the driver /C0068 output inductance /C0068 resistance in the output inductor /C0068 output capacitance /C0068 ESR and ESL in the output capacitor /C0068 output current /C0068 turnon resistance of the high-side and the low-side MOSFET This is a very complex equation if everything is included. To make it more useful to the designers, a simplified equation only considers the most influential factors. The tolerance of this equation is about 30%. ƒs /C0043 V O /C0032 (VI/C0042 V O )/C0032 (ESR /C0042 (10/C0032 10/C0042 7 /C0041 Td)/C0324 C O ) V I/C0032 (VI/C0032 ESR /C0032 (10/C0032 10/C0042 7 /C0041 Td)/C0041 0.0097/C0032 L(O)/C0042 ESL /C0032 V I) Where fs is the switching frequency (Hz), VO is the output voltage, VI is the input voltage, CO is the output capacitance, ESR is the equivalent series resistance in the output capacitor (Ω ), ESL is the equivalent series inductance in the output capacitor (H), L(O) is the output inductance (H), and Td is the output feedback RC filter time constant (s). For example: VI = 5 V, VO = 1.8 V, CO = 680 µF; ESR = 40 mΩ ; ESL = 3 nH; L(O) = 6 µH; Td = 0.5 µs. Then, the frequency (fs) = 122 kHz. output inductor ripple current The output inductor current ripple can affect not only the efficiency and the inductor saturation, but also the output voltage capacitor selection. The equation is exhibited as below: I(ripple)/C0043 V I/C0042 V O /C0042 IO /C0466rds(on)/C0041 RL /C0467 LO /C0032 D /C0032 Ts Where I(ripple) is the peak-to-peak ripple current (A) through inductor; VI is the input voltage, VO is the output voltage, IO is the output current, rds(on) is the on-time resistance of MOSFET (Ω ), D is the duty cycle, and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by changing the output inductor value. Example: VI = 5 V, VO = 1.8 V, IO = 5 A, rds(on) = 10 mΩ , RL = 5 mΩ , D = 0.36, Ts = 10 µs, L(O) = 6 µH Then, the I(ripple) = 2 A. output capacitor RMS current Assuming the inductor ripple current totally goes through the output capacitor to the ground, the RMS current in the output capacitor can be calculated as: IO(rms)/C0043 /C0068 I 12/C0504

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 output capacitor RMS current Where IO(rms) is the maximum RMS current in the output capacitor (A), and ∆I is the peak-to-peak inductor ripple current (A). Example: ∆I = 2 A, so IO(rms) = 0.58 A input capacitor RMS current Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in the input capacitor can be calculated as: II(rms)/C0043 I 2 o /C0032 D /C0032 (1/C0042 D) /C0041 1 12 /C0032 D /C0032 Iripple2/C0504 Where II(rms) is the input RMS current in the input capacitor (A), IO is the output current (A), and D is the duty cycle. From the equation, it can be seen that the highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for the input capacitor ripple current. Example: IO = 5 A; D = 0.36 Then, II(rms)= 3.36 A softstart The softstart timing can be adjusted by selecting the soft-start capacitor value. The equation is shown below. C (soft)/C0043 2 /C0032 T(soft) Where C(soft) is the softstart capacitance (µF), T(soft) is the start-up time on the softstart terminal (s). Example: T(soft) = 5 ms, so, C(soft) = 0.01 µF. current protection The current protection in the TPS5103 is set using an internal current source and an external resistor to set up the current limit. The sensed, high-side MOSFET drain-to-source voltage drop is compared to the set point, if the voltage drop exceeds the limit, the internal oscillator is activated, and continuously resets the current limit until the over-current condition is removed. The equation below should be used for calculating the external resistor value for current protection: Rcl/C0043 rds(on)/C0032 /C0466I(trip)/C0041 Iind(p-p)/C0324 2/C0467 0.000015PWM or HYS mode Rcl/C0043 rds(on)/C0032 I(trip)/C0041 Iind(p-p)/C0324 2 0.000005SKIP mode Where, Rcl is the external current limit resistor (R10, R11), rds(on) is the high side MOSFET on-time resistance, I(trip) is the required current limit, and Iind(p-p) is the peak-to-peak output inductor current. Example: PWM mode or HYS mode rds(on) = 10 mΩ , I(trip) = 5 A, Iind(p-p) = 2 A, so Rcl = 4 kΩ Example: SKIP mode rds(on) = 10 mΩ , I(trip) = 2 A, Iind(p-p) = 1 A, so Rcl = 5 kΩ

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Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized control, two parts are discussed in this section: the power stage small signal modeling and the compensation circuit design. For the buck converter, the small-signal modeling circuit is shown in Figure 41. ac ia ic p Vap D d Ic d VI R L L ZL C R R C ZRC VO Figure 41. Small-Signal Modeling Circuit output inductor, RL is the equivalent serial resistance (ESR) in the output inductor, and R is the load resistance. to improve the feedback control. The whole system is shown in Figure 42. Figure 42. Loop-Gain Compensation The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit. The circuitry is shown in Figure 43.

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loop-gain compensation (continued) There is one pole, one zero, and one integrator. Zero/C0043 1 2/C0112 C3R4 Pole/C0043 1 2/C0112 C2R4 Integrator/C0043 1 2/C0112 ƒC3R2 The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived by the control-to-output transfer function times the compensation. The equation is shown below. Loop /C0042 gain/C0043 Vod X Comp By using a bode plot, the amplitude and the phase of this equation can be drawn with software such as MathCad. In turn, the stability can be easily designed by adjusting the compensation perimeters. The sample bode plot shown in Figure 45 explains the phase margin, gain margin, and the crossover frequency. The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is added to the phase, so that the gain and phase share the same zero. Where the gain curve touches the zero is the crossover frequency. The higher this frequency is, the faster the transient response is, since the transient recovery time is 1/(crossover frequency). The phase to the zero is the phase margin at the crossover frequency. The phase margin should be at least 60 degrees to cover all the condition changes, such as temperature. The gain margin is the gap between the gain curve and the zero when the phase curve touches the zero. This margin should be at least 20 dB to assure the stability over all conditions. Phase Margin Phase Gain Crossover Gain Margin –44 –100 166 f – Frequency – Hz 180 152 138 124 110 –16 –30 –58 –72 –86 10 100 1 k 10 k 100 k 1 M

20 Log (Loop Gain)

Figure 45. Sample Bode Plot (not the EVM)

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layout guidelines (continued) /C0068 When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should be as short and as wide as possible. /C0068 When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5103. /C0068 When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND. /C0068 The bulk-storage capacitors across VI should be placed close to the power FETS. High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the high-side FET and to the source of the low-side FET. /C0068 High-frequency bypass capacitors should be placed across the bulk-storage capacitors on VO . /C0068 LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH and LL should be routed very close to each other to minimize differential-mode noise coupling to these traces. Ceramic-decoupling capacitors should be placed close to where VCC connects to VI, to reduce high-frequency noise coupling on VCC . /C0068 The output-voltage sensing trace should be isolated by either ground trace or VCC trace. test results The tests are conducted at TA = 25°C, the point voltage is 5 V.

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001

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0 0.5 1 1.5 2 2.5 3 3.5 4 IO – Output Current – A Efficiency – % EFFICIENCY vs OUTPUT CURRENT 1.8-V Output Diode Type Efficiency Figure 53 OUTPUT VOLTAGE OUTPUT/VOLTAGE Figure 54 TRANSIENT RESPONSE (OVERSHOOT) Figure 55 TRANSIENT RESPONSE (UNDERSHOOT)

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Table 3. Bill of Materials (see Note 3) † Components for optional mode test only.

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 56. Top Layer Figure 57. Bottom Layer (Top View)

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 4. Test Specifications Table 5. EVM Operating Specifications be simpler. Table 6 gives some recommendations. Table 6. EVM Application Recommendations Table 7. Vendor and Source Information

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001 35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 High-current applications are described in Table 8. The values are recommendations based on actual test circuits. Many variations are possible based on the requirements of the user. Performance of the circuit is dependent upon the layout rather than on the specific components, if the device parameters are not exceeded. The power stage, having the highest current levels and greatest dv/dt rates, should be given the most attention, as both the supply and load can be severely affected by the power levels and edge rates. Table 8. High-Current Applications

30 V, 10 A, 13 mΩ

MULTIPLE MODE SYNCHRONOUS DC/DC CONTROLLER SLVS240A – SEPTEMBER 1999 – REVISED MAY 2001

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040065 /C 10/95

28 PINS SHOWN

8,20 7,40 0,15 NOM 0,63 1,03 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–8° 0,10 3,30 2,70 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS5103IDB ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5103IDBG4 ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5103IDBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS5103IDBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5103IDBR SSOP DB 20 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2

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