TPS51020DBT.B

TPS51020 TI | Alldatasheet

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/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 /C0068/C0085/C0065/C0076/C0044 /C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0077/C0079/C0068/C0069/C0044 /C0068/C0068/C0082 /C0083/C0069/C0076/C0069/C0067/C0084/C0065/C0066/C0076/C0069/C0044 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083/C0044 /C0083/C0084/C0069/C0080/C0262/C0068/C0079/C0087/C0078 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 /C0070/C0079/C0082 /C0078/C0079/C0084/C0069/C0066/C0079/C0079/C0075 /C0083/C0089/C0083/C0084/C0069/C0077 /C0080/C0079/C0087/C0069/C0082 1www.ti.com

FEATURES

/C0068Wide Input Voltage Range: 4.5-V to 28-V /C0068Selectable Dual and DDR Modes /C0068Selectable Fixed Frequency Voltage Mode /C0068Advanced Power Good Logic Monitors both Channels /C0068Selectable Autoskip Mode /C0068Integrated Boot Strap Diodes /C0068180° Phase Shift Between Channels /C0068Integrated 5-V, 60-mA Regulator /C0068Input Feedforward Control /C00681% Internal 0.85-V Reference /C0068R DS(on) Overcurrent Detection (4200 ppm/°C) /C0068Integrated OVP, UVP and Power Good Timers /C006830-pin TSSOP Package

APPLICATIONS

/C0068Notebook Computers System Bus and I/O /C0068DDR I or DDR II Termination

DESCRIPTION

The TPS51020 is a multi-function dual- synchronous step-down controller for notebook system power. The part is specifically designed for high performance, high efficiency applications where the loss associated with a current sense resistor is unacceptable. The TPS51020 utilizes feed forward voltage mode control to attain high efficiency without sacrificing line response. Efficiency at light load conditions can be maintained high as well by incorporating autoskip operation. A selectable, Suspend to RAM (STR) supported, DDR option provides a one chip solution for all switching applications from 5-V/3.3-V supply to a complete DDR termination solution.

ORDERING INFORMATION

TA PLASTIC TSSOP (DBT) −40°C to 85°C TPS51020DBT −40°C to 85°C TPS51020DBTR (T&R) SIMPLIFIED APPLICATION DIAGRAM UDG−03144 VO1 TPS51020 COMP2 SSTRT2 PGOOD VO2 ENBL2 ENBL1 REF_X GND DDR VO1_VDDQ SSTRT1 COMP1 REG5_IN VREG5 VBST2 OUT2_U LL2 OUT2_D OUTGND2 VIN TRIP1 OUTGND1 OUT1_D LL1 OUT1_U VBST1

15 INV2

EXT_5V /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 2 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted. All voltage values are with respect to the network ground terminal unless otherwise noted. (1) TPS51020 UNIT VBST1, VBST2 −0.3 to 35 Input voltage range VBST1, VBST2 (with respect to LL ) −0.3 to 7 Input voltage range VIN, TRIP1, TRIP2, ENBL1, ENBL2, DDR −0.3 to 30 SKIP, INV1, INV2 −0.3 to 7 OUT1_U, OUT2_U −1 to 35 OUT1_U, OUT2_U (with respect to LL ) −0.3 to 7 V LL1, LL2 −1 to 30 V Ouput voltage range REF_X −0.3 to 15Ouput voltage range PGOOD, VO1_VDDQ, VO2, OUT1_D, OUT2_D, COMP1, COMP2, VREG5, SSTRT1, SSTRT2 −0.3 to 7 OUTGND1, OUTGND2 −0.3 to 0.3 Output current range VREG5 70 mAOutput current range REF_X 7 mA Operating free-air temperature range, TA −40 to 85 Storage temperature range, Tstg −55 to 150 °CJunction temperature range, TJ −40 to 125 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Supply voltage, VIN 4.5 28 Supply voltage, VBST1, VBST2 4.5 33 ENBL1, ENBL2, DDR , TRIP1, TRIP2 −0.1 28 OUT1_U, OUT2_U −0.8 33 OUT1_U, OUT2_U (with respect to LL ) −0.1 5.5 LL1, LL2 −0.8 28 V I/O Voltage REF_X −0.1 12 V I/O Voltage SSTRT1, SSTRT2, COMP1, COMP2 −0.1 5.5 SKIP, INV1, INV2 −0.1 5.5 PGOOD VO1_VDDQ, VO2 −0.1 5.5 OUT1_D, OUT2_D, VREG5 −0.1 5.5 Source current VREG5 60 mASource current REF_X 5 mA Operating free-air temperature, TA −40 85 °C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ”recommended operating conditions” is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability DISSIPATION RATING TABLE PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 85°C POWER RATING 30-pin DBT 874 mW 7.0 mW/°C 454 mW

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 3www.ti.com INV1 COMP1 SSTRT1 SKIP VO1_VDDQ DDR GND REF_X ENBL1 ENBL2 VO2 PGOOD SSTRT2 COMP2 INV2 VBST1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN TRIP2 VREG5 REG5_IN OUTGND2 OUT2_D LL2 OUT2_U VBST2 TSSOP (0.5 mm) DBT PACKAGE (TOP VIEW)

ELECTRICAL CHARACTERISTICS

INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D) =1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT CURRENTS IVIN VIN supply current REG5V_IN = OPEN, TRIPx = VIN, OSC = OFF 1.4 2.2 mA IVIN(STBY) VIN standby current ENBLx = 0 V, DDR = VIN, REG5V_IN = OPEN, OSC = OFF 350 550 IVIN(SHDN) VIN shutdown current ENBLx = DDR = 0 V, REG5V_IN = OPEN 0.05 1.00 µA IVIN(REG5) VIN supply current, REG5_IN as 5-V input current REG5V_IN = 5 V, OSC = OFF 200 500 IREG5 REG5_IN input supply current REG5V_IN = 5 V, OSC = OFF 1.0 1.7 mA IVBSTx VBST supply current ENBLx = DDR = VIN 0.05 1.00 AIVBSTx VBST shutdown current ENBLx = DDR = 0 V 0.05 1.00 µA VREG5 INTERNAL REGULATOR VVREG5 VREG5 voltage IOUT = 0 A 4.8 5.0 5.2 V VLD5 Load regulation 0 mA ≤ IOUT ≤ 50 mA, V IN = 12 V 0.6% 2.5% VLN5 Line regulation IOUT = 20 mA, 7 V ≤VIN ≤ 28 V 0.4% 2.0% VTHL UVLO threshold voltage High to low 3.45 3.65 3.85 V VHYS(UV) UVLO hysteresis 100 200 300 mV VTH(SW) Switchover voltage REG_IN voltage 4.2 4.5 4.8 V VHYS(SW) Switchover hysteresis 50 250 mV

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 4 www.ti.com ELECTRICAL CHARACTERISTICS (continued) INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D) =1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER UNITMAXTYPMINTEST CONDITIONS REF_X REFERENCE VOLTAGE VREF10 10-V reference voltage VIN = 14 V, I OUT = 0 A 8.5 10.0 11.0 V VLD10 Load regulation 0 mA ≤ IOUT ≤ 2 mA, V IN = 18 V -12% -20% VLN10 Line regulation IOUT = 100 µA, 14 V ≤VIN ≤28 V 5% VREFVTT VTT reference voltage DDR = 0 V wrt VO1_VDDQ input divided by 2 VVO1 = 2.5 V 1.5% VREFVTT VTT reference load regulation 0 mA ≤ IO ≤ 3 mA 0.75% POWERGOOD COMPARATORS VTHDUAL(PG) PGOOD threshold (dual mode) Undervoltage PGOOD 765 786 808 mVVTHDUAL(PG) PGOOD threshold (dual mode) Overvoltage PGOOD 892 920 945 mV VTHDDR(PG) PGOOD threshold (DDR) Undervoltage PGOOD, VO1_VDDQ = 2.5 V 1.12 1.14 1.16 VVTHDDR(PG ) PGOOD threshold (DDR) Overvoltage PGOOD, VO1_VDDQ = 2.5 V 1.28 1.31 1.33 V TPG(del) PGOOD delay time INVx > undervoltage PGOOD, Delay time from SSTRTx > 1.5 V to PGOOD going high 2048 clks DIGITAL CONTROL INPUTS VIH High-level input voltage, logic DDR , ENBL1, ENBL2, SKIP 2.2 VVIL Low-level input voltage, logic DDR , ENBL1, ENBL2, SKIP 0.3 V IINLEAK Logic input leakage current DDR , ENBL1, ENBL2, SKIP= 5 V |1.0| µA VO1_VDDQ and VO2 R VOUT VOx sink impedance VVOUTx = 0.5 V, fault engaged 6 10 Ω VVOUTOK VOx low restart voltage Fault condition removed, restart 0.25 0.32 0.40 V VVO2LEAK VOx input leakage current DDR = VIN, VOx = 5 V |1.0| µA R VOUT VO1_VDDQ input impedance DDR = 0 1.5 M Ω UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVPDUAL OVP trip output threshold (dual) Sensed at INVx 945 970 1010 mV VOVPDDR OVP trip output threshold (DDR) VO1_VDDQ = 2.5 V 1.31 1.36 1.41 V TOVP(del) OVP propagation delay time(1) 20 µs VUVPDUAL UVP trip output threshold (dual) Sensed at INVx 510 553 595 mVVUVPDDR UVP trip output threshold (DDR) VO1_VDDQ = 2.5 V 750 813 875 mV TUVP(del) UVP propagation delay time 4096 clks OVERCURRENT and INPUT VOLTAGE UVLO PROTECTION ITRIPSNK TRIPx sink current VTRIPx = VIN − 100 mV, T A = 25°C 11 13 15 AITRIPSRC TRIPx source current VTRIPx = 100 mV, T A = 25°C 10 13 16 µA TC ITRIP TRIP current temperature coeficient(1) TA = 25°C 4200 ppm/ VOCPHI High-level OCP comparator offset voltage(1) 0 |3.0| mVVOCPLO Low-level OCP comparator offset voltage(1) 0 |5.0| mV VVINUVLO VIN UVLO trip threshold REF5V_IN = 4.8 V 3.7 3.9 4.1 V VVINHYS VIN UVLO trip hysteresis 100 200 300 mV

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 5www.ti.com ELECTRICAL CHARACTERISTICS (continued) INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D) =1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER UNITMAXTYPMINTEST CONDITIONS 0.85-V REFERENCE CONTROL LOOP VREFCH1 Error amplifier reference, channel 1 initial accuracy Measure COMP1, COMP1= INV1, TA = 25°C 0.84 0.85 0.86 V VREFTC1 Error amplifier reference, channel 1 change with accuracy 0.5% VREFLN1 Error amplifier reference, channel 1 change with line 0.1% VCHMM Channel 2 to channel 1 voltage mismatch 0 |5.0| mV CONTROL LOOP: SKIP HYSTERSTIC COMPARATOR AND ZERO CURRENT COMPARATOR VLLHYS Skip hysteresis comparator hysteresis(1) 1 2 3 VLLOFF Lload hysteresis comparator offset(1) 0 1 mV VZOFF Zero current comparator offset(1) 10 18 mV THLTOLL PWM skip delay time 8 clksTHLTOHL Skip to PWM delay time 1 clks CONTROL LOOP ERROR AMPLIFIER IEASRC COMPx source current 0.2 0.9 mAIEASNK COMPx sink current 0.2 0.7 mA FUGB Unity gain bandwidth(1) 2.5 MHz AOL Open loop gain(1) 80 dB CMR COMP COMPx voltage range(1)(6) 0.4 VREG5−3 V IINVLEAK INVx input current |0.5| µA CONTROL LOOP: DUTY CYCLE, VOLTAGE RAMP, CHANNEL PHASE AND PWM DELAY PATH fOSC = 270 kHz(3) 86% 88% DC MAX Maximum duty cycle fOSC = 360 kHz 84% 85%DC MAX Maximum duty cycle fOSC = 450 kHz(2) 80% 82% PH CH Channel to channel phase difference(5) PWM phase reversal only 180 ° TMIN OUTX_U minimum pulse width(1) 100 ns TIMERS: INTERNAL OSCILLATOR (4) fOSC(hi) Fast oscillator frequency initial accuracy(2) R SSTRTx = OPEN 450 fOSC(lo) Slow oscillator frequency initial accuracyR SSTRTx = 1MΩ or VSSTRT = 3 V 270 kHz fOSC(tc) Oscillator frequency over line and temperatureTrimmed for 360 kHz 306 360 414 kHz (1)Ensured by design. Not production tested. (2)Maximum 450-kHz frequency can be achieved when both channels are enabled. (3)270 kHz is the default frequency during start-up for both channels. (4)See Table 1. (5)See PWM detailed description

(1)Ensured by design. Not production tested. (2)Maximum 450-kHz frequency can be achieved only when both channels are enabled. (3)270 kHz is the default frequency during start-up for both channels. Table 1. Frequency Selection

1 MΩ || CSSTRT to GND C SSTRT only 360

1 MΩ || CSSTRT to GND 1 MΩ || CSSTRT to GND 270

capacitor, the softstart time to 0.85V is altered by about only 20%.

ENBLx is low, and the power good output is high, then the power good signal for that channel is ignored. supply presented to REG5_IN. mode is disabled for Channel 2. resistor between TRIP1 and GND for low-side N-channel MOSFET overcurrent latch shutdown. when this pin is tied to ground via a resistor. Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.VBST2 16 I Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx. nected to GND since VTT must remain in a high-impedance state during S3 mode. VREG5 22 O Internal, 60-mA, 5-V regulator output. DDR, ENBL1 or ENBL2 high ( > 2.2V) turns on the 5 V regulator. pin and the high-side N-channel MOSFET drain where positive node of TRIPx resistors are located. Table 2. Reference Regulator Control

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 9www.ti.com FUNCTIONAL BLOCK DIAGRAM Shows Channel 1 (VO1_VDDQ) and the supporting circuitry.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 10 www.ti.com

APPLICATION INFORMATION

The PWM control block utilizes a fixed-frequency, feed-forward, voltage-mode control scheme with a wide-bandwidth, low-impedance output error amplifier as the voltage servo control block. This scheme allows the highest efficiency down conversion while maintaining excellent line regulation and fast transient response. Loop compensation is programmed by connecting a filter network between the COMPx pin and the INVx pin. The wide bandwidth error amplifier handles conventional Type II compensation or Type III compensation when using ceramic capacitors for the converter output. For channel one, the reference signal for the control loop is always a precision 0.85-V internal reference, while the channel two loop reference is either the 0.85-V reference or, in the case of DDR mode, one half the VO1_VDDQ voltage, (VO1_VDDQ)/2. The output signal of the error amplifier appears at the COMPx pin and is compared to a buffered version of the 0.6-V oscillator ramp. When TRIP2 pin is tied to VIN through a resistor, the voltage ramp is further modulated by the input voltage, VIN, to maintain a constant modulator gain. If the TRIP2 pin is connected to ground through a resistor, then the voltage ramp remains fixed regardless of VIN value. The oscillator frequency is internally fixed and can be selected at 270 kHz, 360 kHz or 470 kHz by insertion of a clamping resistor on the SSTRTx pin per Table 1. For example, 470 kHz can be attained when both SSTRTx voltages exceed 3.5 V, as described in WAVEFORM1. The controller begins with 270 kHz in the first stage of the softstart, and then increases to 470 kHz at the steady state. When 270 kHz is selected, both of SSTRTx voltages are kept below 3.5 V so that the frequency is the same 270 kHz for the entire operation. Two channels are operated in 180 degrees out-of-phase interleave switching mode. This interleaving helps reduce the input current ripple requirement for the input capacitor. However, because the PWM loop determines both the turn-off AND turn-on of the high-side MOSFET, this 180 degree operation may not be apparent by looking at the LLx nodes only. Rather, the turn-off cycle of one channel always corresponds to the turn-on cycle of the other channel and vise-versa. As a result, input ripple is reduced and dynamic response is improved over a broad input voltage range. MAXIMUM DUTY CYCLE Because most notebook applications typically run from three to four cell Li−Ion or run from a 20-V adapter, 100% duty cycle operation is not required. Rather, the TPS51020 is optimized for low duty ratio step-down conversion. As a result of limiting the duty cycle, the flying BST capacitor is refreshed reliably and the low-side over current detection circuitry is capable of detecting an overcurrent condition even if the output is stuck between the regulation point and UVP. The maximum duty cycle for each operating frequency is 88% for 270 kHz, 85% for 360 kHz and 82% for 470 kHz. It should be noted that if the system is operating close to maximum (or minimum) duty cycle, it may be difficult for the converter to respond quickly during line/load transients or state changes (such as frequency switching during soft start or PWM to SKIP mode transitions). This slow response is due to the dynamic range of the COMP pin and is usually not a result of poor phase compensation. In the case of minimum duty cycle operation, the slow response is due to the minimum pulse width of the converter (100 ns TYP). In this case (counter intuitively), it may be advisable to slow down the switching frequency of the converter in order to improve response time.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 11www.ti.com If the SKIP pin is set HIGH, the SMPS operates in the fixed PWM mode. While a LOW signal is applied, the controller operates in autoskip mode. In the autoskip mode, the operation changes from constant frequency PWM mode to an energy-saving skip mode automatically by detecting the edge of discontinuous current mode. During the skip mode, the hysteretic comparator monitors output voltage to trigger high side on at the next coming oscillator pulse after the lower level is detected. Several sequential pulses may be seen, especially in the intermediate load level, before output capacitor is charged up to the higher level and waits for next cycle. In the skip mode, frequency varies with load current and input voltage. Skip mode for SMPS_2 is disabled regardless of the SKIP pin status if DDR mode is selected (see Dual Mode and DDR Mode section). This is because current sink capability is required for VTT, so that rectifying MOSFET needs to be kept on when the inductor current flows inversely. SMPS_1 is still capable of skip mode operation while DDR Mode. CASCADE CONFIGURATION If the TRIP2 pin is tied through a resistor to the input voltage, the TPS51020 assumes that the conversion voltage for channel two is the VIN voltage, usually VBATT. Conversely, if TRIP2 is tied through a resistor to ground, the controller assumes that the conversion voltage for channel two is the output voltage of channel one or some other stable bus voltage. DUAL MODE AND DDR MODE TPS51020 provides one-chip solution for system power supply, such as for 5 V, 3.3 V or 1.8 V, and a dual switcher DDR power supply. By simply selecting DDR signal and some external configuration change following the instructions below, TPS51020 gives a complete function set required for the DDR termination supply such as VDDQ/2 tracking V TT source/sink capability and VTT reference output. If DDR is set high ( > 2.2 V), the TPS51020 runs in dual mode, that is, each converter produces an independent output voltage with respect to the internal 0.85-V reference. Bypass REF_X to ground by 0.01-µF. The VO1_VDDQ or VO2 terminal should be connected to their corresponding switcher output. The 10-V reference output can be used as FET switch biasing for power control during sleep states (see Figure 5). During this dual mode, selection of autoskip mode or PWM mode made by SKIP applies to both SMPS_1 and SMPS_2. If DDR is set low ( < 0.3V), the TPS51020 operates as a dual switcher DDR supply; VDDQ from SMPS_1 and VTT from SMPS_2 (DDR Mode). In this mode, the reference voltage for SMPS_2 is switched to (VO1_VDDQ)/2 to track exactly half the voltage of SMPS_1, divided by internal resistors. VO1_VDDQ should be connected to SMPS_1 output terminal to accomplish this. REF_X outputs the (VO1_VDDQ)/2 voltage after a buffer (5-mA max). SKIP controls only SMPS_1 and SMPS_2 is forced to operate in PWM mode so that current can be sink from the output. Power source of SMPS_2 can either be the battery voltage (independent configuration), or the VDDQ (cascade configuration) by user’s preference. When using the independent configuration, TRIP2 needs to be connected to the VIN node via trip resistor. In case of cascade configuration, tie TRIP2 to GND via trip resistor (see Figure 7). CAUTION:Do NOT toggle DDR HIGH while ENBL1 or ENBL2 is high (see Table 2). REF_X output switches to high voltage (10 V) and be applied to VTTREF directly

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 12 www.ti.com 5-V LINEAR REGULATOR (VREG5) The VREG5 voltage is the bias for all the low voltage circuitry in the TPS51020 as well as the DC boost voltage for the MOSFET gate drivers. Total available current is 60 mA. Bypass this pin to GND by 4.7-µF. The under voltage lockout (UVLO) circuit monitors the output of this regulator to protect internal circuitry from low input voltages. If 5 V is applied to REG5_IN from either the SMPS output or an alternate 5 V, then the linear regulator is turned off and the VREG5 pin is switched over to REG_IN. This operation enhances the efficiency of the overall power supply system because the bulk of the quiescent current now runs from the 5-V output instead of VIN (VBAT). In this configuration, ensure that VREG5_IN is less than or equal to V VIN. EXTERNAL 5V INPUT (REG5_IN) When a 5-V bus is available, VIN does not need to be connected to the battery. In this configuration, VIN should be connected to REG5_IN. LOW-SIDE N-CHANNEL FET DRIVER The low-side driver is designed to drive high current low RDS(on) N-channel MOSFET(s). The maximum drive voltage is 5.5 V. The drive capability is represented by its internal resistance, which are 3 Ω for VREG5 to OUTx_D and 2.5 Ω for OUTx_D to OUTGNDx. A dead time is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on, in order to prevent shoot through. The low-side driver is typically turned off during all fault modes except for OVP. When an OVP condition exists, the low-side driver of the offending channel turns on and attempts to blow the protection fuse of the input supply. HIGH-SIDE N-CHANNEL FET DRIVER The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). When configured as a floating driver, a 5-V bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by the flying capacitor between VBSTx and LLx pins, 0.1-µF ceramic for typical applications. The boost diodes are integrated and are sufficient for enhancing the high-side MOSFET. However, external boost diodes can also be added from VREG5 to each VBSTx in case higher gate-to-source votlage is required. The drive capability is represented by its internal resistance, which are as follows: 3 Ω for VBST to OUTx_U and 2.5 Ω for OUTx_U to LLx. The maximum voltage that can be applied between OUTx_U pin and OUTGNDx pin is 35 V.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 13www.ti.com Each SMPS is switched into standby mode separately by grounding the corresponding ENBLx pin. The 5-V supply is enabled if either the DDR, ENBL1 or ENBL2 pin(s) goes high ( >2.2 V). Softstart of each SMPS is achieved by slowly ramping the error amplifier reference voltage by following a buffered version of the SSTRTx pin voltage. Designers can achieve their own start-up sequencing by simply provide external timing signals since the startup times do not depend on the load current. The softstart time is programmable by external capacitor connected from SSTRTx pin to the ground. Each SSTRTx pin sources constant current, typically 2.3 µA. The output voltage of the SMPS ramps up from 0 V to its target regulation voltage as the SSTRTx pin voltage increases from 0 V to 1.2 V. This gives the softstart time formula to be, C SSTRT (Farads)/C0043 TSSTRT (sec)/C00322.3/C003210/C00426 1.2 The soft-start capacitor is discharged upon UVLO, OVP or UVP is detected as well as ENBLx is set low. OUTPUT DISCHARGE (SOFT-STOP) When an SMPS is turned off by ENBLx asserted low or the part enters a fault mode, both top and bottom drivers are turned off. This may leave the output in a high impedance state that allows the voltage to persist for some time. Output voltage should be discharged prior to the next power up. To achieve this, connect the output to the VO1_VDDQ or VO2 pins. These pins turn on a 6-Ω resistor to ground during an off or fault condition. Both the VO1_VDDQ and VO2 pin must be discharged to 0.3 V before the TPS51020 restarts. The TPS51020 has the flexibility of adding a resistor in series with the VOx pin and the output voltage in order to reduce the discharge current and reduce the total power dissipation within the device. It should be noted that when this resistor is added the discharged voltage threshold changes according to the following equation: V DISCHARGE /C0043 /C0466R EXTERNAL /C0041R DS(on)/C0467 R DS(on) /C00320.3 where /C0068R EXTERNAL is the series resistor between VOx and the output /C0068R DS(on) = 6 Ω

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 14 www.ti.com 10-V N-CHANNEL FET BIAS or (VOUT1)/2 VTT VOLTAGE REFERENCE (REF_X) TPS51020’s REF_X provides two functions depending on the operational mode. One is a linear regulator that supply 10-V for FET switch biasing in the dual mode, the other is VTT reference voltage in the DDR mode. If DDR is high ( > 2.2 V) then the REF_X output is a convenient 10-V, 2-mA (maximum) output, useful for biasing N-channel FET switches typically used to manage S0, S3 and S5 sleep states where the main supply is switched to many outputs. When VIN is < 12 V, REF_X approximately tracks VIN−2 V. If DDR is low, then the REF_X output becomes the VDDQ/2 (VO1_VDDQ/2) reference. This output is capable of 5-mA source current and is left on even if channel two (VTT switcher) is turned off. REF_X is turned off if ENBL1 and ENBL2 are both low (see Table 2). POWERGOOD The TPS51020 has advanced powergood logic that allows single powergood circuit to monitor both SMPS output voltages (see Figure 3 ). VOUT1 VOUT2 PGOOD Delay Counter PGOOD ENBL1 ENBL2 Resets Delay Counter t0 t1 t2 2048 c 2048 c Figure 3. PowerGood Timing Diagram started and have been in regulation (±7.5%) for 2048 clock pulses.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 15www.ti.com If one channel is enabled in the period between T0 and T1, (the other channel’s ramp time plus delay time,) the PGOOD delay counter restarts counting softstart finish after the last channel has finished softstart. Enabling after T1 is ignored by PGOOD until the channel finishes its softstart. If either of the SMPS output goes out by ± 7.5% or UVLO is detected while ENBLx is high, PGOOD pulls low. If a channel is disabled while the other is still active PGOOD maintains it’s logic state and only monitor the active channel. PROTECTION FUNCTIONS The TPS51020 is equipped with input undervoltage lock out (UVLO), output undervoltage protection (UVP) and overvoltage (OVP) protection. Overcurrent is detected using R DS(on) of the external power MOSFETs and protected by triggering UVP, or latch off in some cases. The states of output drive signal depends on which protection was involved. Please refer to each protection description below for the detail. When the input voltage UVLO is tripped, the TPS51020 resets and waits for the voltage to rise up over the threshold voltage and restart the device. Alternatively, if output UVP or OVP is triggered, the device latches off after a delay time defined by the internal fault counter counting the PWM oscillator pulses. The VREF5 and REF_X is kept on in this latch off condition. The fault latch can be reset by toggling both of ENBLx pins in DDR mode. The fault latch can be reset by either toggling VIN or bringing DDR , ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode. If a false trip of the UVLO appears due to input voltage sag during turn-on of the high-side MOSFET such as a large load transient, first consider adding several micro-farads of input capacitance close to the MOSFET’s drain. Also consider adding a small V IN filter, ex. a 2.2-Ω resistor and a 2.2-µF, for decoupling. The trip resistors should be connected to the same node as VIN pin of the device when this filter is applied. The filter resistor should be as small as possible since a voltage drop across this resistor biases the OCP trip point. UNDERVOLTAGE LOCKOUT PROTECTION There are two undervoltage lock out protections (UVLO) in TPS51020. One is for VIN, which has a typical trip threshold voltage 3.9 V and trip hysteresis 200 mV. The other is for VREF5, which has a typical trip threshold voltage 3.65 V and trip hysteresis 300 mV. If either is triggered, the device resets and waits for the voltage to rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger the fault counter to latch off the part. OVERVOLTAGE PROTECTION For overvoltage protection (OVP), the TPS51020 monitors INVx voltage. When the INVx voltage is higher than 0.95V (+12%), the OVP comparator output goes high (after a 20-µs delay) and the circuit latches the top MOSFET driver OFF, and bottom driver ON for the SMPS detected overvoltage. In addition, the output discharge (softstop) function is enabled to discharge the output capacitor. The fault latch can be reset by either toggling VIN or bringing DDR , ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode. UNDERVOLTAGE PROTECTION For undervoltage protection (UVP), the TPS51020 monitors INVx voltage. When the INVx voltage is lower than 0.55 V (−35 %), the UVP comparator output goes high, and the internal FLT timer starts to count PWM oscillator pulses. After 4096 clock pulses, the part latches off. Both top and bottom drivers are turned off at this condition. Output discharge (soft-stop) function is enabled to discharge the output capacitor. The fault latch can be reset by either toggling VIN or bringing DDR , ENBL1 and ENBL2 all low. Be sure to bring DDR high prior to ENBLx when TPS51020 is being used in dual mode.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 16 www.ti.com Overcurrent protection (OCP) is achieved by comparing the drain to source voltage of the high-side and low-side MOSFET to a set point voltage. This voltage appears at the TRIPx pin and is defined by the conversion voltage, typically VIN, minus the I × R drop of the ITRIP current flowing through the external resistor connected to the conversion voltage. The offset of the internal comparators also plays a role in determining the overall accuracy and set point of the OCP limit. When the drain-to-source voltage of the synchronous MOSFET exceeds the set point voltage created by the I × R drop (usually 20 mV to around 150 mV), the synchronous MOSFET on-time is extended into the next pulse and the high-side MOSFET OCP comparator is enabled. If during the subsequent high-side on-time the drain-to-source voltage of the high-side MOSFET exceeds the set point voltage, then the high-side on-time pulse is terminated. This low-side extension/high-side termination action has the effect of decreasing the output voltage until the UVP circuit is activated to turn off both the high-side and low-side drivers. The TPS51020 I TRIP current has a temperature coefficient of 4200 PPM/°C. The threshold voltage for the OCP comparator is set by I × R drop across the trip resistor. The ITRIP current is 12.5-µA (typ) at R.T. so that the OCP point is given by following formula, R TRIP /C0043 R DS(on)/C0032/C0466IOCP /C0041IRIPPLE 2 /C0467 12.5/C003210/C00426 Precaution should be taken with board layout in order to design OCP point as desired. The conversion voltage point must avoid high current path. Any voltage difference between the conversion point and VIN input for the TPS51020 is included in the threshold voltage. VIN plane layout should consider the other channels high-current path as well. A brief discussion is required for TRIP2 function. When TRIP2 is connected, via a resistor to GND, only low-side OCP is used. This is the case for cascade configuration been selected. In this mode, UVP does not play a roll in the shut off action and there is only a short delay between the over current trigger level been hit and the power MOSFETs turn off. However, as with UVP, the SSTRTx pins are discharged and both SMPS goes though a restart. LAYOUT CONSIDERATIONS Below are some points to consider before the layout of the TPS51020 design begins. /C0068Signal GND and power GND should be isolated as much as possible, with a single point connection between them. /C0068All sensitive analog components such as INV, SSTRT, SKIP, DDR, GND, REF_X, ENBL and PGOOD should be reference to signal GND and be as short as possible. /C0068The source of low-side MOSFET, the Schottky diode anode, the output capacitor and OUTGND should be referenced to power GND and be as short and wide as possible, otherwise signal GND is subject to the noise of the outputs. /C0068PCB trace defined as the node of LL should be as short and wide as possible. /C0068Connections from the drivers to the gate of the power MOSFET should be as short and wide as possible to reduce stray inductance and the noise at the LL node. /C0068The drain of high-side MOSFET, the input capacitor and the trip resistor should be as short and wide as possible. For noise reduction, a 22-pF capacitor C TRIP can be placed in parallel with the trip resistor.

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 17www.ti.com /C0068The output voltage sensing trace and the feedback components should be as short as possible and be isolated from the power components and traces. /C0068The low pass filter for VIN should be placed close to the TPS51020 and be referenced to signal GND. /C0068The bootstrap capacitor CBST (connected from VBST to LL) should be placed close to the TPS51020. /C0068VREG5 requires at least 4.7-µF bypass capacitor which should be placed close to the TPS51020 and be referenced to signal GND. /C0068The discharge (VO1_VDDQ, VO2) should better have a dedicated trace to the output capacitor. In case of limiting the discharge current, series resistors should be added. /C0068Ideally, all of the area directly under the TPS51020 chip should also be signal GND. VBST1 OUT1_U LL1 OUT1_D INV1 COMP1 SSTRT1 SKIP TPS51020 OUTGND1 TRIP1 VIN TRIP2 VO1_VDDQ DDR GND REF_X VREG5 REG5_IN OUTGND2 ENBL1 ENBL2 VO2 12 19OUT2_DPGOOD LL2 OUT2_U VBST2 SSTRT2 COMP2 INV2 Cvinbp Rvin L01 L_FET1 Cin1 H_FET1 Co1 Rtrip1Ctrip1 L02 L_FET2 Cin2 H_FET2 Co2 RtripsCtrip2 Cvreg5 Cin CH1 Output Voltage (+) CH1 Output Voltage (GND) Input Voltage (+) Input Voltage (GND) CH2 Output Voltage (GND) CH2 Output Voltage (+) Power GND Signal GND C BST1 C BST2 Figure 4. PCB Trace Guideline

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 18 www.ti.com 5V_OUT GND TPS51020 COMP2 SSTRT2 PGOOD VO2 ENBL2 ENBL1 REF_X GND DDR VO1_VDDQ SSTRT1 COMP1 REG5_IN VREG5 VBST2 OUT2_U LL2 OUT2_D OUTGND2 TRIP2 VIN TRIP1 OUTGND1 OUT1_D LL1 OUT1_U VBST1 3.3V_OUT 3.3V_X 5V_X GND GND GND GND GND GND (10V_REF) R04R01 1.8k R03 10k C12 6800p R02 330 C14 3900p C15 0.01u C19 0.01u C20 3300p R08 2.7k 49.7k R09 10k R11 28.8k R10 330 2200p C22 R101 100kR101 100k 100k R102 R07 100k C11 0.1u 0.1u C08 R12 Q01 Q02 R13 18k 18k R14 Q04 Q03 R15 L02 C05a 150u C05c 0.01u C13 4.7u C04a 150u C04c 0.01u L01 C01a 22u C02 2.2ux2 C03 2.2ux2 51k 51k 51k 51k Q10 Q11 Q12 Q13 Q14 Q15 R200 R201 R202 R203 C01a : Sanyo 35SVPD22M C01c, C02, C03, C27 : Taiyo Yuden GMK325BJ225MH−B C04a, C05a : Panasonic EEFUE0J151R Q01, Q03 : Fairchild FDS6612A Q02, Q04 : Fairchild FDS6690S L01, L02 : Sumida CEP125−4R0MC−H R16 0C27 C01c 2.2u VBAT

8 V to 20 V

Figure 5. Typical Application Circuit: Dual (5V/6A + 3.3V/6A) from VBAT Figure 6. Typical Application Circuit: DDR(2.5V/6A + 1.25V/6A) from VBAT

/C0084/C0080/C0083/C0053/C0049/C0048/C0050/C0048 /C0261 SLUS564C − JULY 2003 − REVISED OCTOBER 2008 19www.ti.com 2.5V_OUT TPS51020 COMP2 SSTRT2 PGOOD VO2 ENBL2 ENBL1 REF_X GND DDR VO1_VDDQ SSTRT1 COMP1 REG5_IN VREG5 VBST2 OUT2_U LL2 OUT2_D OUTGND2 TRIP2 VIN TRIP1 OUTGND1 OUT1_D LL1 OUT1_U VBST1 1.25V_OUT GND GND GND GND GND (VO1_VDDQ/2_REF) R04R01 4.7k R03 3.9k C12 4700p R02 1.2k C14 4700p C15 0.01u C19 0.01u C20 6800p R08 3.9k 7.62k R11 19.7k R10 1.2k 2200p C22 R101 100k 100k R102 R07 100k C11 0.1u 0.1u C08 R12 Q01 Q02 R13 18k 18k R14 Q04 Q03 R15 L02 C05a 5.6u 150u C05c 0.01u C13 4.7u C04a 150u C04c 0.01u L01 5.6u C01a 22u C02 2.2ux2 C04d 150u 150u C05b C04b 150u (EXT_5V) GND 2.5V_OUT C01a : Sanyo 35SVPD22M C01c, C02, C27 : Taiyo Yuden GMK325BJ225MH−B C04a, C05a, C04b, C05b,C04d : Panasonic EEFUE0J151R Q01, Q03 : Fairchild FDS6612A Q02, Q04 : Fairchild FDS6690S L01, L02 : Sumida CEP125−5R6MC−H R16 2.2u0 C01cC27 VBAT Figure 7. Typical Application Circuit: DDR (2.5V/6A + 1.25V/3A) Cascade

Figure 17. Load Transient Response

2 A/div

1 A ≤ IOUT1 ≤ 6 A, 1A/ms

Figure 18. Simultaneous Startup

2 V/ div

1 V/div VOUT2

Figure 19. Offset Startup

1 V/div

Figure 20. Soft-Stop

5 V/div ENBL2

5 V/div

2 V/div

Figure 21. Cascade Configuration DDR Mode

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS51020DBT Active Production TSSOP (DBT) | 30 60 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PS51020 TPS51020DBT.B Active Production TSSOP (DBT) | 30 60 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PS51020 TPS51020DBTR Active Production TSSOP (DBT) | 30 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PS51020 TPS51020DBTR.B Active Production TSSOP (DBT) | 30 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PS51020 TPS51020DBTRG4 Active Production TSSOP (DBT) | 30 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 PS51020 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51020DBTR TSSOP DBT 30 2000 367.0 367.0 38.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS51020DBT DBT TSSOP 30 60 530 10.2 3600 3.5 TPS51020DBT.B DBT TSSOP 30 60 530 10.2 3600 3.5 Pack Materials-Page 3

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Summary

DUAL, VOLTAGE MODE, DDR SELECTABLE, SYNCHRONOUS, STEP-DOWN CONTROLLER FOR NOTEBOOK SYSTEM POWER REVISED OCTOBER 2008

Description