TPS50602HFG/EM

TPS50602-SP TI1 | Alldatasheet

Document overview

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Technical content

Load per Die (A) Efficiency (%) 0 1 2 3 4 5 6 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -55°C 25°C 125°C VIN = 3.3 V F = 500 kHzSW Includes 2 outputs ADVANCE□INFORMATION TPS50602-SP PHASE1 VSENSE1 PHASE2 VSENSE2 PGND2 THERMAL PAD PGND1 VOUT1 VOUT2 PVIN1 VIN1 VIN2 SSTR1 RT1 COMP1 SSTR2 RT2 COMP2 SYNC1 SYNC2 REFCAP1 REFCAP2 PVIN2 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. TPS50602-SP SLVSDJ9 –OCTOBER 2018 TPS50602-SPRadiationHardened3-Vto7-VInput, 12-ASingle,6-ADualOutputSynchronousBuckConverter

1 Features

1• 5962R18207: – Radiation Hardened up to TID 100 krad(Si) – Single Event Latchup (SEL), Single Event Burnout (SEB), and Single Event Gate Rupture (SEGR) Immune to LET = 75 MeV-cm2/mg – SET/SEFI Cross-Section Plot Available

• Peak Efficiency: 95% (VO = 3.3 V)
• Integrated 48-mΩ/37-mΩ MOSFETs (PVIN = 5 V)
• Power Rail: 3 to 7 V on VIN
• 12-A Maximum Output Current in Single Output Configuration and 6-A Maximum Output Current in Dual Output Configuration
• Fixed 500-kHz Switching Frequency Using Internal Oscillator or External Clock Between 100 kHz to 1 MHz at 180° Out of Phase
• 0.804-V ±1.5% Voltage Reference over Temperature, Radiation Tolerance and Line and Load Regulation
• Monotonic Start-Up into Pre-biased Outputs
• Adjustable Soft Start Through External Capacitor
• Input Enable and Power-Good Output for Power Sequencing
• Power Good Output Monitor for Undervoltage and Overvoltage
• Adjustable Input Undervoltage Lockout (UVLO)
• 64-Pin Thermally-Enhanced Ceramic Quad Flatpack Package (HFG)
• Engineering Evaluation (/EM) Samples are Available(1)

2 Applications

• Space Satellite Point of Load Supply for FPGAs, Microcontrollers, Data Converters and ASICs
• Space Satellite Payloads
• Radiation Hardened and Tolerant Point of Load

Applications

• Available in Military (–55°C to 125°C) Temperature Range

3 Description

The TPS50602-SP is a dual TPS50601A-SP die, TID and SEE radiation hardened, 7-V, 12-A single output or 6-A dual output synchronous step-down converter, which is optimized for ultra small form factor designs. This is achieved integrating highly efficiency high-side and low-side MOSFETs and excellent thermal performance. Further space savings are achieved through the dual output configuration, which reduces the overall solution size if multiple 6-A rails are needed. The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone power supply or in tracking applications. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins. Thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature. Device Information(2) PART NUMBER GRADE PACKAGE 5962R1820701VXC RHA – 100 krad(Si) HFG (64) TPS50602HFG/EM Engineering Evaluation(1) (1) These units are intended for engineering evaluation only. They are processed to a noncompliant flow. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of –55°C to 125°C or operating life. (2) For all available packages, see the orderable addendum at the end of the data sheet. Dual Output Configuration Efficiency at VIN = PVIN = 3.3 V

ADVANCE□INFORMATION TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

7.2 One of Two Dice of TPS50602-SP Functional Block

12 Mechanical, Packaging, and Orderable

4 Revision History

October 2018 * Initial release.

ADVANCE□INFORMATION GND EN2 RT2 SYNC2 VIN1 PVIN1 PVIN1 PVIN1 PVIN1 PVIN1 PVIN1 PVIN1 PHASE1 PHASE1 PHASE1 PHASE1 PHASE1 PVIN2 PGND2 PGND2 PGND2 PGND2 PHASE1 PHASE1 REFCAP1 VSENSE1 COMP1 SSTR1 PWRGD1 PHASE2 PHASE2 PHASE2 PHASE2 PHASE2 PHASE2 PHASE2 REFCAP2 VSENSE2 COMP2 SSTR2 PWRGD2 PGND2 PVIN2 PVIN1 PGND1 PGND1 PGND1 PGND1 PGND1 PGND1 PGND1 EN1 SYNC1 VIN2 PVIN2 RT1 GND PVIN2 PVIN2 PVIN2 PVIN2 PVIN2 PGND2 PGND2 234567891011121314151617181920 5251504948474645444342414039383736353433 THERMAL PAD (14 x 12 mm) TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Thermal pad and package lid are internally connected to GND.

5 Pin Configuration and Functions

NO. NAME 1, 33 GND — Return for control circuitry/thermal pad(1). 2 EN2 I Enable pin for die 2. This pin has an internal pullup so if left floating, the device is still enabled. Adjust the input undervoltage lockout (UVLO) with two resistors. 3 RT2 I/O In internal oscillation mode, a resistor is connected between the RT pin and GND to set the switching frequency for die 2. A resistor corresponding to 500 kHz must be connected to this pin. 4 SYNC2 I/O External system clock input for die 2. The clock from SYNC1 is connected to this pin to run at 500 kHz. 5 VIN1 I Supplies the power to the controller for die 1. 6, 7, 8, 9, 10, 11, 12, 13 PVIN1 I Power input for die 1. 14, 15, 16, 17, 18, 19, PGND1 — Return for low-side power MOSFET for die 1.

ADVANCE□INFORMATION TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Pin Functions (continued) PIN I/O DESCRIPTION NO. NAME 21, 22, 23, 24, 25, 26, PHASE1 O Switch node for die 1. 28 REFCAP1 O Capacitor for internal reference. A 470 nF is recommended to be connected between REFCAP1 pin and GND. 29 VSENSE1 I Inverting input of the gm error amplifier for die 1. 30 COMP1 I/O Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.

31 SSTR1 I/O

Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. 32 PWRGD1 O Power Good fault pin is an open-drain connection. Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or during slow start. 34 EN1 I Enable pin for die 1. This pin has an internal pullup so if left floating, the device is still enabled. Adjust the input undervoltage lockout (UVLO) with two resistors. 35 RT1 I/O Resistor to set switching frequency. RT1 should be left floating to generate an output clock at the SYNC1 pin. 36 SYNC1 I/O External system clock input for die 1. This pin outputs a 500 kHz clock signal at 180° out of phase from the internal clock from die 1. This clock is used to drive SYNC2. 37 VIN2 I Supplies the power to the controller for die 2. 38, 39, 40, 41, 42, 43, 44, 45 PVIN2 I Power input for die 2. 46, 47, 48, 49, 50, 51, PGND2 — Return for low-side power MOSFET for die 2. 53, 54, 55, 56, 57, 58, PHASE2 O Switch node for die 2. 60 REFCAP2 O Capacitor for internal reference. A 470 nF is recommended to be connected between REFCAP2 pin and GND. 61 VSENSE2 I Inverting input of the gm error amplifier for die 2. 62 COMP2 I/O Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.

63 SSTR2 I/O

Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing. 64 PWRGD2 O Power Good fault pin is an open-drain connection. Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or during slow start.

ADVANCE□INFORMATION TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See derating curve.

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature (unless otherwise noted)(1) MIN MAX UNIT Input voltage VIN(2) –0.3 7.5 V PVIN(2) –0.3 7.5 EN –0.3 5.5 VSENSE –0.3 3.3 COMP –0.3 3.3 PWRGD –0.3 5.5 SS/TR –0.3 5.5 RT -0.3 5.5 SYNC -0.3 7.5 Output voltage REFCAP –0.3 3.3 VPH –1 7.5 PH 10-ns transient –3 7.5 Vdiff (GND to exposed thermal pad) –0.2 0.2 V Source current PH Current limit Current limit A RT ±100 µA Sink current PH Current limit Current limit A PVIN Current limit Current limit A COMP ±200 µA PWRGD –0.1 5 mA Operating junction temperature –55 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±750 V V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) TBD V

6.3 Recommended Operating Conditions

TJ Junction operating temperature –55 125 °C

6.4 Thermal Information

UNITHFG (CQFP)

64 PINS

RθJC(bot) Junction-to-case (bottom) thermal resistance 0.56 °C/W

ADVANCE□INFORMATION TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Measured at pins. (2) Ensured by design only. Not tested in production. (3) Parameter is not tested in production.

6.5 Electrical Characteristics

TA = –55°C to 125°C, VIN = PVIN = 3.0 V to 7.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN AND PVIN PINS) PVIN operating input voltage 3.0 7.0 V PVIN internal UVLO threshold PVIN rising 2.50 V PVIN internal UVLO hysteresis 450 mV VIN operating input voltage 3.0 7.0 V VIN internal UVLO threshold VIN rising 2.75 3.0 V VIN internal UVLO hysteresis 150 mV VIN shutdown supply current VEN = 0 V 1.35 2.5 mA VIN operating – non switching supply current VSENSE = VBG 5 10 mA ENABLE AND UVLO (EN PIN) Enable threshold Rising 1.14 1.18 V Falling 1.05 1.11 Input current VEN = 1.1 V 6.1 μA Hysteresis current VEN = 1.3 V 3.0 μA VOLTAGE REFERENCE Voltage reference 0 A ≤ Iout ≤ 6 A, –55 to 125°C 0.792 0.804 0.816 V REFCAP voltage 470 nF 1.211 V MOSFET High-side switch resistance(1) PVIN=VIN= 3.0 V, lead length = 4 mm 52 mΩ High-side switch resistance(1) PVIN=VIN= 5.0 V, lead length = 4mm 48 mΩ High-side switch resistance(1) PVIN=VIN= 7.0 V, lead length = 4 mm 46 mΩ Low-side switch resistance(1) PVIN=VIN= 3.0 V, lead length = 4 mm 38 mΩ Low-side switch resistance(1) PVIN=VIN= 5.0 V, lead length = 4 mm 37 mΩ Low-side switch resistance(1) PVIN=VIN= 7.0 V, lead length = 4mm 36 mΩ ERROR AMPLIFIER Error amplifier transconductance (gm)(2) –2 μA < ICOMP < 2 μA, V(COMP) = 1 V 1000 1400 2000 μS Error amplifier dc gain(2) VSENSE = 0.804 V 10000 V/V Error amplifier source/sink(2) V(COMP) = 1 V, 100-mV input overdrive -250 ±115 250 μA Error amplifier output resistance 7 MΩ Start switching threshold(2) 0.25 V COMP to Iswitch gm(2) 22 S CURRENT LIMIT High-side switch current limit threshold (3) VIN = 7.0 V 11 A Low-side switch sourcing current limit(3) VIN = 7.0 V 10 A Low-side switch sinking current limit VIN = 7.0 V 3 A THERMAL SHUTDOWN Thermal shutdown 170 °C Thermal shutdown hysteresis 30 °C INTERNAL SWITCHING FREQUENCY Internally set frequency RT = Open 395 500 585 kHz EXTERNAL SYNCHRONIZATION SYNC out low-to-high rise time (10%/90%) Cload = 25 pF 70 111 ns SYNC out high-to-low fall time (90%/10%) Cload = 25 pF 6 15.5 ns

ADVANCE□INFORMATION TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –55°C to 125°C, VIN = PVIN = 3.0 V to 7.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) Bench verified. Not tested in production. (5) Parameter is production tested at nominal voltage with VIN = PVIN = 5 V. Falling edge delay time(4) 180 ° SYNC out high level threshold IOH = 50 µA 2 V SYNC out low level threshold IOL = 50 µA 600 mV SYNC in low level threshold PVIN=VIN= 3.0 V 900 mV SYNC in high level threshold PVIN=VIN= 3.0 V 2.45 V SYNC in low level threshold PVIN=VIN= 7.0 V 900 mV SYNC in high level threshold PVIN=VIN= 7.0 V 4.25 V SYNC in frequency range(5) Percent of program frequency –5% 5% 100 1000 kHz PH (PH PIN) Minimum on time Measured at 10% to 90% of VIN, 25°C, IPH = 2 A 190 235 ns SLOW START AND TRACKING (SS/TR PIN) SS charge current 1.5 2.5 3 μA SS/TR to VSENSE matching V(SS/TR) = 0.4 V 30 90 mV POWER GOOD (PWRGD PIN) VSENSE threshold VSENSE falling (fault) 91 % Vref VSENSE rising (good) 94 % Vref VSENSE rising (fault) 109 % Vref VSENSE falling (good) 106 % Vref Output high leakage VSENSE = Vref, V(PWRGD) = 5 V 30 181 nA Output low I(PWRGD) = 2 mA 0.3 V Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.6 1 V Minimum SS/TR voltage for PWRGD 1.55 V

6.6 Typical Characteristics

System Efficiency curves (Figure 4, Figure 5, and Figure 6) include 2 outputs. Figure 1. Current Sharing Figure 2. High-Side RDS(On) Figure 3. Low-Side RDS(On) Figure 4. Efficiency at VIN = PVIN = 3.3 V, FSW = 500 kHz Figure 5. Efficiency at VIN = PVIN = 5 V, FSW = 500 kHz Figure 6. Efficiency at VIN = PVIN = 5 V, FSW = 100 kHz

ADVANCE□INFORMATION TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS050602-SP is a dual TPS50601A-SP die device that can be configured in dual output or single output configuration. Each die is a 7-V, 6-A synchronous step-down (buck) converter with two integrated MOSFETs, a PMOS for the high side and a NMOS for the low side. To improve performance during line and load transients, the device implements a constant frequency, peak current mode control, which also simplifies external frequency compensation. The 500-kHz switching frequency allows for efficiency and size optimization when selecting the output filter components. The device is designed for safe monotonic startup into prebiased loads. The default start up is when VIN is typically 3 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage UVLO with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pullup current. The total operating current for the device is approximately 5 mA when not switching and under no load. When the device is disabled, the supply current is typically less than 2.5 mA. The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 6 A. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications. The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open-drain MOSFET which is pulled low when the VSENSE pin voltage is less than 91% or greater than 109% of the reference voltage VREF and asserts high when the VSENSE pin voltage is 94% to 106% of the VREF. The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during power-up. A small-value capacitor or resistor divider should be coupled to the pin for slow start or critical power-supply sequencing requirements. The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 106% of the VREF. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections, which help control the inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the slow-start circuit automatically when the junction temperature drops 10°C (typical) below the thermal shutdown trip point.

ADVANCE□INFORMATION ERROR AMPLIFIER UVLO Current Sense Oscillator Slope Compensation and Clamp Voltage Reference VSENSE_x SS/TR_x COMP_x PH_x REFCAP_x VIN_x PGND_x Thermal Shutdown EN_x Enable Comparator Shutdown 1.14 V Logic Shutdown PWRGD_x Thermal Pad/GND_x Power Stage & Deadtime Control Logic LS MOSFET Current Limit OV Minimum Clamp Pulse Skip Ip Ih PVIN_x UV HS MOSFET Current Comparator Current Sense Overload Recovery SYNC Detect SYNC_x RT_x RT Bias V/I PVIN 2.75 V UVLO 2.49 V One of Two Dice TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

7.2 One of Two Dice of TPS50602-SP Functional Block Diagram

7.3 Feature Description

7.3.1 VIN and Power VIN Pins (VIN and PVIN)

The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power converter system. Both pins have an input voltage range from 3 to 7 V. A voltage divider connected to the EN pin can adjust the input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin helps to provide consistent power-up behavior.

7.3.2 Voltage Reference

The voltage reference system produces a precise voltage reference as indicated in Electrical Characteristics.

7.3.3 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. TI recommends to use 1% tolerance or better resistors. Start with a 10 kΩ for RTOP and use Equation 1 to calculate RBOTTOM. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.

• VREF = 0.804 V (1)

7.3.4 Safe Start-Up into Prebiased Outputs

7.3.5 Error Amplifier

COMP pin and ground. The error amplifier DC gain is typically 10,000 V/V.

7.3.6 Slope Compensation

subharmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.

7.3.7 Enable and Adjust UVLO

collector output logic to interface with the pin. TPS50602-SP Evaluation Module, (see the TPS50602-SP EVM User's Guide, SLVUB65). with Equation 2 and Equation 3. Figure 7. Adjustable VIN UVLO

• Ih = 3 μA
• Ip = 6.1 μA
• VENRISING = 1.14 V
• VENFALLING = 1.11 V (3)

7.3.8 Fixed Switching Frequency and Synchronization (SYNC)

The two dice in the TPS50602-SP must be operated at the same switching frequency and at 180° out of phase. the RT pin also sets the proper operation of slope compensation. resistance for a given switching frequency, use Equation 4 or the curve in Figure 10.

• RT in kΩ
• FSW in kHz (4)

Figure 10. RT vs Switching Frequency

7.3.9 Slow Start (SS/TR)

time. Equation 5 shows the calculations for the slow-start time (tSS, 10% to 90%) and slow-start capacitor (CSS). The voltage reference (VREF) is 0.804 V and the slow-start charge current (ISS) is 2 μA.

SS/TR pin to ground ensuring proper soft-start behavior.

7.3.10 Power Good (PWRGD)

full current sinking capability when the VIN input voltage is above 3 V. pin is pulled low or the SS/TR pin is below 1.55 V.

7.3.11 Sequencing (SS/TR)

Figure 11. Sequential Start-Up Sequence time, the pullup current source must be doubled in Equation 5.

Figure 12. Ratiometric Start-Up Sequence and tracking resistors, the VSS-OFFSET and ISS are included as variables in the equations. value calculated in Equation 9.

Figure 13. Ratiometric and Simultaneous Start-Up Sequence

7.3.12 Output Overvoltage Protection (OVP)

7.3.13 Overcurrent Protection

7.3.13.1 High-Side MOSFET Overcurrent Protection

intersects the current reference, the high-side switch is turned off.

7.3.13.2 Low-Side MOSFET Overcurrent Protection

current limit at the start of a cycle. off until the start of the next cycle. parallel diode (the high-side MOSFET is still off at this stage).

7.3.14 Thermal Shutdown

7.3.15 Turn-On Behavior

and goes through its soft-start process, the required duty-cycle is less than the minimum controllable on-time. minimum on-pulse is greater than the minimum controllable on-time, the turn-on behavior is normal.

7.3.16 Small Signal Model for Frequency Compensation

added to attenuate high-frequency noise. method. The step-by-step design procedure described in Detailed Design Procedure may also be used. Figure 14. Types of Frequency Compensation

1. Determine the crossover frequency fco. A good starting point is one-tenth of the switching frequency, FSW.

the reference voltage (0.804 V).

ADVANCE□INFORMATION C2 = COUT × RESR C1 = COUT × RL fp = 1 COUT × RL × tN TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Feature Description (continued) 3. Place a compensation zero at the dominant pole using C1 and R3. C1 can be determined by (11) 4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor COUT. (12)

7.4 Device Functional Modes

7.4.1 Fixed-Frequency PWM Control

The device uses fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted into a current reference which compares to the high-side power switch current. When the power switch current reaches the current reference generated by the COMP voltage level, the high-side power switch is turned off and the low-side power switch is turned on.

7.4.2 Continuous Current Mode (CCM) Operation

As a synchronous buck converter, the device normally works in CCM under all load conditions.

ADVANCE□INFORMATION TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS50602-SP device is a highly-integrated synchronous step-down DC-DC converter. The device is used to convert a higher DC-DC input voltage to a lower DC output voltage with a maximum output current of 12-A in single output configuration or 6-A in dual output configuration. The TPS50602-SP user's guide is available on the TI website (see SLVUB66). The guide highlights standard EVM test results, schematic, and BOM for reference (basic design equations in following sections are provided for reference only).

8.2 Typical Application

Figure 15. 12-A Single Output Configuration

ADVANCE□INFORMATION TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated Typical Application (continued) 1. The RT pin of the master device must be left floating. This achieves 2 purposes, to set the frequency to 500 kHz (typical) using the internal oscillator and to configure the SYNC pin of the master device as an output pin with a 500-kHz clock, 180° out of phase respect to the internal oscillator of the master device. For more details, see Fixed Switching Frequency and Synchronization (SYNC) section. 2. The RT pin on slave device should be connected to a resistor such that the frequency of the slave device is within 5% of the master's frequency, 500 kHz in this case. See Figure 10 for reference. 3. SYNC pin of the master device must be connected to the SYNC pin of the slave device. 4. Only a single feedback network is needed connected to the VSENSE pin of the master device. Therefore, both VSENSE pins must be connected. 5. Only a single compensation network is needed connected to the COMP pin of the master device. Therefore both COMP pins must be connected. 6. Only a single soft start capacitor is needed connected to the SS pin of the master device. Therefore both SS pins must be connected. 7. Only a single enable signal (or resistor divider) is needed connected to the EN pin of the master device. Therefore both EN pins must be connected. 8. Since the master device controls the compensation, soft start and enable networks, the factor of 2 must be taken into account when calculating the components associated with these pins. The master-slave mode can also be implemented using an external clock. In such case, a different frequency other than 500 kHz can be used. When using an external clock, only the RT and SYNC pins configuration varies as follows: 1. RT pins of both master and slave device must be connected to a resistor matching the frequency of the external clock being used. See Figure 10 for reference. 2. The external clock is connected to the SYNC pin of the master device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well. 3. An inverted clock (180° out of phase respect to the master device) must be connected to the SYNC pin of the slave device. A 10-kΩ resistor to GND should be connected to the SYNC pin as well. 8.2.2 6-A Dual Output Configuration The 6-A dual output configuration of the TPS50602-SP allows for great area savings. In this case, the 2 dice in the TPS50602-SP can be configured individually as shown in Figure 16 but they must run 180° out of phase at an internal 500-kHz switching frequency (internal oscillator) or an external clock but. If using internal oscillator, the RT1 pin is left floating since SYNC1 is used as an output clock signal for SYNC2. A resistor is then connected to the RT2 pin to set the frequency to 500 kHz. Please refer to Fixed Switching Frequency and Synchronization (SYNC) section for more details regarding switching frequency configuration.

Figure 16. 6-A Dual Output Configuration

8.2.3 Design Requirements

Table 1. Design Parameters

8.2.4 Detailed Design Procedure

8.2.4.1 Operating Frequency

the RT2 pin must have a 95.3-kΩ resistor.

8.2.4.2 Output Inductor Selection

value of the output inductor. For this design example, use KL = 0.45 and the inductor value is calculated to be 1.8 µH for nominal VIN = 5 V.

8.2.4.3 Output Capacitor Selection

load current. The output capacitance needs to be selected based on the more stringent of these three criteria. of view, necessary to accomplish this.

ADVANCE□INFORMATION RESR < VOUTripple Iripple COUT > 1 8 × fSW Iripple VOUTripple TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Where ΔIO is the change in output current, FSW is the regulator switching frequency and ΔVOUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 5% change in VOUT gives a minimum capacitance of 160 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. However, for space applications and large capacitance values, tantalum capacitors are typically used which have a certain ESR value to take into consideration. Equation 15 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where FSW is the switching frequency, VOUTripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 20 mV. Under this requirement, Equation 15 yields 168.75 µF. (15) Equation 16 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 16 indicates the ESR should be less than 7.41 mΩ. (16) For this specific design, taking into consideration the stringent requirements for space applications, two output capacitors of 330 µF (COUT = 660 µF) with ESR = 6 mΩ each have been selected.

8.2.4.4 Slow Start Capacitor Selection

The slow start capacitor CSS, determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS50601A-SP reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be calculated using Equation 5. The example circuit has the soft start time set to an arbitrary value of about 4 ms which requires a 10-nF capacitor. In TPS50601A-SP, ISS is 2-µA typical, and VREF is 0.804

8.2.4.5 Undervoltage Lockout (UVLO) Set Point

The UVLO can be adjusted using the external voltage divider network formed by R1 and R2. R1 is connected between VIN and the EN pin of the TPS50601A-SP and R2 is connected between EN and GND. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above selected voltage (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below (UVLO stop or disable) voltage. Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified in Table 1, the nearest standard resistor value for R1 is 10 kΩ and for R2 is 3.4 kΩ.

8.2.4.6 Output Voltage Feedback Resistor Selection

The resistor divider network RTOP and RBOTTOM is used to set the output voltage. For the example design, 10 kΩ was selected for RTOP. Using Equation 1, RBOTTOM is calculated as 4.77 kΩ. A 4.64-kΩ resistor was used for this design.

8.2.4.7 Compensation Component Selection

There are several industry techniques used to compensate DC-DC regulators. For this design, type 2B compensation is used as shown in the Small Signal Model for Frequency Compensation section.

ADVANCE□INFORMATION fco = ¨fpmod × fSW fco = §fpmod × fzmod fzmod = 1 tN × RESR × COUT fpmod = IOUT tN × VOUT × COUT TPS50602-SP www.ti.com SLVSDJ9 –OCTOBER 2018 Product Folder Links: TPS50602-SP Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated First, the modulator pole, fpmod, and the RESR zero, fzmod must be calculated using Equation 17 and Equation 18. Use Equation 19 and Equation 20 to estimate a starting point for the closed loop crossover frequency fco, then the required compensation components may be derived. For this design example, fpmod is 0.58 kHz and fzmod is 80.36 kHz. Equation 19 is the geometric mean of the modulator pole and the ESR zero and Equation 20 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 19 yields 6.82 kHz and Equation 20 yields 12.03 kHz. A frequency of 10 kHz is chosen as the intended crossover frequency. (17) (18) (19) (20) Now the compensation components can be calculated using Equation 10 and Equation 11. The standard values for R3 and C1 are 4.02 kΩ and 68 nF, respectively.

ADVANCE□INFORMATION TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

8.2.5 Application Curve

The evaluation module for the TPS50602-SP was used to capture a load step response of the device. The testing conditions were:

• VIN = PVIN = 5 V
• VOUT = 2.5 V
• Load step = 0 A to 5 A
• Switching frequency = 500 kHz

9 Power Supply Recommendations

The TPS50602-SP is designed to operate from an input voltage supply range between 3 V and 7 V. This supply voltage must be well regulated and proper local bypass capacitors should be used for proper electrical performance from PVIN to GND and from VIN to GND. Due to stringent requirements for space applications, typically additional input bypass capacitors are used. The TPS50602-SP Evaluation Module uses 6, 22-µF ceramic capacitors in addition to 3, 150-µF tantalum capacitors from PVIN to GND and a 4.7 µF and a 0.1 µF from VIN to GND.

10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. Standard good practices should be applied. Some basic guidelines follow:

• The top layer contains the main power traces for PVIN, VIN, VOUT, and PHASE. Also on the top layer are connections for the remaining pins of the TPS50602-SP and a large top side area filled with ground.
• The top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor and the output filter capacitor.
• Thermal pad can be electrically floating or connected externally. If electrically connected externally then it must be connected to GND. Customer should evaluate their system performance when thermal pad is electrically isolated and thermally conductive.
• Preferred approach is that GND pin should be tied directly to the power pad under the IC and the PGND.
• The PVIN and VIN pins should be bypassed to ground with ceramic capacitors placed as close as possible to the pins.
• Since the PH connection is the switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling.
• The RT, REFCAP and COMP pins are sensitive to noise so the respective components should be located as close as possible to the IC and routed with minimal lengths of trace.
• The feedback voltage signal VSENSE should be routed away from the switching node.

10.2 Layout Example

Figure 17. PCB Layout Example

ADVANCE□INFORMATION TPS50602-SP SLVSDJ9 –OCTOBER 2018 www.ti.com Product Folder Links: TPS50602-SP Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following: TPS50602EVM-CVAL Evaluation Module, SLVUB66

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Device Nomenclature

RHA Radiation hardness assurance for space systems

www.ti.com 27-Nov-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PTPS50602HFG/EM ACTIVE CFP HFG 64 1 TBD Call TI Call TI 25 to 25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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