TPS50601-DIE

TPS50601-DIE 1.6-V TO 6.3-V Input, 6-A Synchronous Step Down SWIFT™ Converter (Rev. A)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLVSC37,A]
• PDF pages: 7

Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community TPS50601-DIE SLVSC37A – JUNE 2013– REVISED JUNE 2014 TPS50601-DIE1.6-VTO6.3-VInput,6-ASynchronousStepDownSWIFT™ Converter

1 Features 3 Description

The TPS50601-DIE is a 6.3-V, 6-A synchronous step 1• Split Power Rail: 1.6 V to 6.3 V on PVIN down converter which is optimized for small designs• Power Rail: 3 V to 6.3 V on VIN through high efficiency and integrating the high-side

• Flexible Switching Frequency Options: and low-side MOSFETs. Further space savings are achieved through current mode control, which– Adjustable Internal Oscillator reduces component count, and a high switching– External Sync Capability frequency, reducing the inductor's footprint. – Sync Pin Can Be Configured as a 500-kHz The output voltage startup ramp is controlled by theOutput for Master/Slave Applications SS/TR pin which allows operation as either a stand• Monotonic Start-Up into Pre-Biased Outputs alone power supply or in tracking situations. Power
• Adjustable Slow Start and Power Sequencing sequencing is also possible by correctly configuring the enable and the open drain power good pins.• Power Good Output Monitor for Undervoltage and Overvoltage Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is• Adjustable Input Undervoltage Lockout enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side2 Applications sinking current limit which turns off the low-side• Point of Load Regulation MOSFET to prevent excessive reverse current. Thermal shutdown disables the part when die temperature exceeds thermal shutdown temperature. Ordering Information(1) PACKAGEPRODUCT PACKAGE ORDERABLE PART NUMBER PACKAGE QUANTITYDESIGNATOR TPS50601VTDC1 77 TPS50601 TD Bare die in waffle pack(2) TPS50601VTDC2 10 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Processing is per the Texas Instruments space production baseline and is in compliance with the Texas Instruments Quality Control System in effect at the time of manufacture. Electrical screening consists of DC parametric and functional testing at room temperature only. Unless otherwise specified by Texas Instruments AC performance and performance over temperature is not warranted. Visual Inspection is performed in accordance with MIL-STD-883 Test Method 2010 Condition B at 75X minimum. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLVSC37A –JUNE 2013– REVISED JUNE 2014 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2013) to Revision A Page

2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated

www.ti.com SLVSC37A – JUNE 2013– REVISED JUNE 2014 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

5 Bare Die Information

BACKSIDE BOND PAD BOND PADDIE THICKNESS BACKSIDE FINISH POTENTIAL METALLIZATION COMPOSITION THICKNESS 15 mils. Silicon with backgrind Floating Al5TiN 557.5 nm Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

SLVSC37A –JUNE 2013– REVISED JUNE 2014 www.ti.com Bond Pad Coordinates in Microns DESCRIPTION PAD NUMBER X MIN Y MIN X MAX Y MAX GND 1 400.77 5039.325 578.07 5216.625 EN 2 44.19 4169.79 221.49 4347.09 RT 3 44.19 3894.21 221.49 4071.51 SYNC 4 44.19 3618.63 221.49 3795.93 VIN 5 47.565 2952.27 224.865 3129.57 PVIN 6 280.215 2414.115 457.515 2591.415 PVIN 7 280.215 2170.665 457.515 2347.965 PVIN 8 280.215 1928.115 457.515 2105.415 PVIN 9 280.215 1684.665 457.515 1861.965 PGND 10 254.52 1236.285 431.82 1413.585 PGND 11 254.52 1008.315 431.82 1185.615 PGND 12 254.52 780.345 431.82 957.645 PGND 13 254.52 552.375 431.82 729.675 PGND 14 254.52 324.405 431.82 501.705 PGND 15 254.52 96.435 431.82 273.735 PH 16 1590.12 99.405 1767.42 276.705 PH 17 1590.12 321.435 1767.42 498.735 PH 18 1590.12 555.345 1767.42 732.645 PH 19 1590.12 777.375 1767.42 954.675 PH 20 1590.12 1011.285 1767.42 1188.585 PH 21 1590.12 1233.315 1767.42 1410.615 PH 22 1564.335 1684.665 1741.635 1861.965 PH 23 1564.335 1928.115 1741.635 2105.415 PH 24 1564.335 2170.665 1741.635 2347.965 PH 25 1564.335 2414.115 1741.635 2591.415 BOOT 26 1801.71 3352.14 1979.01 3529.44 VSENSE 27 1801.71 3644.145 1979.01 3821.445 COMP 28 1801.71 3940.92 1979.01 4118.22 SS/TR 29 1801.71 4216.5 1979.01 4393.8 PWRGD 30 1463.67 5039.325 1640.97 5216.625 GND 31 1251.09 5039.325 1428.39 5216.625 GND 32 1038.51 5039.325 1215.81 5216.625 GND 33 825.93 5039.325 1003.23 5216.625 GND 34 613.35 5039.325 790.65 5216.6

4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated

www.ti.com 11-Apr-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS50601VTDC1 ACTIVE 0 77 TBD Call TI N / A for Pkg Type TPS50601VTDC2 ACTIVE 0 10 TBD Call TI N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 11-Apr-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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