TPS40041DRBRG4

Low Pin Count, Low VIN (2.5V to 5.5V Synchronous Buck DC-to-DC Controller (Rev. D)

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• Manufacturer or author: Texas Instruments, Incorporated [SLUS700,D]
• PDF pages: 38

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(CONT.) DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTROSTATIC DISCHARGE (ESD) PROTECTION PACKAGE DISSIPATION RATINGS (1) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 One of three short circuit threshold levels may be selected by the addition of an external resistor from the COMP pin to circuit ground. During power on, and before the internal soft start commands the output voltage to rise, the TPS40040/1 enters a calibration cycle, measures the current out of the COMP pin, and selects an internal SCP threshold voltage. At the end of the 1.6-ms calibration time, the output voltage is allowed to rise for a 4-ms soft start. During operation, the selected SCP threshold voltage is compared to the upper MOSFET s voltage drop during its ON time to determine whether there is an overload condition. The packaging of the TPS40040/1 is unique in that the PowerPAD is used as an electrical ground connection as well as a thermal connection. ORDERING INFORMATION OPERATING FREQUENCY PACKAGE TAPE AND REEL QTY. PART NUMBER 300 kHz Plastic 8-pin SON (DRB) 250 TPS40040DRBT 300 kHz Plastic 8-pin SON (DRB) 3000 TPS40040DRBR 600 kHz Plastic 8-pin SON (DRB) 250 TPS40041DRBT 600 kHz Plastic 8-pin SON (DRB) 3000 TPS40041DRBR over operating free-air temperature range (unless otherwise noted, all voltages are with respect to GND.) PARAMETER VALUE UNIT VDD 6.5 SW to 10.5 SW transient ns) BOOT SW+6.5 V HDRV SW to SW+6.5 EN FB, LDRV -0.3 to 6.5 COMP -0.3 to Operating junction temperature -40 to 150 C Storage junction temperature -55 to 150 over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT V IN Input voltage 2.25 5.5 V T J Junction temperature -40 125 C PARAMETER MIN TYP MAX UNIT Human body model 2500 V CDM 1500 V THERMAL IMPEDANCE T A 25C POWER RATING T A 85C POWER RATING JUNCTION-TO-AMBIENT 48C/W 0.8W (1) For more information on the DRB package and the test method, refer to TI technical brief, literature number SZZA017. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com ELECTRICAL CHARACTERISTICS TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 T J -40 C to 85C VDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Supply VDD Input voltage range 2.25 5.5 V IDD sd Shutdown EN VDD 100 180 µ A IDDq Quiescent FB 0.8 V 1.0 2.0 mA IDDs Switching current No load at HDRV/LDRV 2.0 UVLO ON Minimum turn-on voltage 1.95 2.05 2.15 V UVLO HYS Hysteresis 130 200 mV Oscillator/ Ramp Generator f PWM TPS40040 PWM frequency 2.25 V VDD 5.5 V 250 300 350 kHz f PWM TPS40040 PWM frequency VDD 5.0 T J 70C 270 300 330 kHz f PWM TPS40041 PWM frequency 2.25 V VDD 5.5 V 500 600 700 kHz f PWM TPS40041 PWM frequency VDD 5.0 T J 70C 540 600 660 kHz V RAMP Ramp amplitude PP V PEAK V VALLEY 0.75 0.87 1.0 V V VALLEY Ramp valley voltage 0.37 V PWM MAXDUTY Maximum duty cycle, TPS40040 V FB 2.25 V VDD 5.5 V Maximum duty cycle, TPS40041 V FB 2.25 V VDD 5.5 V MINDUTY Minimum duty cycle MIN pulse Minimum width control range before Minimum controllable pulse width 150 ns width (1) jumping to zero. Error Amplifier VDD 5.0 T J 70C 593.5 600.0 606.5 V FB FB input voltage mV 2.25 V VDD 5.5 -40C T J 590 610 125C I FB FB input bias current 150 nA I OH 0.5 mA, V FB VDD 5.5 V OH High level output voltage 2.0 2.5 V V V OL Low level output voltage I OL 0.5 mA, V FB VDD 150 mV I OH Output source current V COMP 0.7 V FB GND mA I OL Output sink current V COMP 0.7 V FB VDD G BW (1) Gain bandwidth MHz A OL Open loop gain dB Short Circuit Protection Resistor COMP to GND 2.4 k Ω T J TH1 Low short circuit threshold voltage 105 130 25C Medium short circuit threshold Default: No resistor COMP to GND, V TH2 145 180 215 mV voltage T J 25C Resistor COMP to GND k Ω T J V TH3 High short circuit threshold voltage 250 310 370 25C V TH(tc) (1) Threshold temperature coefficient 3100 ppm Minimum HDRV pulse time in over t ON(oc) (1) 200 current ns t SWOCblank SW leading edge blanking pulse in 100 (1) over current detection t HICCUP Hiccup time between restarts ms (1) Ensured by design. Not production tested. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) T J -40 C to 85C VDD (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Soft Start/Enable Calibration time before softstart t CAL (2) 1.0 1.6 2.5 begins ms t SS (2) Soft start time FB rise time from V to 600 mV 3.0 4.0 6.0 t REG Time to voltage regulation Sum of t CAL plus t SS 4.0 5.6 8.5 V EN Enable threshold EN voltage w.r.t. VDD -0.8 -1.2 -1.6 V V ENHYS Enable hysteresis mV Bootstrap R BOOT3V3 V BOOT to VDD, VDD 3.3 V Bootstrap switch resistances Ω R BOOT5V V BOOT to VDD, VDD V Output Driver V BOOT V SW 3.3 I SRCE 100 R HDHI3V3 HDRV pull-up resistance 3.0 5.5 mA R HDLO3V3 HDRV pull-down resistance V BOOT V SW 3.3 I SINK 100 mA 1.5 Ω R LDHI3V3 LDRV pull-up resistance VDD 3.3 I SOURCE 100 mA 3.0 5.5 R LDLO3V3 LDRV pull-down resistance VDD 3.3 I SINK 100 mA 1.0 2.0 t RISE (3) LDRV, HDRV rise time C LOAD nF t FALL (3) LDRV, HDRV fall time C LOAD nF ns T DEAD HL Adaptive timing HDRV to LDRV No load T DEAD LH Adaptive timing LDRV to HDRV No load SW Node I LEAK Leakage current EN VDD µ A Thermal Shutdown t SD (3) Shutdown temperature 145 C Hysteresis (2) t CAL and t SS track with temperature and input voltage (3) Ensured by design. Not production tested. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com TYPICAL CHARACTERISTICS −40 60 120 Temperature − C 1.100 1.000 0.900 0.800 0.700 0.500 0.400 −20 0 40 80 100 0.600 VDD = 2.25 V VDD = 5.5 V IDDq − mA 60 120 Temperature − C −20 0 40 80 10020 VDD = 2.25 V VDD = 5.5 V −40 110 105 100 IDDsd − µA UVLO Threshold − V −40 60 120 Temperature − C 2.150 2.100 2.050 2.000 1.950 1.850 1.800 −20 0 40 80 100 1.900 2.200 Turn ON Turn OFF −40 60 120 Temperature − C −0.9 −1.0 −1.1 −1.2 −1.3 −1.5 −1.6 −20 0 40 80 100 −1.4 −0.8 VDD = 5 V Enable Threshold Relative to VDD − V Frequency − KHz −40 60 120 Temperature − C 350 325 300 275 250 −20 0 40 80 10020 VDD =2.25 V VDD =3.9 V VDD = 5 V Frequency − KHz −40 60 120 Temperature − C 700 650 600 500 −20 0 40 80 100 550 VDD = 2.25V VDD = 3.9V VDD = 5.5V TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Quiescent Current (Non-Switching) Shutdown Current Figure Figure UVLO Threshold EN Threshold Figure Figure Oscillator Frequency (TPS40040) Oscillator Frequency (TPS40041) Figure Figure Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com VFB − mV −40 60 120 Temperature − C 610 608 604 602 600 594 590 −20 0 40 80 100 596 592 598 606 VDD = 2.25 V VDD = 3.9 V VDD = 5.5 V −40 60 120 Temperature − C 4.50 4.45 4.40 4.35 4.25 4.20 −20 0 40 80 100 4.30 VDD = 5 V TSS − ms Gain −40 60 120 Temperature − C 6.1 6.0 5.9 5.8 5.6 5.5 −20 0 40 80 100 5.7 VDD = 5 V Gain −40 60 120 Temperature − C 6.0 5.9 5.8 5.7 5.6 5.5 −20 0 40 80 10020 VDD = 5 V −40 60 120 Temperature − C 450 400 300 250 200 100 −20 0 40 80 100 150 350 R C = 2.5 kΩ R C =nil R C = 12.5 kΩ ILIM Threshold − mV −40 60 120 Temperature − C −20 0 40 80 100 VDD = 3.3 V VDD = 5 V Switch Resistance − Ω TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) Soft Start Time FB Voltage Figure Figure PWM Gain (TPS40040) PWM Gain (TPS40041) Figure Figure 10. ILIM Threshold Bootstrap Switch Resistance Figure 11. Figure 12. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Pulse Width − ns −40 60 120 Temperature − C 130 125 120 115 110 100 −20 0 40 80 100 105 VDD = 2.25 V VDD = 5.5 V Pulse Width − ns −40 60 120 Temperature − C 100 −20 0 40 80 100 VDD = 2.25 V VDD = 5.5 V −40 60 120 Temperature − C 0.00 −0.50 −0.10 −0.15 −0.20 −0.40 −0.50 −20 0 40 80 100 −0.35 VDD = 5.5 V −0.45 −0.30 −0.25ISW − µA Duty Cycle − % −40 60 120 Temperature − C 100 −20 0 40 80 10020 VDD = 2.25 V VDD = 5.5 V TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) Minimum Controllable Pulse Width (TPS40040) Minimum Controllable Pulse Width (TPS40041) Figure 13. Figure 14. Maximum Duty Cycle SW Node Leakage Current Figure 15. Figure 16. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com DEVICE INFORMATION TERMINAL CONFIGURATION EN FB COMP VDD HDRV SW BOOT LDRV 54 GND TPS40040/1 TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The package is an 8-pin SON (DRB) package. Note: The thermal pad is an electrical ground connection. Figure 17. DRB Package Terminal Configuration (Top View) Table TERMINAL FUNCTIONS TERMINAL I/O NO. Input (bootstrapped) supply to the high-side gate driver for PWM enabling the gate of the high side FET to be driven above the input supply rail. Connect a ceramic capacitor from this pin to SW. This capacitor is charged from the VDD pin voltage through an internal switch. BOOT I The switch is turned ON during the off time of the converter. To slow down the turn on of the external MOSFET, a small resistor Ω to Ω may be placed in series with the bootstrap capacitor. See

Applications

value. Output of the error amplifier and connection node for loop feedback components. The voltage at this pin determines the duty cycle for the PWM. Optionally, a resistor from this pin to ground is used to determine the voltage threshold used for short circuit protection. (See Application Section) COMP O Low threshold R 2.4 k Ω +/-10% Mid threshold R not installed High threshold R k Ω +/-10% Active low enable input allows ON/OFF operation of the controller. If power is applied to the TPS40040/1 while the EN pin is allowed to float high, the TPS40040/1 remains disabled EN I (both external switches are held OFF). Only when the EN pin is pulled to 1.2 V below VDD is the TPS40040/1 allowed to start. An internal 100-k Ω resistor is connected between VDD and EN to provide pull up. Connect this pin to GND to bypass the enable function. Inverting input of the error amplifier. In closed loop operation, the voltage at this pin is at the internal reference level of 600 mV. A series resistor divider from the converter output to FB I ground, with the center connection tied to this pin, determines the value of the regulated output voltage. This pin is also a connection node for loop feedback components. This is the gate drive output for the high side N-channel MOSFET switch for PWM. It is HDRV O referenced to SW and is bootstrapped for enhancement of the high-side switch. LDRV O Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET. Power input to the device. This pin should be locally bypassed to GND with a low ESR VDD I ceramic capacitor of µ F or greater. Connection to the switched node of the converter and the power return for the upper gate driver. There should be a high current return path from the source of the upper MOSFET to SW O this pin. It is also used by the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction. Ground connection to the device. This is also the thermal pad used to conduct heat from the device. This connection serves a twofold purpose. The first is to provide an electrical ground GND Thermal Pad connection for the device. The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be tied externally to a ground plane. See Application Section for PC board layout information. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Block Diagram OSCILLATOR

4 VDD

Pre−biasThermal Shutdown Vdd−1.2v EN PWM COMP 0.6V SDN100K PWM 0.6 V TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Figure 18. Functional Block Diagram Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com APPLICATION INFORMATION Functional (300 kHz) and TPS40041 (600 kHz) are fixed-frequency voltage-mode synchronous buck controllers. In operation, the synchronous rectifier (SR) is allowed to conduct current in both directions, allowing a converter to operate in continuous mode, even under no load conditions, simplifying feedback loop compensation requirements. During startup, internal circuitry modulates the switching of the synchronous rectifier to prevent discharging of the output if a pre-biased condition exists. The 600-mV bandgap reference voltage cell is internally connected to the non-inverting input of the error amplifier. The voltage reference is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The error amplifier has a bandwidth of greater than MHz, and open loop gain of at least dB. The output voltage swing is limited to just above and below the oscillator ramp levels to improve transient response. Voltage mode buck type converters are typically compensated using Type III networks. Please refer to the Design Example for detailed methodology in designing feedback loops for voltage mode converters. The oscillator frequency is internally fixed. The TPS40040/1 operating frequencies are 300 kHz/600 kHz, respectively. When the input voltage is below the UVLO threshold, the TPS40040/1 turns off the internal oscillator and holds all gate drive outputs in the low (OFF) state. When the input rises above the UVLO threshold, and the EN pin is below the turn ON threshold, the start-up sequence is allowed to begin. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Enable and Start-Up Sequence Configure ILIM Threshold Soft Start 4 ms1.5 ms VOUT ENB COMP Soft Start TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The EN pin of the TPS40040/1s internally pulled to VDD. When power is applied to VDD, the EN pin is allowed to float high, and the TPS40040/1 remains OFF. Only when the EN pin is externally pulled below the threshold voltage of VDD 1.2 V is the TPS40040/1 allowed to start. When enabled, the TPS40040/1 enters a calibration cycle where the short circuit current threshold is determined. The TPS40040/1 monitors the current out of the COMP pin and selects a threshold based on the sensed value of the current. See Selecting the Short Circuit Current Limit Threshold section for for details. When this calibration time is completed, the soft-start cycle is allowed to begin. See Figure below. Figure 19. Startup DESIGN If the enable function is not used, the EN pin should be connected to ground HINT: (GND). DESIGN When designing the feedback loop compensation, ensure the capacitors used HINT: are not so large that they distort the COMP pin calibration waveform. At the end of a calibration cycle, the TPS40040/1 slowly increases the voltage to the non-inverting input of the error amplifier. In this way, the output voltage slowly ramps up until the voltage on the non-inverting input to the error amplifier reaches the internal reference voltage. At that time, the voltage at the non-inverting input to the error amplifier remains at the reference voltage. During the soft-start interval, pulse-by-pulse current limiting is active. If seven consecutive current limit pulses are detected, overcurrent is declared and a timeout period equivalent to seven calibration/soft-start cycles goes into effect. See Output Short Circuit Protection section for details. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Pre-Bias Startup t − Time − 2 µs/div VHDRV VLDRV t − Time − 500 µs/div VIN = 5 V VOUT = 1.2 V (200 mV/div) PREBIAS = 0 V PREBIAS = 0.5 V PREBIAS = 1 V TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The TPS40040/1 supports pre-biased output voltage applications. In cases where the output voltage is held up by external means while the TPS40040/1 is off, full synchronous rectification is disabled during the initial phase of soft starting the output voltage. When the first PWM pulses are detected during soft start, the controller slowly initiates synshronous rectification by starting the synchronous rectifier with a narrow on time. It then increments that on time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage startup and ramp to regulation is smooth and controlled. NOTE: If the output is pre-biased, PWM pulses start when the internal soft-start voltage rises above the error amplifier input (FB pin). Figure below depicts the waveform of the HDRV and LDRV output signals at the beginning PWM pulses. When HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a short pulse. With every clock cycle, the leading edge of LDRV is modulated, increasing the on time of the synchronous rectifier. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve full synchronous rectification. During normal operation of the converter, the TPS40040/1 operates in full two quadrant source/sink mode. Figure shows the startup waveform of a 1.2-V output converter under three different pre-biased output conditions. The lowest trace is when there is no pre-bias on the output. The center and top most traces indicate converter startup with 0.5-V and 1.0-V pre-bias conditions. Figure 20. MOSFET Drivers at Beginning of Soft Start Figure 21. Startup Waveforms The recommended output voltage pre-bias range is less than or equal to 90% of the final regulation voltage. A pre-biased output voltage of 90% to 100% of final regulation could lead to the sinking of current from the pre-bias source. If the pre-biased voltage is greater than the designed converter output regulation voltage, then upon the completion of the soft-start interval, the TPS40040/1 draws current from the output to bring the output voltage into regulation. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Output Short Circuit Protection Selecting the Short Circuit Current Limit Threshold Synchronous Rectification and Gate Drive TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 To minimize circuit losses, the TPS40040/1 uses the R DS(on) of the upper MOSFET switch as the current sensing element. The current limit comparator, initially blanked during the first portion of each switching cycle, senses the voltage across the high-side MOSFET when it is fully ON. This voltage is compared to an internally selected short circuit current (SCC) limit threshold voltage. If the comparator senses a voltage drop across the high-side MOSFET greater than the SCC limit threshold, it outputs an OC pulse. This terminates the current PWM pulse preventing further current ramp-up, and sets the fault counter to count up one count on the next clock cycle. Similarly, if no OC pulse is detected, the fault counter decrements by one count. If seven OC pulses are summed, a fault condition is declared and the upper switch of the PWM output of the chip is immediately disabled (turned OFF) and remains that way until the fault time-out period has elapsed. Both HDRV and LDRV drivers are kept OFF during the fault time-out. The fault time-out period is determined by cycling through seven internal soft-start time periods. At the end of the fault time-out period, startup is attempted again. The main purpose is for hard fault protection of the power switches. The internal SCC voltage has a positive temperature coefficient designed to improve the short circuit threshold tolerance variation with temperature. However, given the tolerance of the voltage thresholds and the R DS(on) range for a MOSFET, it is possible to apply a load that thermally damages the external MOSFETs. The TPS40040/1 uses one of three user selectable voltage thresholds. During the calibration interval at power on or enable Figure the TPS40040/1 monitors the current out of the COMP pin and selects a threshold based on the sensed value. If the current is zero; that is, no resistor is connected between COMP and GND, then the threshold voltage level is 180 mV. If a 2.4-k Ω resistor is connected between COMP and GND, then the threshold voltage level is 105 mV. If a 12-k Ω resistor is connected between COMP and GND, then the threshold voltage is 310 mV. Once calibration is complete, the selected SCP threshold level is latched into place and remains constant. In addition, the sensing circuits on COMP pin during calibration are disconnected from the COMP pin, and soft start is allowed to begin. In a buck converter, when the upper switch MOSFET turns off, current is flowing in the inductor to the load. This current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a diode, or it can be a controlled active device. The TPS40040/1 provides a signal to drive an N-channel MOSFET as a synchronous rectifier (SR). This control signal is carefully coordinated with the drive signal for the main switch so that there is minimum dead time from the time that the SR turns OFF and the upper switch MOSFET turns ON, and minimum delay from when the upper switch MOSFET turns OFF and the SR turns ON. NOTE: The longer the time spent in diode conduction during the rectifier conduction period, the lower the converter efficiency. The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate to source voltage of approximately At VDD the drivers are capable of driving MOSFETs appropriate for a 15-A converter. The LDRV driver switches between VDD and ground, while HDRV driver is referenced to SW and switches between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit that minimizes body diode conduction in the synchronous rectifier. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Gate Drive Resistors Total Gate Charge Synchronous Rectifier dV/dt Turn-On TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The TPS40040/41 s adaptive gate delay circuitry monitors the HDRV-to-SW and LDRV-to-GND voltages to determine the state of the external MOSFET switches. Any voltage drop across an external series gate drive resistor is sensed as reduced gate voltage during turn-off and may interfere with the MOSFET timing. DESIGN A resistor should never be placed in series with the synchronous rectifiers gate HINT: and the gate trace should be kept as short as practical in the layout. The internal voltage sensing of the external MOSFET gate voltages used by the TPS40040/1 to control the dead-times between turn-off and turn-on can be sensitive to large MOSFET gate charges, especially when different gate charges are used for the high-side and low-side MOSFETs. Increased gate charge increases MOSFET switching times and decreases the dead-time between the MOSFETs switching. MOSFETs with no more than nC of total gate charge should be selected. DESIGN The upper switch MOSFET s gate charge should be no less than 60% of the HINT: synchronous rectifier s gate charge to minimize the turn-on/turn-off delay mismatch between the high-side and low-side MOSFET. As the upper switch MOSFET turns on, the switch node voltage rises from close to ground to VIN in a very short period of time (typically ns to ns) resulting in very high voltage spikes on the switch node. The construction of a MOSFET creates parasitic capacitances between its terminals, particularly the gate-to-drain and gate-to-source, creating a capacitive divider between the drain and source of the MOSFET with the gate at its mid-point. If the gate-to-drain charge GD is larger than the gate-to-source charge GS the capacitive divider places proportionally more charge on the gate of the MOSFET as the switch node voltage rises than is shunted to GND. In extreme cases, this can cause the synchronous rectifier gate voltage to rise above the turn on threshold voltage of the MOSFET and causes cross-conduction. This is called dV/dt turn-on. It increases power dissipation in both the high-side and the low-side MOSFET, reducing efficiency. Select a synchronous rectifier MOSFET with a Q GD to Q GS ratio of less than DESIGN one and provide a wide, low resistance, low inductance loop in the synchronous HINT: rectifier gate drive circuit. (See Layout Consideration) A resistor in series with the boost capacitor slows the turn on of the high-side DESIGN MOSFET, and reduces the dV/dt of the switch node. See Boost Capacitor HINT: Series Resistor section. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Bootstrap for N-Channel MOSFET Drive Bootstrap Capacitor Series Resistor External Schottky Diode for Low Input Voltage VDD Bypass and Filtering TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The PWM duty cycle is limited to a maximum of 95%, allowing the bootstrap capacitor to charge during every cycle. During each PWM OFF period, the voltage on VDD charges the bootstrap capacitor. When the PWM switch is next commanded to turn ON, the voltage used to drive the MOSFET is derived from the voltage on this capacitor. Since this is a charge transfer circuit, the value of the bootstrap capacitor must be sized such that the energy stored in the capacitor on a per cycle basis is greater then the gate charge requirement of the MOSFET being used. See the Design Example section for details. Since resistors should not be placed in series with the high-side gate, it may be necessary to place a small Ω to Ω resistor in series with the bootstrap capacitor to control the turn-on of the main switching MOSFET and reduce the dV/dt rate of rise of the switch node voltage. A resistor placed between the BOOT pin and the bootstrap capacitor increases the series resistance during the turn-on of the high-side MOSFET, and has no effect during the high-side MOSFET s turn-off period. This prevents the TPS40040/1 from sensing the upper switch MOSFET s turn-off too early and reducing the upper switch MOSFET turn-off to the SR MOSFET turn-on delay timing too far. DESIGN To reduce EMI, place a small Ω to Ω resistor in series with the boost HINT: capacitor to control the turn-on of the main switching FET. The TPS40040/1 uses an internal P-channel MOSFET switch between VDD and BOOT to charge the bootstrap capacitor during synchronous rectifier conduction time. At low input voltages, a MOSFET can not be turned on hard enough to rapidly replenish the charge required to turn on an (high gate charge) external high-side MOSFET. For this situation, an external Schottky diode between the VDD and BOOT pins may be added. While the diode carries very small average current G x F SW it may be required to carry several hundred mA of peak surge current. The diode should be rated for at least 500 mA of surge current. For higher input voltage applications, if a resistor is used in series with the boost capacitor, connect the diode to the junction of the resistor and capacitor to remove the added resistance from the capacitor s charge path. For low input voltages, and a high gate charge upper switch MOSFET, a small DESIGN Schottky diode should be placed from VDD to BOOT. Do not use a resistor in HINT: series with the boost capacitor. To prevent switching noise from being injected into the TPS40040/1 control circuitry, a ceramic capacitor µ F minimum) must be placed as close to the VDD pin and GND pad as possible. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com VDD Filter Resistor Thermal Shutdown Package Power Dissipation P D(driver)/C0043Q G /C0032V DRIVE /C0032FSW W /C0324driver (1) P T /C0043/C04662 /C0032P D V DRIVE /C0041IQ /C0467/C0032V DD W (2) P T /C0043/C04662 /C0032G Q /C0032FSW /C0041IQ /C0467/C0032V DD W (3) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 To further limit the noise on VDD, a small Ω to Ω resistor may be placed between the input voltage and the VDD pin to create a small filter to VDD. The resistor should connect near the drain of the upper switch MOSFET to prevent trace IR drops from increasing the sensed voltage drop. The resistor itself should be placed close to Pin The current through the resistor includes the device's no-load switching current of mA plus gate switching current. The voltage drop induced across this resistor reduces the VDD-to-SW voltage sensed by the over current protection circuitry within the device. This results with the apparent voltage drop across the upper switch MOSFET being increased, thereby decreasing the current at which protection will occur. To minimize this effect, the resistor value should be selected to yield less than a 25-mV drop. If the junction temperature of the device reaches the thermal shutdown level, the PWM and the oscillator are turned off and HDRV and LDRV are driven off. When the junction cools to the required level, the PWM soft starts as during a normal power-up cycle. The power dissipation in a controller is largely dependent on the MOSFET driver currents and the input voltage. The driver current is proportional to the total gate charge, Q G of the external MOSFETs, and the operating frequency of the converter. Driver power, neglecting external gate resistance, is calculated from: And the total power dissipation, assuming the same MOSFET is selected for both the high side and synchronous rectifier is: or where I Q is the quiescent operating current (neglecting drivers). The max power capability of the PowerPad package is dependent on the layout as well as air flow. The thermal impedance from junction-to-air assuming 2-oz copper trace and thermal pad with solder and no air flow is detailed in Reference [5]. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com PCB Layout Guidelines HDRV SW BOOT LDRV FB COMP VDD TPS40041 GND (Power Pad) Locate Parts Over Signal Ground Island Signal Ground Power Ground Locate Parts Over Power Ground Output Current Loop Input Current Loop SR Gate Drive Main Gate Drive VDD Bypass VDD Filter (Optional) Current Limit Set Resistor VIN Enable Enable Bypass (Optional) BOOST Resistor (Optional) EN VOUT Power Component Routing TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 A synchronous BUCK power stage has two primary current loops, the input current loop that carries high ac discontinuous current and an output current loop that carries high dc continuous current. The output current loop carries low ac inductor ripple current. Figure 22. Synchronous BUCK Power Stage As shown in Figure the input current loop contains the input capacitors, the switching MOSFET, the inductor, the output capacitors, and the ground path back to the input capacitors. To keep this loop as small as possible, it is good practice to place some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop includes the filter inductor, the output capacitors, and the ground return between the output capacitors and the source of the synchronous rectifier MOSFET. As with the input current loop, the ground return between the output capacitor ground and the source of the SR source should be routed under the inductor and MOSFETs to minimize the power loop area. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Device to Power Stage Interface VDD Filtering Device Connections PowerPAD Layout TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The TPS40040/1 uses a very fast break-before-make anti-cross conduction circuit to minimize power loss. Adding external impedance in series with the gates of the switching MOSFETs adversely affects the converter s operation and must be avoided. The loop impedance (HDRV-to-gate plus source-to-SW and LDRV-to-SR gate plus SR source-to-GND) should be kept to less than nH to avoid possible cross-conduction. The HDRV and LDRV connections should widen to mils as soon as possible out from the device pin. The return for the main switching MOSFET gate drive is the SW pin of the TPS40040/1. The SW pin should be routed to the source of the main switching FET with at least a 20-mils wide trace as close to the HDRV trace as possible to minimize loop impedance. The return for the SR MOSFET gate drive is the TPS40040/1 GND pad. The GND pad should be connected directly to the source of the SR with at least a 20-mil wide trace directly under the LDRV trace. Use a minimum of parallel vias to connect the GND pad to the source of the SR if multiple layers are used. A small, less than Ω resistor may be added in series with the BOOT pin to slow the turn-on of the upper switch MOSFET, thereby reducing the rising edge slew-rate of the switch node. In turn, this reduces EMI, increases upper MOSFET OFF to SR ON dead time, and minimizes induced dV/dt turn-on of the SR when the upper switch MOSFET turns on. It is recommended customers make provisions on their boards for this resistor and not use resistors in series with MOSFET gate leads. A ceramic capacitor, µ F minimum, must be placed as close to the VDD pin and GND pad as possible with a 15-mil wide (or greater) trace. If used, a small series connected resistor Ω to Ω may be placed less than 100 mils from the TPS40040/1 between the supply input voltage and the VDD pin to further reduce switching noise on the VDD pin. NOTE: The voltage drop across this resistor affects the level at which the over-current circuit operates by filtering the sensed VDD voltage. If a current limit resistor is used (COMP to GND), it must be placed within 100 mils of the COMP pin to limit noise injection into the PWM comparator. Compensation components (feedback divider, and associated error amplifier components) should be placed over a signal ground island connected to the power ground at the GND pad through a 10-mil wide trace. If multiple layers are used, connect to GND through a single via on an internal layer opposite the connection to the source of the synchronous rectifier. The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend on the size of the PowerPAD package. See PCB Layout Guidelines for further information. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package [2] for more information on the PowerPAD package. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com DESIGN EXAMPLES Example A 5-V to 1.8-V DC-to-DC Converter Using a TPS40041 EN EN TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The following example illustrates the design process and component selection for a 5-V to 1.8-V point-of-load synchronous buck converter. The design goal parameters are given in the table below. A list of symbol definitions is found at the end of this section. Design Goal Parameters SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT V IN Input voltage 4.5 5.5 V V INripple Input ripple I OUT A mV V OUT Output voltage I OUT V IN V 1.764 1.8 1.836 V Line regulation V IN 4.5 A to 5.5 V 0.5% Load regulation I OUT A to A 0.5% V RIPPLE Output ripple I OUT A mV V TRANS Transient deviation I OUT A to I OUT A to A I OUT Output current V IN 4.5 V to 5.5 V A F SW Switching frequency 600 kHz Size In For this example, the schematic shown in Figure is used. The TPS40041, with F SW 600 kHz, is selected to reduce inductor and capacitor sizes. Figure 23. TPS40041 Sample Schematic Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Inductor Selection L /C0043 V IN(max)/C0042V OUT 0.3/C0032IOUT /C0032 V OUT V IN(max) /C00321 FSW (4) IL(rms)/C0043/C0466IL(avg)/C0467 /C00411 12 /C0466IRIPPLE /C0467 2/C0504 /C0043/C0466IOUT /C0467 /C00411 12 /C0466IRIPPLE /C0467 /C0504 (5) Output Capacitor Selection (C8 C9) C OUT(min) /C0043 ITRAN(max) 2 /C0032L /C0466V IN(min)/C0042V OUT /C0467/C0032V TRAN when VIN(min)/C01162 /C0032V OUT (6) C OUT(min) /C0043 ITRAN(max) 2 /C0032L /C0466V OUT /C0467/C0032V TRAN when VIN(min)/C01172 /C0032V OUT (7) ESR MAX /C0043 V RIPPLE(total)/C0042V RIPPLE(cap) IRIPPLE /C0043 V RIPPLE(total)/C0042/C0466IRIPPLE C OUT /C0032FSW /C0467 IRIPPLE (8) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The inductor is typically sized for 30% peak-to-peak ripple current RIPPLE Given this target ripple current, the required inductor size is calculated by: Solving with V IN(max) 5.5 an inductor value of 1.12 µ H is obtained. A standard value of 1.0 µ H is selected, resulting in 2-A peak-peak ripple. The RMS current through the inductor is approximated by the equation: Using Equation the maximum RMS current in the inductor is about 6.03 The selection of the output capacitor is typically driven by the output load transient response requirement. Equation and Equation estimate the output capacitance required for a given output voltage transient deviation. For this example, Equation is used in calculating the minimum output capacitance. Based on a 4-A load transient with a maximum 50-mV deviation, a minimum of 178- µ F output of capacitance is required. The output ripple is divided into two components. The first is the ripple voltage generated by inductor ripple current flowing through the output capacitor's capacitance, and the second is the voltage generated by the ripple current flowing in the output capacitor's ESR. The maximum allowable ESR is then determined by the maximum ripple voltage and is approximated by: Based on 178 µ F of capacitance, 2-A ripple current, 600-kHz switching frequency and a design goal of 36-mV ripple voltage, we calculate a capacitive ripple component of 18.7 mV and a maximum ESR of 8.6 m Ω Two 1206, 100- µ 6.3-V, X5R ceramic capacitors are selected to provide significantly less than 8.6 m Ω of ESR. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Peak Current Rating of Inductor ICHARGE /C0043 V OUT /C0032C OUT TSS (9) LL(peak)/C0043IOUT(max) /C00411 /C0466IRIPPLE /C0467/C0041ICHARGE (10) Input Capacitor Selection (C1 C2) C IN(min)/C0043 ILOAD /C0032V OUT V RIPPLE(cap)/C0032V IN /C0032FSW (11) ESR MAX /C0043 V RIPPLE(ESR) ILOAD /C00411 /C0466IRIPPLE /C0467 (12) IRMS(cin)/C0043IIN(rms)/C0042IIN(avg)/C0043/C0426/C0466IOUT /C0467 /C00411 12 /C0466IRIPPLE /C0467 /C0427/C0032 V OUT V IN /C0504 /C0042 V OUT /C0032IOUT V IN (13) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 With output capacitance known, it is now possible to calculate the charging current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by: Using the TPS40041 s fixed 4.5-ms soft-start time, C OUT 200 µ F and V OUT 1.8 I CHARGE is found to be mA. The peak current rating of the inductor is now found by: The inductor requirements are summarized in the table below. Inductor Requirements PARAMETER SYMBOL VALUE UNITS Inductance L 1.0 µ H RMS current (thermal rating) I L(rms) 6.03 A Peak current (saturation rating) I L(peak) 7.08 A PG0083.102, 1.0 µ H is selected for its small size, low DCR and high current handling capability. The input voltage ripple is divided between capacitance and ESR. For this design, V RIPPLE (CAP) mV and V RIPPLE (ESR) mV. The minimum capacitance and maximum ESR are estimated by: For this design, C IN µ F and ESR 3.5 m Ω The RMS current in the input capacitors is estimated by: With V IN V IN(max) the input capacitors must support a ripple current of 1.56 A RMS Two 1206, 100- µ X5R ceramic capacitors with about 5-m Ω ESR and a 2-A RMS current rating are selected. It is important to check the dc bias voltage derating curves to ensure the capacitors provide sufficient capacitance at the working voltage. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com MOSFET Switch Selection (Q1 Q2) P G1SW /C00431 /C0032V IN /C0032IOUT /C0032/C0466TRISE /C0041TFALL/C0467/C0032FSW /C0043V IN /C0032IOUT /C0032 Q GS2_Q1 /C0041Q GD_Q1 V DD /C0042V TH R DRIVE /C0032FSW (14) Q GS2_Q1 /C0041Q GD_Q1 /C0116 P G1SW V IN /C0032IOUT /C0032V DD /C0042V t R DRIVE /C00321 FSW (15) P CON_Q1 /C0043D /C0032/C0426/C0466IOUT /C0467 /C00411 12 /C0466IRIPPLE /C0467 /C0427/C0032R DS(on) /C0043 V OUT V IN /C0032IL(rms) 2 /C0032R DS(on_Q1) (16) R DS(on_Q1) /C0043 P CON_Q1 IL(rms) 2 /C0032V OUT V IN (17) R DS(on_Q2) /C0043 P CON_Q2 IL(rms) 2 /C0032/C04661 /C0042V OUT V IN /C0467 (18) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The switching losses for the upper switch MOSFET are estimated by: For this design, switching losses are higher at low input voltage due to the lower gate drive current. Designing for W of total losses in both MOSFETS and 20% of the total MOSFET losses in switching losses, we can estimate our maximum gate-to-drain charge for the design at: For a low-gate threshold MOSFET, and the TPS40041 s Ω and Ω drive resistances, we estimate a maximum Q GS2 GD of 10.8 nC. The conduction losses in the upper switch MOSFET are estimated by the RMS current through the MOSFET times its R DS(on) Estimating about 30% of total MOSFET losses to be high-side conduction losses, the maximum R DS(on) of the high-side MOSFET can be estimated by: For this design, with I L_RMS A RMS and 4.5 V to 1.8 R DS(on_Q1) is 19.5 m Ω for the upper switch MOSFET. Estimating 50% of total MOSFET losses are in the SR as conduction losses, repeat equation 14. Then calculate the maximum R DS(on) of the SR by the equation: For this design I L_RMS A at 5.5 V to 1.8 V R DS(on_Q2) 19.6 m Ω The table below summarizes the MOSFET requirements. MOSFET Requirements PARAMETER SYMBOL VALUE UNITS High-side FET R DS(on) R DS(on_Q1) 19.5 m Ω High-side FET turn-on charge Q GS2_Q1 GD_Q1 10.8 nC Low-side FET R DS(on) R DS(on_Q2) 19.6 m Ω IRF7910 has an R DSON(max) of m Ω at 4.5-V gate drive,Q GD of 6.2 nC, and Q GS2 of nC. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Bootstrap Capacitor (C7) C BOOST /C0043 20 /C0032Q GS_Q1 V IN(min) (19) VDD Bypass Capacitor (C6) VDD Filter Resistor (R7) R VDD /C0116 V RVDD(max) IDD /C0043 25 mV 2 mA /C0041/C0466Q G_Q1 /C0041Q G_Q2 /C0467FSW (20) Short Circuit Protection (R2) V CS /C0043IL(peak)/C0032R DS(on_Q1) (21) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 To ensure proper charging of the upper switch MOSFET gate, limit the ripple voltage on the bootstrap capacitor to of the minimum gate drive voltage of 3.0 Based on the IRF7910 MOSFET with a maximum total gate charge of nC, calculate a minimum of 116 nF of capacitance. The next higher standard value of 220 nF is selected. Select a 1.0- µ F ceramic bypass capacitor for VDD. An optional resistor in series with VDD helps filter switching noise from the device. Driving the two IRF7910 MOSFETs, with a typical total Q G of nC each, we calculate a maximum I DD current of mA. The result of equation 19, leads to selecting a Ω resistor, and limits the voltage drop across this resistor to less than mV. The TPS40040/1 use the forward drop across the upper switch MOSFET during the ON time to measure the inductor current. The voltage drop across the high-side MOSFET is given by: When V IN 4.5 V to 5.5 I L_PEAK 7.2A. Using the IRF7910 MOSFET, we calculate the peak voltage drop to be 108 mV. The TPS40041 s internal 3100-ppm temperature coefficient helps compensate for the MOSFET s R DS(on) temperature coefficient. For this design, select the short circuit protection voltage threshold of 180 mV by selecting OPEN. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Feedback Loop Design Modeling the Power Stage A MOD /C0043V IN V RAMP(p /C0042p) (22) FRES /C00431 2 /C0032/C0112/C0032L /C0032C/C0504 (23) FESR /C00431 2 /C0032/C0112/C0032C OUT /C0032R ESR (24) AMOD 0dB FRES FESR −40dB/dec −20dB/dec Frequency (Log Scale) Feedback Divider (R4, R8) R5 in paralell with R4/C0043V FB /C0032R8 V OUT /C0042V FB (25) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 To design feedback circuit, a small signal average modeling technique is employed. Further information on this technique may be found in the references. The peak-to-peak ramp voltage given in the Electrical Specification table allows the modulator gain to be calculated as: For this design, a modulator gain of 7.3 (17.3 dB) is calculated. The LC filter applies a double pole at the resonance frequency: For this design, the resonance frequency is about 11.3 kHz. Below this frequency, the power stage has the dc gain of 17.3 dB and above this frequency the power stage gain drops off at -40 dB per decade. The ESR zero is approximated by: For C OUT x 100 µ F and R ESR 2.5 m Ω F ESR 318 kHz. This is greater than 1/5th the switching frequency and outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per decade above F ESR The straight line approximation the power stage gain is approximated in Figure Figure 24. Power Stage Frequency Response Straight Line Approximation Select be between k Ω and 100 k Ω For this design, select k Ω Next, is selected to produce the desired output voltage when V FB 0.600 V using the following formula. VFB 0.600 V and k Ω for VOUT 1.8 k Ω If the calculated value is not a standard resistor, select a slightly higher resistor value and add in parallel to reduce the parallel combination of and to produce desired output voltage. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Error Amplifier Pole-Zero Selection A PS(fcc)/C0043A MOD /C004240 /C0032LOG /C0466 FCO FRES /C0467 (26) FP2(max) /C0043 FSW A MID(band) (27) TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Place two zeros at 80% and 125% of the resonance frequency to keep the actual resonance frequency between the two zeros over the L and C tolerance. For F RES 11.3 kHz, F 9.0 kHz and F kHz. Selecting the cross-over frequency CO of the control loop between times the LC filter resonance and 1/5th the switching frequency. For most a good balance between ease of design and fast transient response. If F ESR F CO F F CO and F F CO If F ESR F CO F F CO and F F CO For this design with F SW 600 kHz, F RES 11.3 kHz and F ESR 318 kHz. F CO kHz and since F ESR F CO F F CO and F F CO Since F CO F ESR the power stage gain at the desired cross-over can be approximated by: A PS CO -11.7 dB, so the error amplifier gain between the two poles should be (11.7/20) 3.84. If the error amplifier gain is greater than dB at F SW the converter can achieve a stable bi-modal operation with duty cycles alternating between two stable values, and the output regulated with a output ripple component at F SW To prevent this effect, check F by the equation: Since F F P2(max) it is possible for this control loop to obtain bi-modal operation. To prevent this bi-modal operation, reduce F CO and re-calculate A PC CO F and F P2(max) Now, F CO kHz, A MID-BAND 2.67, F kHz and F 200 kHz. The table below summarizes the error amplifier compensation network design criteria. Error Amplifier Compensation Network PARAMETER SYMBOL VALUE UNITS First zero frequency F kHz Second zero frequency F First pole frequency F Second pole frequency F 200 Mid-band gain A MID-BAND 2.67 V/V Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Feedback Components (R3, R6, C3, C4, C5) C5 /C00431 2 /C0032/C0112/C0032R8 /C0032FZ2 (28) R6 /C00431 2 /C0032/C0112/C0032C5 /C0032FP1 (29) R3 /C0043 A MID(band)/C0032(R6 /C0032R8 ) R6 /C0041R8 (30) C4 /C00431 2 /C0032/C0112/C0032R3 /C0032FZ1 (31) C3 /C00431 2 /C0032/C0112/C0032R3 /C0032FP2 (32) 0dB FZ1 Frequency (Log Scale) FZ2 FP1 FP2 A mid−Band FSW TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Approximate with the formula: 560 pF (closest standard capacitor value to calculated 568 pF) and approximate with the formula: 4.75 k Ω (closest standard resistor value to calculated 4.74 k Ω Calculate by the formula: With A MID_BAND 3.84, 4.75 k Ω and k Ω 14.7 k Ω (closest standard resistor value to calculated 14.7 k Ω Calculate and by the equations: For 14.7 k Ω pF (closest standard value to pF) 1200 pF (closest standard value to 1.2 nF) Error Amplifier straight line approximation transfer function looks like Figure Figure 25. Error Amplifier Frequency Response Straight Line Approximation Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com 0 4 7 100% 90% 80% 60% 1 3 5 2 50% 70% IOUT − Load Current − A η − Efficiency − % 4.5 5 5.5 0 4 7 1.814 1.812 1.810 1.808 1.800 1 3 6 1.804 1.802 1.806 4.5 5 5.5 1.818 1.816 IOUT − Load Current − A VOUT − Output Voltage − V TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Figure 26. Typical Efficency for 5-V to 1.8-V at 6-A Converter Using TPS40041 Figure 27. Typical Line/Load Regulation for 5-V to 1.8-V at 6-A Converter Using TPS40041 Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 List of Materials REF QTY Capacitor, ceramic, 6.3 X5R, 20%, 100 µ 1210 TDK C325X5R0J107M Capacitor, ceramic, 6.3 X5R, 20%, 100 µ 1210 TDK C3225X5R0J107M Capacitor, ceramic, X7R, 20%, 270pF, 0402 TDK C1005C01H271M Capacitor, ceramic, X7R, 20%, 1500 pF, 0402 TDK C1005X7R1H152M Capacitor, ceramic, X7R, 20%, 560 pF, 0402 TDK C1005X7R1H561M Capacitor, ceramic, 6.3 X5R, 20%, 1.0 µ 0402 TDK C1005X7R0J105M Capacitor, ceramic, 6.3 X5R, 20%, 0.22 µ 0402 TDK C1005X7R0J224M Capacitor, ceramic, 6.3 X5R, 20%, 100 µ 1210 TDK C3225X5R0J107M Capacitor, ceramic, 6.3 X5R, 20%, 100 µ 1210 TDK C3225X5R0J107M Inductor, SMT, 1.0 µ 6.6 m Ω ED1514, 0.268 x 0.268 Pulse PG0083.102 MOSFET, dual N-channel, 6.6 m Ω 1.0 µ SO8 IR IRF7311 Resistor, chip, IRF7910, 0402 Std Std Resistor, chip, 1%, OPEN, 0402 Std Std Resistor, chip, 1%, 11.8 k Ω 0402 Std Std Resistor, chip, 1%, OPEN, 0402 Std Std Resistor, chip, k 1%, 10.0 k Ω 0402 Std Std Resistor, chip, 1%, 5.62 k Ω 0402 Std Std Resistor, chip, k 1%, k Ω 0402 Std Std Device, Low Voltage DC to DC Synchronous Buck Controller, TPS40041DRB TI TPS40041DRB, SON-8P Active High Enable Circuit Resistor, chip, 100 k Ω 1%, 100 k Ω 0402 Std Std Mosfet, N-channel, VDS RDS Ω ID 115 mA, 2N7002W-7 Diodes Inc 2N7002W, SOT-323 (SC-70) Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 Definition of Symbols SYMBOL V IN(max) Maximum operating input voltage V IN(min) Minimum operating input voltage V INRIPPLE Peak-to-peak ac ripple voltage on V IN V OUT Target output voltage V OUTRIPPLE Peak-to-peak ac ripple voltage on V OUT I OUT(max) Maximum operating load current I RIPPLE Peak-to-peak ripple current through the output filter inductor I L_PEAK Peak ripple current through the output filter inductor I L_RMS Root mean squared current through the output filter inductor I RMS_CIN Root mean squared current in input capacitor F SW Switching frequency F CO Desired control loop cross-over frequency A MOD Low frequency gain of the pulse width modulator V CONTROL PWM control voltage (error amplifier output voltage V COMP F RES L-C filter resonant frequency F ESR Output capacitors ESR zero frequency F First pole frequency in error amplifier compensation F Second pole frequency in error amplifier compensation F First zero frequency in error amplifier compensation F Second pole frequency in error amplifier compensation Q G1_Q1 Total gate charge of upper switch MOSFET Q G2_Q2 Total gate charge of synchronous rectifier MOSFET R DS(on_Q1) ON drain-to-source resistance of upper switch MOSFET R DS(on_Q2) ON drain-to-source resistance of synchronous rectifier MOSEFT P CON_Q1 Conduction losses in upper switch MOSFET P SW_Q1 Switching losses in upper switch MOSFET P CON_Q2 Conduction losses in synchronous rectifier MOSFET Q GD_Q1 Gate-to-drain charge of upper switch MOSFET Post threshold gate-to-source charge of the upper switch MOSFET. (Estimate from Q G vs. V GS if not provided in Q GS2_Q1 MOSFET data sheet) V FB Internal reference voltage as measured on FB pin. V RAMP_slope Slope of internal PWM ramp A PS(Fco) V COMP to V OUT gain at desired loop cross-over frequency. (dB) A MID-BAND V OUT to V COMP gain at desired loop cross-over frequency (V/V) Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Example A 2.5-V to 1.2-V DC-to-DC Converter Using a TPS40041 0.0 2.5 3.5 1.210 1.208 1.206 1.198 0.5 2.0 3.0 1.202 1.0 1.200 1.204 2.25 2.5 2.75 1.5 IOUT − Load Current − A VOUT − Output Voltage − V 0.0 2.0 3.5 100% 90% 80% 60% 0.5 1.5 3.01.0 50% 70% 2.5 IOUT − Load Current − A η − Efficiency − % 2.25 2.5 2.75 TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 This example illustrates a 2.5-V to 1.2-V at 3-A synchronous buck application using the TPS40041. A diode has been added to increase the bootstrap capacitor charging current at low input voltage. The highest current limit threshold has been selected due to the increased R DS(on) at low input voltages. Figure 28. Schematic for 2.5-V to 1.2-V at 3-A Converter Using the TPS40041 Figure 29. Typical Efficency for 2.5-V to 1.2-V at 3-A Figure 30. Typical Line/Load Regulation for 2.5-V to 1.2-V Converter Using TPS40041 at 3-A Converter Using TPS40041 Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com Example A 3.3-V to 1.2-V DC-to-DC Converter Using a TPS40040 0 8 12 1.217 1.212 1.207 1.202 1.182 2 6 10 1.192 1.187 1.197 3.3 3 3.6 IOUT − Load Current − A VOUT − Output Voltage − V 0 8 12 100 2 6 10 4 IOUT − Load Current − A η − Efficiency − % 3 3.3 3.6 TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 This example illustrates a 3.3-V to 1.2-V at 10-A synchronous BUCK application using the TPS40040 switching at 300 kHz. Separate SO-8 MOSFETs have been chosen to support the higher currents in this application and a resistor has been added in series with the BOOT pin to slow the rising edge of the switch node and reduce EMI on the input of the converter. Figure 31. Schematic for 3.3-V to 1.2-V at 10-A Converter Using the TPS40040 Figure 32. Typical Efficiency for 3.3-V to 1.2-V at 10-A Figure 33. Typicaly Line and Load Regulation for 3.3-V to Converter Using TPS40040 1.2-V at 10-A Converter Using TPS40040 Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

www.ti.com ADDITIONAL REFERENCES Related Parts References Package Outline Recommended PCB Footprint TPS40040 TPS40041 SLUS700D MARCH 2006 REVISED DECEMBER 2007 The following parts have characteristics similar to the TPS40040/1 and may be of interest. Related Parts DEVICE www.power.ti.com under Technical Documents. Many design tools and links to additional references, including design software, may also be found at www.power.ti.com Under The Hood Of Low Voltage DC/DC Converters SEM1500 Topic 2002 Seminar Series Understanding Buck Power Stages in Switchmode Power Supplies SLVA057, March 1999 Design and Application Guide for High Speed MOSFET Gate Drive Circuits SEM 1400, 2001 Seminar Series Designing Stable Control Loops SEM 1400, 2001 Seminar Series Additional PowerPAD TM information may be found in Attachment, Texas Instruments Literature Number SLUA271, June 2002 The page following outlines the mechanical dimensions of the DRB package. The second page following outlines the recommended PCB layout. Copyright 2006 2007, Texas Instruments Incorporated Product Folder Link(s): TPS40040 TPS40041

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40040DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS40040DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS40040DRBT SON DRB 8 250 210.0 185.0 35.0 TPS40040DRBT SON DRB 8 250 210.0 185.0 35.0 TPS40041DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS40041DRBT SON DRB 8 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2015 Pack Materials-Page 2

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