TPS40021-EP_16 TI1 | Alldatasheet

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www.ti.com SLUSB58 –SEPTEMBER 2012 ENHANCED,LOW-INPUTVOLTAGE-MODESYNCHRONOUSBUCKCONTROLLER Check forSamples: TPS40021-EP 1FEATURES 2• OperatingInputVoltage2.25V to5.5V APPLICATIONS

  • Output Voltageas Low as 0.7V • Networking Equipment
  • 1% Internal0.7-VReference • Telecom Equipment
  • PredictiveGate Drive™ N-Channel MOSFET • Base Stations DriversforHigherEfficiency • Servers
  • ExternallyAdjustableSoft-Startand Short • DSP PowerCircuitCurrentLimit
  • Programmable Fixed-Frequency100-kHz to SUPPORTS DEFENSE, AEROSPACE, 1-MHz Voltage-Mode Control AND MEDICAL APPLICATIONS
  • Source or Sink Current • ControlledBaseline
  • Quick Response Output Transient • One Assembly and TestSite Comparators With Power Good Indication • One FabricationSiteProvideOutput Status
  • AvailableinMilitary(–55°C to125°C)• 16-PinPowerPAD ™ Package Temperature Range (1)
  • Extended Product LifeCycle
  • Extended Product-Change Notification
  • Product Traceability (1) Custom temperaturerangesavailable

DESCRIPTION

The TPS40021 is a dc-to-dccontrollerdesigned fornon-isolatedsynchronous buck regulators,providing enhanced operationand designflexabilitythroughuserprogrammability. The deviceutilizesa proprietaryPredictiveGate Drivetechnologyto minimizethe diode conductionlosses associatedwiththehigh-sideand synchronousrectifierN-channelMOSFET transistions.The integratedcharge pump withboostcircuitprovidesa regulated5-V gate driveforboth the highsideand synchronousrectifier N-channelMOSFETs. The use ofthePredictiveGate Drivetechnologyand chargepump/boostcircuitscombine toprovidea highlyefficient,smallerand lessexpensiveconverter. Designflexibilityisprovidedthroughuserprogrammabilityofsuch functionsas:operatingfrequency,shortcircuit currentdetectionthresholds,soft-startramp time,and externalsynchronizationfrequency.The operating frequencyisprogrammableusinga singleresistorovera frequencyrangeof100 kHz to1 MHz. Higheroperating frequenciesyieldsmallercomponent valuesfora givenconverterpower levelas wellas fasterloopclosure. The shortcircuitcurrentdetectionisprogrammable througha singleresistor,allowingthe shortcircuitcurrent limitdetectionthresholdtobe easilytailoredtoaccommodate differentsize(RDS(on))MOSFETs. The shortcircuit currentfunctionprovidespulse-by-pulsecurrentlimitingduringsoft-startand shortterm transientconditionsas wellas a faultcountertohandlelongerdurationshortcircuitcurrentconditions.Ifa faultisdetectedthecontroller shutsdown fora periodof time determinedby sixconsecutivesoft-startcycles.The controllerautomatically retriestheoutputeveryseventhsoft-startcycle. In additionto determiningthe offtime duringa faultcondition,the soft-startramp providesa closedloop controlledramp oftheconverteroutputduringstartup.Programmabilityallowstheramp ratetobe adjustedfora widevarietyofoutputL-C component values. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PredictiveGate Drive,PowerPAD aretrademarksofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

VDD 2.25 V − 5.5 V 4 FB 1 1 BOOT1 TPS40021

6 SS/SD

SLUSB58 –SEPTEMBER 2012 www.ti.com The outputvoltagetransientcomparatorsprovidea quickresponse , firststrike,approach to outputvoltage transients.The outputvoltageissensed througha resistordividerattheOSNS pin.Ifan overvoltageconditionis detectedtheHDRV gatedriveisshut-offand theLDRV gatedriveisturnedon untiltheoutputisreturnedto regulation.Similarly,ifan outputundervoltageconditionissensed theHDRV gatedrivegoes to95% dutycycle topump theoutputback up quickly.Ineithercase,thePowerGood open drainoutputpullslow toindicatean outputvoltageout of regulationcondition.The PowerGood outputcan be daisy-chainedto the SS/SD pinor enablepinof othercontrollersor convertersforoutputvoltagesequencing.The transientcomparatorscan be disabledby simplytyingtheOSNS pintoVDD. The TPS40021 can be externallysynchronizedthroughtheILIM/SYNC pinup to1.5× thefree-runningfrequency. This allowsmultiplecontollersto be synchronizedto eliminateEMI concernsdue to inputbeat frequencies between controllers.

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www.ti.com SLUSB58 –SEPTEMBER 2012 This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) ORDERABLE TOP-SIDETJ PACKAGE VID NUMBERPART NUMBER MARKING TPS40021MPWPREP Tape and Reel,2000 V62/12601-01XEPlasticHTSSOP PowerPAD–55°C to125°C 40021M(PWP) (2) TPS40021MPWPEP Tube,90 V62/12601-01XE-T (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI websiteatwww.ti.com. (2) WithCu NIPDAU lead/ballfinish ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerangeunlessotherwisenoted MIN MAX UNIT SS/SD, VDD, PVDD, OSNS –0.3 6 BOOT2, BOOT1 VSW + 6 VIN Inputvoltagerange SW –0.3 10.5 V SWT (SW transient< 50 ns) –5 FB, ILIM –0.3 6 VOUT Outputvoltagerange COMP, PWRGD, RT –0.3 6 V IS Sinkcurrent PWRGD 10 mA TJ Maxium juctiontemperature 150 °C Tstg Storagetemperature –65 150 °C Lead temperature1,6mm (1/16inch)fromcase for10 seconds 260 °C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability.Allvoltage valuesarewithrespecttothenetworkgroundterminalunlessotherwisenoted. THERMAL INFORMATION TPS40021-EP THERMAL METRIC (1) PWP UNITS

16 PINS

θJA Junction-to-ambientthermalresistance(2) 38.3 θJCtop Junction-to-case(top)thermalresistance(3) 28 θJB Junction-to-boardthermalresistance(4) 9 °C/W ψJT Junction-to-topcharacterizationparameter(5) 0.4 ψJB Junction-to-boardcharacterizationparameter(6) 8.9 θJCbot Junction-to-case(bottom)thermalresistance(7) 2.9 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specificJEDEC- standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (4) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (5) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (6) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). (7) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. Spacer Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS40021-EP

SLUSB58 –SEPTEMBER 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT Supplyvoltage,VIN 2.25 5.50 V Operatingtemperaturerange,TJ –55 125 °C

ELECTRICAL CHARACTERISTICS

TJ = −55°C to125°C, TJ = TA,VDD = 5.0V (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Inputvoltagerange 2.25 5.50 V VPVDD PVDD pinvoltage VDD = 3.3V 4.9 5.2 V Switchingcurrent 500 kHz,No loadon HDRV, LDRV 3.5 5 IDD Quiescentcurrent FB = 0.8V 2 3 mA Shutdown current SS/SD = 0 V,OutputsOFF 0.38 1 Minimum on-voltage 1.95 2.05 2.15 VUVLO mV Hysteresis 72 130 200 OSCILLATOR 2.25V ≤ VDD ≤ 5.00V,R T = 69.8kΩ 405 500 575 fOSC Accuracy kHz 2.25V ≤ VDD ≤ 5.00V,R T = 34.8kΩ 740 950 1100 VRAMP Ramp voltage VPEAK − VVAL 0.80 0.93 1.07 V VVAL Ramp valleyvoltage 0.24 0.31 0.41 V PWM VOSNS = VDD ,R T = 34.8kΩ,VDD = 3.3V,FB = 0 V 85 94 dMAX Maximum dutycycle % VOSNS = VDD ,R T = 70 kΩ,VDD = 5 V,FB = 0 V 90 95 dMIN Minimum dutycycle 0 % tMIN Minimum HDRV on-time(1) 250 ns ERROR AMPLIFIER VFB Feedback inputvoltage 2.25V ≤ VDD ≤ 5 V 0.683 0.690 0.701 V IBIAS Inputbiascurrent 30 130 nA VOH High-leveloutputvoltage IOH = 0.5mA, VFB = GND 2 2.5 V VOL Low-leveloutputvoltage IOL = 0.5mA, VFB = VDD 0.08 0.15 V High-leveloutputsourceIOH VFB = GND 2.7 7 mAcurrent IOL Low-leveloutputsinkcurrent VFB = VDD 3 8 mA G BW Gain bandwidth(2) 10 MHz AOL Open loopgain 53 85 dB CURRENT LIMIT ISINK Currentlimitsinkcurrent 2.25V ≤ VDD ≤ 5.00V,R T = 69.8kΩ 165 190 215 µA VOS Currentlimitoffsetvoltage -20 0 20 mV Minimum HDRV on−timein VDD = 3.3V 200 300overcurrent tON ns Switchleading-edgeblanking 140pulsetime(2) tSS Soft-startcycles 6 cycles CurrentlimitinputvoltageVILIM 2 VDD Vrange SOFT START ISS Soft-startsourcecurrent Outputs= OFF 2 3.3 5.4 µA (1) Operationbelowtheminimum on-timecouldresultinoverlapoftheHDRV and LDRV outputs. (2) Specifiedby design.Not productiontested.

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www.ti.com SLUSB58 –SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) TJ = −55°C to125°C, TJ = TA,VDD = 5.0V (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SHUTDOWN VSD Shutdown thresholdvoltage 0.2 0.26 0.29 V DeviceenablethresholdVEN 0.25 0.28 0.32 Vvoltage OUTPUT DRIVER High-sidedriverpull-upR HDHI V(BOOT1) − V(SW) = 3.3V,ISOURCE = 100 mA 1 2.5 5 Ωresistance High-sidedriverpull-downR HDLO V(BOOT1) − V(SW) = 3.3V,ISINK = 100 mA 0.7 1.5 3 Ωresistance Low-sidedriverpull-upR LDHI PVDD = 3.3V,ISOURCE = 100 mA 1 2.5 5 Ωresistance Low-sidedriverpull-downR LDLO PVDD = 3.3V,ISINK = 100 mA 0.41 0.80 1.50 Ωresistance tLRISE Low-sidedriverrisetime 15 35 ns tLFALL Low-sidedriverfalltime 10 25 ns C LOAD = 1 nF tHRISE High-sidedriverrisetime 15 35 ns tHFALL High-sidedriverfalltime 10 25 ns THERMAL SHUTDOWN Shutdown temperature(3) 165 TSD °C Hysteresis(3) 15 CHARGE PUMP R VB2 R DS(on) VDD toBOOT2 VDD = 5 V,ISOURCE = 10 mA 2.8 6.6 10.4 Ω R B2P R DS(on) BOOT2 toPVDD VDD = 5 V,ISOURCE = 10 mA 2.8 5.6 8.4 Ω R PB1 R DS(on) PVDD toBOOT1 VDD = 5 V,ISOURCE = 10 mA 2.9 5.9 8.9 Ω POWER GOOD VPGD Pull-downvoltage VOSNS = 0.8V,IPWRGD = 0.5mA, VDD = 3.3V 50 90 140 mV Outputsense hightopower 0.7V ≤ VOSNS ≤ 0.8V,IPWRGD = 0.5mA,tONHPL 6 10 14 µsgood lowdelaytime VDD = 3.3V Outputsense lowtopower 0.6V ≤ VOSNS ≤ 0.7V,IPWRGD = 0.5mA,tONLPL 6 10 14 µsgood lowdelaytime VDD = 3.3V Shutdown hightopower good VOSNS = 0.7V,IPWRGD = 0.5mA, VDD = 3.3V,tSDHPH 2 4 6 µshighdelaytime 0 V ≤ VSS/SD ≤ 0.4V Outputsense hightonominal 0.7V ≤ VOSNS ≤ 0.8V,IPWRGD = 0.5mA,tONHPH 140 500 1000 nstopower good highdelaytime VDD = 3.3V Outputsense lowtonominal 0.6V ≤ VOSNS ≤ 0.7V,IPWRGD = 0.5mA,tONLPH 140 500 1000 nstopower good highdelaytime VDD = 3.3V TRANSIENT COMPARATORS Overvoltageoutputthreshold 23 29 35voltageVOV ReferencedtoVFB mV Hysteresis 8 15 22 Undervoltageoutputthreshold -37 -31 -25voltageVUV ReferencedtoVFB mV Hysteresis 8 15 22 OSNS minimum disableVDIS ReferencedtoVDD 0.5 Vvoltage (3) Specifiedby design.Not productiontested. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS40021-EP

SLUSB58 –SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = −55°C to125°C, TJ = TA,VDD = 5.0V (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYNCHRONIZATION SynchronizationenablelowVENSY 0.7 Vthresholdvoltage SynchronizationcurrentlimitVBLNK ReferencedtoVDD -0.7 Venablethresholdvoltage Minimum synchronizationtMIN 35 50 nsinputpulsewidth PREDICTIVE DELAY Sense voltagetomodulateVSWP -200 mVdelay Maximum delaymodulation LDRV OFF-to-HDRV ON 40 65 90 tLDHD ns Counterdelay/bittime LDRV OFF-to-HDRV ON 2.5 4.5 6.2 Maximum delaymodulation HDRV OFF-to-LDRV ON 80 tHDLD ns Counterdelay/bittime HDRV OFF-to-LDRV ON 5 RECTIFIER ZERO CURRENT COMPARATOR tZBLNK Zerocurrentblankingtime(4) 150 ns (4) Specifiedby design.Not productiontested.

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(TOP VIEW) TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NO. I/O DESCRIPTION NAME PWP Thispinprovidesa bootstrappedsupplyforthehighsideFET driver,enablingthegateofthehighBOOT1 16 I sideFET tobe drivenabove theinputsupplyrail.Connecta capacitorfromthispintotheSW pin. Thispinprovidesa secondarybootstrappingnecessaryforgenerationofPVDD. ConnectaBOOT2 13 I capacitorfromthispintoSW. COMP 5 O Outputoftheerroramplifier.RefertoElectricalCharacteristicstableforloadingconstraints. Invertinginputoftheerroramplifier.Innormaloperation,VFB isequaltotheinternalreferencelevelFB 4 I of690 mV. The gatedriveoutputforthehighsideN-channelMOSFET switchisbootstrappedtonearPVDD forHDRV 15 O good enhancement ofthehigh-sideswitch.The HDRV switchesfromBOOT1 toSW. The currentlimitpinisused tosetthecurrentlimitthreshold.A currentsinkfromthispintoGND setsthethresholdvoltageforoutputshortcircuitcurrentacrossa resistorconnectedtoVDD. ILIM/SYNC 1 I Synchronizationisaccomplishedby pullingIMAX tolessthan1 V fora periodgreaterthanthe minimum pulsewidthand thenreleasing.An open collectorordraindeviceshouldbe used.These pulsesmust be ofhigherfrequencythanthefreerunningfrequencyofthelocaloscillator. Gate driveoutputforthelow-sidesynchronousrectifierN-channelMOSFET. LDRV switchesfromLDRV 11 O PVDD toPGND. The outputsense pinisconnectedtoa resistordividerfromVOUT toGND (identicaltothemain OSNS 3 O feedbackloop)and isused tosense power good conditionand providesreferenceforthetransient comparators. PGND 10 O Power (high-current)groundused by LDRV. PWRGD 9 - Power good.Thisisan open-drainoutputwhichconnectstothesupplyviaan externalresistor. Thispinistheregulatedoutputofthecharge-pumpand providesthesupplyvoltagefortheLDRVPVDD 12 O driverstage.PVDD alsodrivesthebootstrapcircuitwhichgeneratesthevoltageon BOOT1. Externalpinforprogrammingtheoscillatorfrequency.Connnecteda resistorbetween thispinandRT 7 I GND. SGND 8 - Signalground The soft-start/shutdownpinprovidesuserprogrammablesoft-starttimingand shutdowncapabilitySS/SD 6 I forthecontroller. Thispin,used forovercurrent,zero-current,and intheanti-crossconductionsensingisconnected totheswitchednode on theconverter.Outputshortcircuitisdetectedby sensingthevoltageatthisSW 14 I pinwithrespecttoVDD whilethehigh-sideswitchison.Zerocurrentisdetectedby sensingthepin voltagewithrespecttogroundwhen thelow-siderectifierMOSFET ison. VDD 2 I Power inputforthedevice.Maximum voltageis5.5V.De-couplingofthispinisrequired. A. Formore informationon thePWP package,refertoTITechnicalBrief,LiteratureNo. SLMA002 . B. PowerPAD heatslugmust be connectedtoSGND (Pin8),orelectricallyisolatedfromallotherpins. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS40021-EP

5 SW14COMP

0.719 V 0.659 V 0.69 V OSCUVLO PREDICTIVE GATE DRIVE(tm) PWM LOGIC CLK CHARGE PUMP BOOT116 HDRV15 PWM ACTIVE DRV VDD UVLO FAULT COUNTER SOFT START FAULT SS ACTIVE DCHG CLK OC 0.28 V UVLO ISS SD VDD UVLO 1 V VDD SYNC DRV PVDD PGND10 CURRENT LIMIT COMPARATOR + + 1.4 V IRT IRT SS TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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APPLICATION INFORMATION

The TPS40021 isa low-inputvoltage,synchronous,voltagemode-buck controller.A typicalapplicationcircuitis shown inFigure1.These controllersaredesignedtoallowconstructionofhigh-performancedc-to-dcconverters withinputvoltagesfrom 2.25 V to 5.5 V, and outputvoltagesas low as 690 mV. Using a top sideN-channel MOSFET fortheprimarybuck switchresultsinlowerswitchresistancefora givengatecharge. The devicecontrolsthedelaysfrom main switchofftorectifierturnon and from rectifierturnofftomain switch turnon ina way thatminimizesdiodelosses(bothconductionand recovery)inthesynchronousrectifier.The reductionintheselossesissignificantand can mean thatfora givenconverterpower level,smallerFETs can be used,orthatheatsinkingcan be reducedoreven eliminated. The TPS40021 isthecontrollerofchoiceformost generalpurposesynchronousbuck designs,operatingintwo quadrantmode (i.e.sourceorsinkcurrent)fulltime.Thisdeviceprovidesthebestperformanceforoutputvoltage loadtransientresponseoverthewidestloadcurrentrange. The controllerprovidesfora coarse shortcircuitcurrent-limitfunctionthatprovidespulse-by-pulsecurrent limiting,as wellas integratesshortcircuitcurrentpulsestodeterminetheexistenceofa persistantfaultstateat theconverteroutput.Ifa faultisdetected,theconvertershutsdown fora periodoftime(determinedby sixsoft- startcycles)and thenrestarts.The current-limitthresholdisadjustablewitha singleresistorconnectedfromVDD to the ILIM/SYNC pin.This overcurrentfunctionisdesignedto protectagainstcatastrophicfaultsonly,and cannotbe guaranteedtoprotectagainstallovercurrentconditions. The controllerimplementsa closed-loopsoftstartfunction.Startupramp timeissetby a singleexternalcapacitor connectedtotheSS/SD pin.The SS/SD pinalsodoublesas a shutdownfunction. VoltageReference The bandgap cellisdesignedwitha trimmed,curvaturecorrected(< 1%) 0.69-Voutput,allowingoutputvoltages as lowas 690 mV tobe obtained. Oscillator The ramp waveform isa saw-toothform atthePWM frequencywitha peak voltageof1.25V, and a valleyof 0.3V. The PWM dutycycleislimitedtoa maximum of97%, allowingthebootstrapand chargepump capacitors tochargeduringeverycycle. Bootstrap/ChargePump The TPS40021 includesa chargepump toboostthedrivevoltagetothepower MOSFET ’s tohigherlevelswhen theinputsupplyislow.A capacitorconnectedfromPVDD toPGND isthestoragecap forthepump. A capacitor connectedfromSW toBOOT2 getschargedeveryswitchingcyclewhileLDRV ishighand itschargeisdumped on thePVDD capacitorwhen HDRV goes high.An internalswitchdisablesthechargepump when thevoltageon PVDD reachesapproximately4.8V and enablespumping when PVDD fallstoapproximately4.6V. The high- sidedriveruses thecapacitorfromSW toBOOT1 as itspower supply.When SW islow,thiscapacitorcharges fromthePVDD capacitor.When theSW pingoes high,thiscapacitorprovidesabove-raildriveforthehigh-side N-channelFET. PVDD, BOOT1 and BOOT2 are pre-chargedto the VDD voltageduringa shutdown condition.For low-input voltageconverters,utilizinghighergate thresholdvoltageMOSFETs, itmay be necessaryto add an Schottky diodefrom VDD (anode)toBOOT1 toguaranteesufficientvoltageforinitialstartup.Once switchingstartsthe chargepump reversesbiason theSchottkydiode. Drivers The HDRV and LDRV MOSFET driversare capable of drivinggate-to-sourcevoltagesup to 5.0 V. Using appropriateMOSFETs, a 25-A convertercan be achieved.The LDRV driverswitchesbetween VDD and ground, whilethe HDRV driverisreferencedto SW and switchesbetween BOOT1 and SW. The maximum voltage between BOOT1 and SW is5.0V when PVDD isinregulation. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS40021-EP

C1 11 Fµ R102.2 Ω C1715 nF Si7880DPC2 1 µF C310 µF R910 k Ω 470 µF 470 µF 470 F C710 µF 1 18 k Ω 30.1 k Ω C13 0.022 µF C15 47 pF C14 2200 pF 8.66 k Ω R610 k Ω 2.87 k Ω R210 k Ω 8.66 k Ω C16 1800 pF 330 µF 330 µF C10330 µF C1 122 µF C1222 µF R3 1.5 k Ω 0.75 µF

1.25 V20 A

6 SS/SD7 RT 8S G N D

3.3 V VDD Q1 Si7858DP TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com Figure1. TypicalApplication

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www.ti.com SLUSB58 –SEPTEMBER 2012 Synchronous Rectificationand PredictiveGate Delay In a normal buck converter,when the high−sideswitchturnsoff,currentisflowinginthe inductor.Since this currentcannotbe stoppedimmediatelya rectifierorcatchdeviceisused togivethiscurrenta pathtoflowand maintainvoltagelevelsat a safelevel.Thisdevicecan be a simplediodeor itcan be an actively−controlled transistorifa controlsignalisavailableto driveit.The TPS40021 providesa signalto drivean N −channel MOSFET as a synchronousrectifier.Thiscontrolsignaliscarefullycoordinatedwiththedrivesignalforthemain switchso thatthereisabsoluteminimum dead−timebetween the turnoffof one FET and the turnon of the other.This TI−patentedfunction,predictivegate delay,uses informationfrom the currentswitchingcycleto adjustthedelaysforthenextcyclevirtuallyeliminatingdiodeconductionwhilepreventingcross−conductionor shootthrough.Figure2 shows theswitch−node voltagewaveform fora synchronouslyrectifiedbuck converter duringthe synchronousrectificationperiod.Illustratedare the relativeeffectsof a fixeddelaydrivescheme (constant,pre−setdelaysfortheturn−offtoturn−on intervals),an adaptivedelaydrivescheme (variabledelays based on voltagessensed on the currentswitchingcycle)and TI’s predictivedelaydrivescheme. Since the diodevoltagedropisgreaterthantheconductiondropoftheFET, thelongertimespentindiodeconduction,the more power dissipatedintherectifierand thelowertheefficiency.Also,notshown inthefigure,isthefactthat the predictivedelaycircuitcan actuallypreventthe body diodefrom becoming forwardbiasedat all,avoiding reverserecoveryand itsassociatedlosses.Thisresultsina significantpower savingswhen themain FET turns on. The predictivegatedrivearchitectureon theTPS40021 requiresa minimum pulsewidthofgreaterthan150 ns forproperoperation.At pulsewidthsbelow 150 ns,thelow−sideFET turn−on couldoverlapthehigh−sideFET turn−offleadingtocrossconductioninthepower stage. Figure2. Switch Node Waveforms forSynchronous Buck Converter Output ShortCircuitProtection OutputshortcircuitprotectionintheTPS40021 issensed by lookingatthevoltageacrossthemain FET whileit ison.Ifthevoltageexceeds a pre-setthreshold,thecurrentpulseisterminated,and a counterinsidethedevice isincremented.Ifthiscounterfillsup,a faultconditionisdeclaredand thechipdisablesswitchingfora periodof timeand thenattemptstorestarttheconverterwitha fullsoft-startcycle.The more detailedexplanationfollows. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS40021-EP

(+) V TS ( −) Internal PWM VT S 0 V External Main Drive Normal Cycle Overcurrent Threshold Voltgage Overcurrent Cycle TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com Ineach switchingcycle,a comparatorlooksatthevoltageacrossthetopsideFET whileitison.Ifthevoltage acrossthatFET exceedsa programmablethresholdvoltage,thenthecurrentswitchingpulseisterminatedand a 3-bitcounter(eightcounts)isincrementedby one count.IfduringtheswitchingcyclethetopsideFET voltage does notexceed a presetthreshold,thenthiscounterisdecrementedby one count.(The counterdoes notwrap around from seven to zero or from zero to seven).Ifthe counterreaches a fullcount of seven,the device declaresthata faultconditionexistsattheoutputoftheconverter.Inthisstate,switchingstopsand thesoft-start capacitorisdischarged.The counterisdecrementedby one by thesoftstartcap discharge.When thesoft-start capacitorisfullydischarged,thedischargecircuitisturnedoffand thecap isallowedtochargeup atthenominal chargingrate,When the soft-startcapacitorreaches approximately1.3 V, itis dischargedagain and the overcurrentcounterisdecremented by one count.The capacitorischarged and discharged,and the counter decremented untilthe count reaches zero (a totalof sixtimes).When thishappens, the outputsare again enabledas the soft-startcapacitorgeneratesa referenceramp forthe converterto followwhileattemptingto restart.Duringthissoft-startinterval(whetherornotthecontrollerisattemptingtodo a faultrecoveryorstarting forthefirsttime),pulse-by-pulsecurrentlimitingisineffect,butovercurrentpulsesarenotcountedtodeclarea faultuntilthesoft-startcyclehas been completed.Itispossibletohave a supplytrytobringup a shortcircuitfor the durationof the soft-startperiodplusseven switchingcycles.Power stage designsshouldtake thisinto accountifitmakes a differencethermally.Figure3 shows thedetailsoftheovercurrentoperation. Figure3. Switch Node Waveforms forSynchronous Buck Converter Figure4 shows thebehaviorofkey signalsduringinitialstartup,duringa faultand a successfullyfaultrecovery. At timet0,power isappliedtotheconverter.The voltageon thesoft-startcapacitor(VCSS) beginstoramp up At t1,thesoft-startperiodisoverand theconverterisregulatingitsoutputatthedesiredvoltagelevel.From t0to t1,pulse-by-pulsecurrentlimitingwas ineffect,and fromt1onward,overcurrentpulsesarecountedforpurposes ofdeterminingifa faultexists.At t2,a heavy overloadisappliedtotheconverter.Thisoverloadisinexcessof the overcurrentthreshold,the converterstartslimitingcurrentand the outputvoltagefallsto some level dependingon theoverloadapplied.Duringtheperiodfrom t2tot3,thecounteriscountingovercurrentpulses and attimet3reachesa fullcountof7.The soft-startcapacitoristhendischarged,theoutputsaredisabled,the counterdecremented,and a faultconditionisdeclared.

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I =LIM 19 /c183/c1900.69 V RT VCSS VOUT IL O A D t 1.3 V F AUL T VDD 0.6 V cycles t0 t1 t2 t3 t10 0 6 5 4 3 2 1 0 t4 t5 t6 t7 t8 t9 1 2 3 4 5 6 7 0.6 V Counter TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 Figure4. Overcurrent/FaultWaveforms When thesoft-startcapacitorisfullydischarged,itbeginschargingagainatthesame ratethatitdoes on startup, witha nominal3-μA currentsource.As thecapacitorvoltagereachesfullcharge,itisdischargedagainand the counterisdecremented by one count.These transitionsoccurat t3 throught9.At t9,the counterhas been decrementedtozero.Now thefaultlogiciscleared,theoutputsareenabledand theconverterattemptstorestart witha fullsoft-startcycle.The convertercomes intoregulationatt10. The internalSS signalisa diodedropbelow VCSS .When VCSS reachesone diodedropabove ground,(≅ 0.6V) theoutput(VOUT )beginsit’s soft-startramp. SettingtheShortCircuitCurrentLimitThreshold Connectinga resistorfrom VDD toILIMsetsthecurrentlimit.A currentsinkinthechipcauses a voltagedrop acrosstheresistorconnectedtoILIM.Thisvoltagedrop istheshortcircuitcurrentthresholdforthepart.The currentthattheILIMpinsinksisdependenton thevalueoftheresistorconnectedtoRT and isgivenby: (1) The toleranceofthecurrentsinkistooloosetodo an accuratecurrentlimit.The main purposeisforhardfault protectionof the power switches.Given the toleranceof the ILIM sinkcurrent,and the R DS(on) range fora MOSFET, itisgenerallypossibletoapplya loadthatthermallydamages theconverter.Thisdeviceisintended forembedded converterswhere loadcharacteristicsaredefinedand can be controlled.A smallcapacitorcan be added between ILIM and VDD forfiltering.However, capacitorsshould not be used ifthe synchronization functionistobe used. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS40021-EP

50 ns to 100 ns 50 ns to 100 ns R (k ) =T /c87 /c19037.736 10/c183 f (kHz)OSC - 5.09 (k/c87/c41 C =SS ISS/c190VFB /c183t (F)SS CSS SS/SD TPS40021 SHUTDOWN 3.3 Aµ TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com Soft-Startand Shutdown The soft−startand shutdown functionsare common to the SS/SD pin.The voltageat thispinover−ridesthe referencevoltageon theerroramplifierduringstartup.Thiscontrolstheoutputvoltageslew rateand thesurge currentrequiredtochargetheoutputcapacitoratstartup,allowingfora smooth startupwithno overshootofthe outputvoltage.InitialHDRV pulsewidthsduringSoft−Startaretypicallyverynarrow,likelylessthan150ns.As a result,HDRV and LDRV can be on simultaneously,resultingincross−conductionthe MOSFETs of the power stage.To minimizecross−conductionduringsoft−start,thesoft−starttimewhen thepulsewidthsare lessthan 150ns shouldbe kepttoa minimum. A shutdown featurecan be implementedby pullingSS/SD toGND viaa transistoras shown inFigure5. Figure5. Shutdown Implementation (2) where tSS isthestartup timeinseconds. SwitchingFrequency The switchingfrequencyisprogrammed by a resistorfrom RT toSGND. Nominal switchingfrequencycan be calculatedby: (3) Synchronization The TPS40021 can be synchronizedtoan externalreferencefrequencyhigherthanthefreerunningoscillator frequency.The recommended method istouse a diodeand a push pulldrivesignalas shown inFigure6. Figure6. SynchronizationMethods

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www.ti.com SLUSB58 –SEPTEMBER 2012 This designallowssynchronizationup to the maximum operatingfrequencyof 1 MHz. For best resultsthe nominaloperatingfrequencyofa converterthatistobe synchronizedshouldbe keptas closeas practicableto thesynchronizationfrequencytoavoidexcessivenoiseinducedpulsewidthjitter.A good targetistoshootfor thefreerunfrequencytobe 80% ofthesynchronizedfrequency.Thisensuresthatthesynchronizationsourceis thefrequencydeterminingelementinthesystemand nottoadverselyaffectnoiseimmunity. Othermethods ofimplementingthesynchronizationfunctionincludeusingan open collectororopen drainoutput devicedirectly,ordiscreetdevicestopulltheILIM/SYNC pindown. These do work butperformancecan sufferat highfrequencybecause theILIM/SYNC pinmust riseto(VDD − 1.0V) beforethenextswitchingcyclebegins. Any time thatthisrequiresis directlysubtractedfrom the maximum pulse widthavailableand should be consideredwhen choosingdevicesto driveILIM/SYNC. Consequently,the lowestoutputcapacitancedevices work best. Duringa synchronizationcycle,the currentsinkon the ILIM/SYNC pinbecomes disabledwhen ILIM/SYNC is pulledbelow 1.0V. The ILIM/SYNC currentsinkremainsdisableduntilILIM/SYNC reaches(VDD −1.0V) This removes theloadon theILIM/SYNC pintoallowthevoltagetoslewrapidlydependingon theILIMresistorand any straycapacitanceon thepin.To maximizethisslewrate,minimizestraycapacitanceon thispin. The durationofthesynchronizationpulsepullingILIM/SYNC low shoud be between 50 ns and 100 ns.Longer durationsmay limitthemaximum obtainabledutycycle. TransientComparators and Power Good The TPS40021 makes use ofa separatepin,OSNS, tomonitoroutputvoltageforthesetwo functions.Innormal operation,OSNS isconnectedtotheoutputviaa resistordivider.Itisimportanttomake thisdividerthesame ratioas thedividerforthefeedbacknetworkso thatinnormaloperationthevoltageatOSNS isthesame as the voltageatFB, 0.69V nominal. The PWRGD pinisan open drainoutputthatispulledlow when thevoltageatOSNS fallsoutside0.69V ±4.6% (approximately).A delayhas been purposelybuiltintothePWRGD pinpullinglow inresponsetoan outofband voltageon OSNS, tominimizetheneed forfilteringthesignalintheeventofa noiseglitchcausinga briefoutof band OSNS voltage.The PWRGD signalreturnstohighwhen theOSNS signalreturnstoapproximately±1% of nominal(0.69V ±1%). The transientcomparatorsoverridethe conventionalvoltagecontrolloopwhen the outputvoltageexceeds a ±4.6% window.Iftheoutputtransitionishigh(i.e.loadstepsdown from90% loadto10 % load)thentheHDRV gatedriveisterminated,0% dutycycle,theLDRV gatedriveisturnedon tosinkoutputcurrentuntilVOUT returns to within1% of nominal.Converselywhen VOUT drops outsidethe window (i.e.steploadincreasesfrom 10% load to 90% load)HDRV increasesto maximum duty cycleuntilVOUT returnsto within1% of nominal(see Figure7). Duringstart-up,the transientcomparatorscontrolthe stateof PWRGD as previouslydescribed.However, the operationofthegatedriveoutputsisnotaffected(seeFigure8). The transientcomparatorsprovidean improvementinloadtransientrecoverytimeifused properly.In some situations,recoverytimemay be one halfofthetimerequiredwithouttransientcomparators.Keep inmind that thetransientcomparatorconceptisa double-edgedsword.Whiletheyprovideimprovedtransientrecoverytime, theycan alsoleadto instabilityifincorrectlyapplied.For properfunctionality,designa feedbackloopforthe converterthatplacestheclosedloopunitygainfrequencyatleastfivetimeshigherthanthe0-dB frequencyof theoutputL-C filter.Ifnot,thefeedbackloopcannotrespondtotheringoftheL-C on a transientevent.The ring islikelyto be largeenough to disturbthe transientcomparatorsand the resultisa power oscillator.Another helpfulactionistoground thefeedbackloopdividerand theOSNS dividerattheSGND pin.Make sureboth dividersmeasure thesame physicallocationon theoutputbus.These helpavoidproblemswithresistivedrops athigherloadscausingproblems. ConnectingOSNS to VDD disablesthe transientcomparators.This also disablesthe PWRGD function. Alternatively,OSNS and FB can be tiedtogether.Thisconnectionallowsa properPWRGD atstartup,though transientperformancediminishes. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS40021-EP

VOUT − 1% 1.5 µsVOUT 4 sµ VDD 0.3 V 0.6 V 500 ns Transient Comparators Disabled Transient Comparators Enabled SS/SD PWRGD 1.3 V 98 % Duty Cycle 0 % Duty Cycle 98 % Duty Cycle 0 % Duty Cycle 10 µs 500 n s 500 n s 4.6% − 4.6% −1% < 10 µs 10 µs FB PWRGD SW − 4.6% TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com Figure7. Duty Cycle Waveforms Figure8. TransientComparator Waveforms

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www.ti.com SLUSB58 –SEPTEMBER 2012 Layout Considerations SuccessfuloperationoftheTPS40021 isdependentupon theproperconverterlayoutand groundingtechniques. High currentreturnsfortheSR MOSFET ’s source,inputcapacitance,outputcapacitance,PVDD capacitance, and inputbypass capacitors(ifapplicable),shouldbe kepton a singlegroundplaneorwide traceconnectedto thePGND (pin10)througha shortwide trace.Controlcomponents connectedtosignalground,as wellas the PowerPad thermalpad, shouldbe connectedto a singleground planeconnectedto SGND (pin8) througha shorttrace.SGND and PGND shouldbe connectedata singlepointusinga narrowtrace. Properoperationof PredictiveGate Drivetechnologyand IZERO functionsare dependent upon detectinglow- voltagethresholdson theSW node.To ensurethatthesignalattheSW pinaccuratelyrepresentsthevoltageat themain switchingnode,theconnectionfromSW (pin14)tothemain switchingnode oftheconvertershouldbe keptas shortand wide as possibleand shouldideallybe kepton thetoplevelwiththepower components.Ifthe SW tracemust traversemultipleboardlayersbetween theTPS40021 and themain switchingnode,multiplevias shouldbe used tominimizethetraceimpedance. Gate driveoutputs,LDRV and HDRV (pins11 and 15, respectively)shouldbe keptas shortas possibleto minimizeinductancesinthetraces.Ifthegatedriveoutputsneed totraversemultipleboardlayersmultiplevias shouldbe used. Charge pump components,BOOT1, BOOT2, PVDD, and any inputbypass capacitors(ifrequired),shouldbe kept as closeas possibleto theirrespectivepins.Ceramic bypass capacitorsshould be used ifthe input capacitorsare locatedmore than a coupleof inchesaway from the TPS40021. Ifa bypass capacitorisnot needed the tracefrom the inputcapacitorsto VDD (pin2)shouldbe kept as shortand wide as possibleto minimizetraceimpedance.Ifmultipleboardlayersaretraversedmultipleviasshouldbe used. Manufacturer’s instructionsshouldbe followedforproperlayoutoftheexternalMOSFETs. Thermalimpedances giveninthemanufacturer’s datasheetsare fora givenmountingtechniquewitha specifiedsurfacearea under thedrainoftheMOSFET. PowerPad package informationcan be foundintheAPPLICATION INFORMATION sectionofthisdatasheet. Refer to TPS40021 EVM −001 High EfficiencySynchronous Buck ConverterwithPWM ControllerEvaluation Module (HPA009) User’s Guide,(LiteratureNo. SLUU144A )fora typicalboardlayout. The PowerPAD package provideslow thermalimpedance forheat removalfrom the device.The PowerPAD derivesitsname and low thermalimpedance fromthelargebondingpad on thebottomofthedevice.The circuit boardmust have an areaofsolder-tinned-copperunderneaththepackage.The dimensionsofthisareadepends on thesizeofthePowerPAD package.Fora 16-pinTSSOP (PWP) package theareais5 mm x 3.4mm [3]. Thermalviasconnectthisareatointernalorexternalcopperplanesand shouldhave a drilldiametersufficiently smallso thatthe viaholeiseffectivelypluggedwhen the barrelof the viaisplatedwithcopper.Thisplugis needed topreventwickingthesolderaway from theinterfacebetween thepackage body and thesolder-tinned areaunderthedeviceduringsolderreflow.Drilldiametersof0.33mm (13mils)works wellwhen 1-ozcopperis platedatthesurfaceoftheboard whilesimultaneouslyplatingthebarrelofthevia.Ifthethermalviasare not pluggedwhen thecopperplatingisperformed,thena soldermask materialshouldbe used tocap theviaswitha diameterequalto the viadiameterof 0.1 mm minimum. Thiscappingpreventsthe solderfrom beingwicked throughthethermalviasand potentiallycreatinga soldervoidunderthepackage.RefertoPowerPAD Thermally Enhanced Package[3]formore informationon thePowerPAD package. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS40021-EP

C = I DIN(min) OUT(max) (max) /c183 /c183 1/c190f VOSC IN(ripple)/c183 ESR =OUT VRIPPLE/c190IRIPPLE C =OUT(min) IRIPPLE/c1908 /c183 /c183f V RIPPLE L =(min) /c190 /c190VOUT f I/c183RIPPLE /c1833 - VOUT VIN(max) TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com REFERENCE DESIGN Thisdesignused theTPS40020 PWM controllertofacilitatea step-downapplicationfrom 3.3-Vto1.5V (see Figure11).Designspecificationsinclude:

  • Inputvoltage:2.5V ≤ VIN ≤ 5.0V
  • Nominaloutputvoltage:3.3V
  • OutputvoltageVOUT :1.5V
  • OutputcurrentIOUT :20 A
  • Switchingfrequency:300 kHz SettingtheFrequency Choosingtheoptimum switchingfrequencyiscomplicated.The higherthefrequency,thesmallertheinductance and capacitanceneeded,so thesmallerthesize,butthenthetheswitchinglossesare higher,theefficiencyis poorer.Forthisevaluationmodule,300 kHz ischosen forreasonableefficiencyand size. A resistorR4, which isconnectedfrom pin7 to ground,programs the oscillatorfrequency.The approximate operatingfrequencyiscalculatedinEquation3. UsingEquation2,R T iscalculatedtobe 120 kΩ and a 118-kΩ resistorischosen for300 kHz operation. InductanceValue The inductancevaluecan be calculatedby Equation4. (4) where IRIPPLE istheripplecurrentflowingthroughtheinductor,which affectstheoutputvoltagerippleand core losses. Based on 24% ripplecurrentand 300 kHz,theinductancevalueiscalculatedto0.71μH and a 0.75-μH inductor (partnumber isCDEP149 −0R7) ischosen.The DCR ofthisinductoris1.1m Ω and thelossis440 mW, whichis approximately1.5% ofoutputpower. (5) (6) With 1.2% outputvoltageripple,the needed capacitanceisat least109 μF and itsESR shouldbe lessthan 3.75m Ω.Three2-V,470-μF,POSCAP capacitorsfromSanyo areused.The ESR is10 m Ω each. The requiredinputcapacitanceiscalculatedinEquation7.The calculatedvalueisapproximately390 μF fora 100-mV inputripple.Three 6.0-V,330-μF POSCAP capacitorswith10 m Ω ESR areused tohandle10 A ofRMS inputcurrent.Additionally,two ceramiccapacitorsareused toreducetheswitchingripplecurrent. (7)

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6 SS/SD7 RT 8 SGND

3.3 V C11 Fµ R102.2 Ω C1715 nF S7880DP C2 1 µF C310 µF R9 10 k Ω 470 µF 470 µF 470 F C710 µF 1 18 k Ω R17 30.1 k Ω C13 0.022 µFC15 47 pF C14220 pF R5 8.66 k Ω R6 10 k Ω 2.87 k Ω R210 k Ω 8.66 k Ω C16 1800 pF 330 µF 330 µF C10330 µF C1 122 µF C1222 µF R3 1.43 k Ω 0.75 µF

1.5 V20 A

www.ti.com SLUSB58 –SEPTEMBER 2012 Figure9. ReferenceDesign Schematic Inputand Output Capacitors The outputcapacitanceand itsESR needed arecalculatedinEquation5 and Equation6. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS40021-EP

–150 –100 –50 100 150 200 –50 –40 –30 –20 –10 100 1k 10k 100k Phase (°)Gain (dB) Oscillator Frequency (kHz) Phase Gain A(s) = /c190(1 + 14 7) [1 + 16 ( 2 + 3)]s C R s C R R/c183 /c183 /c183 /c183 /c183 s R C/c183 /c183 /c1832 14 [(1 + C15/c190C14 ) + 7 15] (1 + 8 16)s R C s R C/c183 /c183 /c183 /c183 /c183 f =P2 /c1901 2 7 15/c112/c183 /c183R C (assuming C C14 > 15) f =P1 /c1901 2 8 16/c112/c183 /c183R C f =Z2 /c1901 2 2 16/c112/c183 /c183R C (assuming R R2 > 8) f =Z1 /c1901 2 7 14/c112/c183 /c183R C TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com Compensation Design Voltage-modecontrolisused inthisevaluationmodule,usingR2, R7, R8, C14, C15, and C16 toforma Type-III compensator network.The L-C frequencyof the power stage isapproximately4.9-kHzand the ESR-zero is around34 kHz.The overallcrossoverfrequency,f0db,ischosen at43-kHz forreasonabletransientresponseand stability.Two zerosfZ1 and fZ2 fromthecompensatoraresetat2.4kHz and 4 kHz.The two poles,fP1 and fP2 are setat34 kHz and 115 kHz.The frequencyofpolesand zerosaredefinedby thefollowingequations: (8) (9) (10) (11) The transferfunctionforthecompensatoriscalculatedinEquation12. (12) Figure10 shows thecloseloopgainand phase.The overallcrossoverfrequencyisapproximately30 kHz.The phase marginis57°. OVERALL GAIN AND PHASE vs OSCILLATOR FREQUENCY Figure10. MOSFETs and Diodes For a 1.5-Voutputvoltage,the lowerthe R DS(on) of the MOSFET, the higherthe efficiency.Due to the high currentand highconductionloss,theMOSFET shouldhave verylow conductionresistance(RDS(on))and thermal resistance.Si7858DP ischosen foritslowR DS(on) (between3 m Ω and 4 m Ω)and Power-Pak package. CurrentLimiting ResistorR3 setstheshortcurrentlimitthreshold.The R DS(on) oftheupperMOSFET isused as a currentsensor. The currentlimit,IOUT(CL) isinitializedat30% above themaximum outputcurrent,IOUT(max) ,which is28 A. Then R3 can be calculatedinEquation14 and yieldsa valueof1.4kΩ.An R3 of1.43kΩ isselected.

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0.70 0.75 0.80 0.85 0.90 0.95 0 5 10 15 20 Efficiency (%) Load Current (A) V = 2.5 VIN V = 4.0 VIN V = 5.0 VIN V = 3.3 VIN VFB/c190R1 = VOUT/c190R R1 + 2 /c190 /c190/c174 /c1740.69V R1 = 1.5V R k1 + 10 /c87 R k1 = 8.52 /c87 R3 = /c87)/c190K R I/c183 /c183DS(on) OUT(CL) ILIM = /c1901.5 0.004 28/c183 /c183 A ILIM = 1.4 (k I =LIM (19 /c183VFB/c190R4 ) = (19 /c183/c1900.69 V 118 k/c87 ) = 111.1 (µ )A TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 (13) (14) where R DS(on) istheon-resistorofQ1 (4m Ω) Temperaturecoefficient,K=1.5 VFB = 0.69V R4 = 118 kΩ VoltageSense Regulator R1 and R2 operateas the outputvoltagedivider.The erroramplifierreferencevoltage(VFB ) is0.69 V. The relationshipbetween theoutputvoltageand dividerisdescribedinEquation15.Using a 10-kΩ resistorforR2 and 1.5-Voutputregulation,R1 iscalculatedas 8.52kΩ,8.66kΩ isselectedforR1. (15) TransientComparator The outputvoltagetransientcomparatorsprovidea quickresponse,firststrike,approach to outputvoltage transients.The outputvoltageissensed througha resistordividerattheOSNS pin,usingR5 and R6 shown in Figure9. Ifan overvoltageconditionisdetected,the HDRV gate driveisshutoffand the LDRV gate driveis turnedon untiltheoutputisreturnedtoregulation.Similarly,ifan outputundervoltageconditionissensed,the HDRV gate drivegoes to 95% dutycycleto pump the outputback up quickly.The voltagedividershouldbe exactlythesame as resistorsR1 and R2 discussedpreviously.ResistorR5 = 8.66kΩ and R6 = 10 kΩ inthis evaluationmodule. EfficiencyCurves The testedefficiencyatdifferentloadsand inputvoltagesareshown inFigure11.The maximum efficiencyisas highas 93% at1.5-Voutput.The efficiencyisaround88% when theloadcurrent(ILOAD )is20 A. EFFICIENCY vs OUTPUT LOAD CURRENT Figure11. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS40021-EP

V = 3.3 V I = 20 A IN LOAD V (2 V/div)SW Time (1 s/div)μ G004 Time (1 s/div)μ V = 3.3 V I = 20 A IN LOAD V (10 mV/div)OUTac TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com TypicalOperatingWaveforms Figure12. Figure13. TransientResponse and Output RippleVoltage The outputrippleisabout15 mV P−P at20-A output.When theloadchanges from4 A to20 A, theovershooting voltageisabout35 mV. Figure 14 shows the transientwaveform with and withoutthe transientcomparator.Using the transient comparatoryieldsa settlingtimeof10-μs fasterthanwithout. The outputrippleisabout15 mV P−P at20-A output.When theloadchanges from 0 A to13 A, theovershoot voltageisapproximately80 mV, and theundershootisisapproximately60 mV as shown inFigure15.When the transientcomparatoristriggered,thepowergood (PWRGD) signalgoes low.

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I (10 A/div)OUT V (100 mV/div)OUTac Time (200 s/div)μ V (2.5 V/div) PWRGD Time (10 s/div)μ Time (10 s/div)μ Time (200 s/div)μ I (10 A/div)OUT V (50 mV/div)OUTac V = 3.3 VIN I (10 A/div)OUT With Transient Comparator Without Transient Comparator V = 3.3 VIN I (10 A/div)OUT With Transient Comparator Without Transient Comparator G005 TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 Figure14. TransientResponse Undershoot/Overshoot Figure15. TransientResponse Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS40021-EP

0.500 0.525 0.550 0.575 0.600 0.625 0.650 0.675 0.700 1251007550250–50 –25 Shutdown Supply Current (mA) Junction T emperature (°C) G009 683 685 687 689 691 693 695 697 1251007550250–50 –25 Reference V oltage (mV) Junction T emperature (°C) G010 1251007550250–50 –25 Maximum Duty Cycle (%) Junction Temperature (°C) G007 V = 5 V, R = 35 kDD T Ω V = 3.3 V, R = 69.8 kDD T Ω 450 550 500 600 650 700 750 800 850 900 950 1000 1251007550250–50 –25 Oscillator Frequency (kHz) Junction Temperature (°C) G008 R = 69.8 kT Ω R = 35 kT Ω TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS SPACER MAXIMUM DUTY CYCLE OSCILLATOR FREQUENCY vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure16. Figure17. SHUTDOWN SUPPLY CURRENT REFERENCE VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure18. Figure19.

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–20 –15 –10 1251007550250–50 –25 ILIM Offset Voltage (mV) Junction Temperature (°C) G013 V = 2.0DD V = 3.2DD V = 4.9DD 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.28 0.29 0.30 1251007550250–50 –25 Shutdown Threshold V oltage (V) Junction T emperature (°C) G014 Disable Enable 100 200 300 400 500 600 700 800 900 1000 160140120100806020 40 Switching Frequency (kHz) Timing Resistance (k ) Ω G011 V = 3.9 VIN 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 1251007550250–50 –25 Soft-Start Sourcing Current ( A) μ Junction T emperature (°C) G012 TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) SPACER SWITCHING FREQUENCY SOFT-START SOURCING CURRENT vs vs TIMING RESISTANCE JUNCTION TEMPERATURE Figure20. Figure21. ILIMOFFSET VOLTAGE SHUTDOWN THRESHOLD VOLTAGE vs vs JUNCTION TEMPERATURE JUNCTION TEMPERATURE Figure22. Figure23. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS40021-EP

V = 3.3 V f = 300 kHz DD SW V = 1.5 VOUT Time (1 s/div)μ LDRV SW VOUT G018 Time (20 ms/div) V = 3.3 V f = 300 kHz DD SW V = 1.5 VOUT SS/SD SW VOUT 180 182 184 186 188 190 192 194 196 198 200 1251007550250–50 –25 ILIM Sink Current ( A) μ Junction Temperature (°C) G015 V = 3 V R = 69.8 k DD T Ω G016 V = 3.3 V f = 300 kHz DD SW V = 1.5 VOUT Time (1 s/div)μ LDRV SW VOUT TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SPACER ILIMSINK CURRENT vs JUNCTION TEMPERATURE Figure24. Figure25.TPS40021 DiscontinuousMode (DCM) Figure26.TPS40021 IZERO Detection– DCM Figure27.Output CurrentFaultOperation

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Time (1 ms/div) SS/SD PWRGD VOUT V = 3.3 V f = 300 kHz I DD SW V = 1.5 V = 5 A OUT LOAD G022 Time (200 s/div)μ COMP SW SD V = 3.3 V f = 300 kHz I DD SW V = 1.5 V = 5 A OUT LOAD G019 Time (1 ms/div) V = 3.3 V f = 300 kHz I DD SW V = 1.5 V = 5 A OUT LOAD SS/SD PWRGD VOUT G020 Time (25 s/div)μ V = 3.3 V f = 300 kHz I DD SW V = 1.5 V = 5 A OUT LOAD PVDD SW VOUT TPS40021-EP www.ti.com SLUSB58 –SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) SPACER Figure28.Start-UpOperationWithoutTransient Figure29.PVDD Hysteresis Comparators Figure30.Start-UpOperationWith TransientComparators Figure31.COMP Shutdown Operation Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS40021-EP

Time (1 s/div)μ V = 3.3 V f = 300 kHz DD SW V = 1.5 VOUT SS/SD PWRGD G024 Time (500 ns/div) V = 3.3 V f = 330 kHz DD SYNC V = 1.5 VOUTLDRV SW ILIM TPS40021-EP SLUSB58 –SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SPACER Figure32.PWRGD Shutdown Operation Figure33.ExternalSynchronization

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www.ti.com 9-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS40021MPWPEP ACTIVE HTSSOP PWP 16 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 40021M TPS40021MPWPREP ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 40021M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 9-Sep-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS40021-EP :

  • Catalog: TPS40021 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40021MPWPREP HTSSOP PWP 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-Feb-2016 Pack Materials-Page 2

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