TPS40020_16 TI1 | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 34
Technical content
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 /C0069/C0078/C0072/C0065/C0078/C0067/C0069/C0068/C0044 /C0076/C0079/C0087/C0262/C0073/C0078/C0080/C0085/C0084 /C0086/C0079/C0076/C0084/C0065/C0071/C0069/C0262/C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082
FEATURES
/C0068Operating Input Voltage 2.25 V to 5.5 V /C0068Output Voltage as Low as 0.7 V /C00681% Internal 0.7 V Reference /C0068Predictive Gate Drive N-Channel MOSFET Drivers for Higher Efficiency /C0068Externally Adjustable Soft-Start and Short Circuit Current Limit /C0068Programmable Fixed-Frequency
100 KHz-to-1 MHz Voltage-Mode Control
/C0068Source-Only Current or Source/Sink Current /C0068Quick Response Output Transient Comparators with Power Good Indication Provide Output Status /C006816-Pin PowerPAD Package
APPLICATIONS
/C0068Networking Equipment /C0068Telecom Equipment /C0068Base Stations /C0068Servers /C0068DSP Power
DESCRIPTION
The TPS4002x family of dc-to-dc controllers are designed for non-isolated synchronous buck regulators, providing enhanced operation and design flexability through user programmability. The TPS4002x utilizes a proprietary Predictive Gate Drive technology to minimize the diode conduction losses associated with the high-side and synchronous rectifier N-channel MOSFET transistions. The integrated charge pump with boost circuit provides a regulated 5-V gate drive for both the high side and synchronous rectifier N-channel MOSFETs. The use of the Predictive Gate Drive technology and charge pump/boost circuits combine to provide a highly efficient, smaller and less expensive converter. Design flexibility is provided through user programmability of such functions as: operating frequency, short circuit current detection thresholds, soft-start ramp time, and external synchronization frequency. The operating frequency is programmable using a single resistor over a frequency range of 100 kHz to 1 MHz. Higher operating frequencies yield smaller component values for a given converter power level as well as faster loop closure. ILIM/ SYNC VDD OSNS COMP HDRV BOOT2 PVDD LDRV VDD 2.25 V − 5.5 V 4 FB BOOT1 TPS40020
6 SS/SD
8 SGND
UDG−02094 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 PowerPAD and Predictive Gate Drive are trademarks of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com Copyright 2004, Texas Instruments Incorporated Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com DESCRIPTION (CONTINUED) The short circuit current detection is programmable through a single resistor, allowing the short circuit current limit detection threshold to be easily tailored to accommodate different size (RDS(on)) MOSFETs. The short circuit current function provides pulse-by-pulse current limiting during soft-start and short term transient conditions as well as a fault counter to handle longer duration short circuit current conditions. If a fault is detected the controller shuts down for a period of time determined by six (6) consecutive soft-start cycles. The controller automatically retries the output every seventh (7 th) soft-start cycle. In addition to determining the off time during a fault condition, the soft-start ramp provides a closed loop controlled ramp of the converter output during startup. Programmability allows the ramp rate to be adjusted for a wide variety of output L-C component values. The output voltage transient comparators provide a quick response , first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin. If an overvoltage condition is detected the HDRV gate drive is shut-off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. In either case, the PowerGood open drain output pulls low to indicate an output voltage out of regulation condition. The PowerGood output can be daisy-chained to the SS/SD pin or enable pin of other controllers or converters for output voltage sequencing. The transient comparators can be disabled by simply tying the OSNS pin to VDD. The TPS4002x can be externally synchronized through the ILIM/SYNC pin up to 1.5× the free-running frequency. This allows multiple contollers to be synchronized to eliminate EMI concerns due to input beat frequencies between controllers. INTERNAL BLOCK DIAGRAM UDG−0209 2 VDDDISABLE BOOT213 VDD ILIM/SYNC1 PWRGD
5 SW14COMP
3 OSNS
0.719 V 0.659 V 0.69 V OSCUVLO PREDICTIVE GATE DRIVE(tm) PWM LOGIC CLK CHARGE PUMP BOOT116 HDRV15 PWM ACTIVE DRV VDD UVLO FAULT COUNTER SOFT START FAULT SS ACTIVE DCHG CLK OC 0.28 V UVLO ISS SD VDD UVLO 1 V VDD SYNC DRV PVDD PGND10 CURRENT LIMIT COMPARATOR 1.4 V IRT IRT SS Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA LOAD CURRENT (1) PACKAGE PART NUMBER −40°C to 85°C SOURCE Plastic HTSSOP (PWP)(2) TPS40020PWP −40°C to 85°C SOURCE/SINK Plastic HTSSOP (PWP)(2) TPS40021PWP (1)See page 7 for explanation. (2)The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40020PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(4) TPS4002X UNIT SS/SD, VDD, PVDD, OSNS −0.3 to 6 BOOT2, BOOT1 VSW + 6 Input voltage range, VIN SW −3.0 to 10.5 V Input voltage range, VIN SWT (SW transient < 50 ns) −5 V FB, ILIM −0.3 to 6.0 Output voltage range, VOUT COMP , PWRGD, RT −0.3 to 6 Sink current, IS PWRGD 10 mA Operating virtual junction temperature range, TJ −40 to 125 Storage temperature, Tstg −55 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 C (4)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input voltage, VIN 2.25 5.5 V Operating junction temperature, TJ −40 85 °C THERMAL PAD ILIM/SYNC VDD OSNS FB COMP SS/SD RT SGND BOOT1 HDRV SW BOOT2 PVDD LDRV PGND PWRGD PWP P ACKAGE (5)(6) (TOP VIEW) (5) For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002. (6) PowerPAD/C0116 heat slug must be connected to SGND (Pin 8), or electrically isolated from all other pins. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 85°C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VDD Input voltage range, VDD 2.25 5.50 VVPVDD PVDD pin voltage VDD = 3.3 V 4.9 5.2 V Switching current 500 kHz, No load on HDRV, LDRV 3.5 5.0 IDD Quiescent current FB = 0.8 V 2.0 3.0 mAIDD Shutdown current SS/SD = 0 V, Outputs OFF 0.38 1.00 mA VUVLO Minimum on-voltage 1.95 2.05 2.15 V VUVLO Hysteresis 80 130 200 mV OSCILLATOR fOSC Accuracy 2.25 V ≤ VDD ≤ 5.00 V, RT = 69.8 kΩ 425 500 575 kHzfOSC Accuracy 2.25 V ≤ VDD ≤ 5.00 V, RT = 34.8 kΩ 800 950 1100 kHz VRAMP Ramp voltage VPEAK −VVAL 0.80 0.93 1.07 VVVAL Ramp valley voltage 0.24 0.31 0.41 V PWM dMAX Maximum duty cycle VOSNS = VDD , RT = 34.8 kΩ, VDD = 3.3 V, FB = 0 V 85% 94% dMAX Maximum duty cycle VOSNS = VDD , RT = 70 kΩ, VDD = 5.0 V, FB = 0 V 90% 95% dMIN Minimum duty cycle 0% tMIN Minimum HDRV on-time(2) 250 ns ERROR AMPLIFIER IBIAS Input bias current 30 130 nA VOH High-level output voltage IOH = 0.5 mA, VFB = GND 2.0 2.5 VVOL Low-level output voltage IOL = 0.5 mA, VFB = VDD 0.08 0.15 V IOH High-level output source current VFB = GND 3 7 mAIOL Low-level output sink current VFB = VDD 3 8 mA G BW Gain bandwidth(1) 5 10 MHz AOL Open loop gain(1) 55 85 dB CURRENT LIMIT ISINK Current limit sink current 2.25 V ≤ VDD ≤ 5.00 V, RT = 69.8 kΩ 165 190 215 µA VOS Current limit offset voltage −20 0 20 mV tON Minimum HDRV on−time in overcurrent VDD = 3.3 V 200 300 nstON Switch leading-edge blanking pulse time(1) 140 ns tSS Soft-start cycles 6 cycles VILIM Current limit input voltage range 2 VDD V SOFT START ISS Soft-start source current Outputs = OFF 2.0 3.3 5.4 µA (1)Ensured by design. Not production tested. (2)Operation below the minimum on-time could result in overlap of the HDRV and LDRV outputs. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = −40°C to 85°C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SHUTDOWN VSD Shutdown threshold voltage 0.22 0.26 0.29 VVEN Device enable threshold voltage 0.25 0.28 0.32 V OUTPUT DRIVER R HDHI High-side driver pull-up resistance V(BOOT1) − V(SW) = 3.3 V, ISOURCE = 100mA 1.0 2.5 5.0 R HDLO High-side driver pull-down resistance V(BOOT1) − V(SW) = 3.3 V, ISINK =100mA 0.8 1.5 3.0 Ω R LDHI Low-side driver pull-up resistance PVDD = 3.3 V, ISOURCE =100 mA 1.0 2.5 5.0 R LDLO Low-side driver pull-down resistance PVDD = 3.3 V, ISINK =100 mA 0.45 0.80 1.50 tLRISE Low-side driver rise time 15 35 tLFALL Low-side driver fall time C LOAD = 1 nF 10 25 nstHRISE High-side driver rise time C LOAD = 1 nF 15 35 ns tHFALL High-side driver fall time 10 25 THERMAL SHUTDOWN TSD Shutdown temperature(1) 165 °CTSD Hysteresis(1) 15 °C CHARGE PUMP RVB2 R DS(on) VDD to BOOT2 VDD = 5.0 V, I SOURCE =10 mA 2.8 6.6 10.4 R B2P R DS(on) BOOT2 to PVDD VDD = 5.0 V, I SOURCE =10 mA 2.8 5.6 8.4 Ω R PB1 R DS(on) PVDD to BOOT1 VDD = 5.0 V, I SOURCE =10 mA 2.9 5.9 8.9 Ω POWER GOOD VPGD Pull-down voltage VOSNS = 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 50 90 140 mV tONHPL Output sense high to power good low delay time 0.7 V ≤ VOSNS ≤ 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 6 10 14 tONLPL Output sense low to power good low delay time 0.6 V ≤ VOSNS ≤ 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V 6 10 14 s tSDHPH Shutdown high to power good high delay timeVOSNS = 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V, 0.0 V ≤ VSS/SD ≤ 0.4 V 2 4 6 µs tSDLPL Shutdown low to power good low delay timeVOSNS = 0.7 V, IPWRGD =0.5 mA, tONHPH Output sense high to nominal to power good high delay time 0.7 V ≤ VOSNS ≤ 0.8 V, IPWRGD =0.5 mA, VDD = 3.3 V 140 500 1000 ns tONLPH Output sense low to nominal to power good high delay time 0.6 V ≤ VOSNS ≤ 0.7 V, IPWRGD =0.5 mA, VDD = 3.3 V 140 500 1000 ns TRANSIENT COMPARATORS VOV Overvoltage output threshold voltage 23 29 35 VOV Hysteresis Referenced to VFB 8 15 22 mV VUV Undervoltage output threshold voltage Referenced to VFB −37 −31 −25 mV VUV Hysteresis 8 15 22 VDIS OSNS minimum disable voltage Referenced to VDD 0.5 V (1)Ensured by design. Not production tested. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = −40°C to 85°C, TJ = TA, VDD = 5.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYNCHRONIZATION VENSY Synchronization enable low threshold voltage 0.7 VBLNK Synchronization current limit enable threshold voltage Referenced to VDD −0.7 V tMIN Minimum synchronization input pulse width 35 50 ns PREDICTIVE DELAY VSWP Sense voltage to modulate delay −200 mV tLDHD Maximum delay modulation LDRV OFF-to-HDRV ON 40 65 90 tLDHD Counter delay/bit time LDRV OFF-to-HDRV ON 2.5 4.5 6.2 ns tHDLD Maximum delay modulation HDRV OFF-to-LDRV ON 55 80 105 ns tHDLD Counter delay/bit time HDRV OFF-to-LDRV ON 2.2 5.0 6.5 RECTIFIER ZERO CURRENT COMPARATOR VSW Sense voltage to turn off rectifier MOSFET TPS40020 LDRV output = OFF −5 −2.5 2 mV tZBLNK Zero current blanking time(1) 150 ns (1)Ensured by design. Not production tested. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION BOOT1 16 I This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high side FET to be driven above the input supply rail. Connect a capacitor from this pin to the SW pin. BOOT2 13 I This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a capacitor from this pin to SW. COMP 5 O Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints. FB 4 I Inverting input of the error amplifier. In normal operation, VFB is equal to the internal reference level of 690 mV. HDRV 15 O The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for good enhancement of the high-side switch. The HDRV switches from BOOT1 to SW. ILIM/SYNC 1 I The current limit pin is used to set the current limit threshold. A current sink from this pin to GND sets the threshold voltage for output short circuit current across a resistor connected to VDD. Synchronization is accomplished by pulling IMAX to less than 1 V for a period greater than the minimum pulse width and then releasing. An open collector or drain device should be used. These pulses must be of higher frequency than the free running frequency of the local oscillator. LDRV 11 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from PVDD to PGND. OSNS 3 O The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main feedback loop) and is used to sense power good condition and provides reference for the transient comparators. PGND 10 O Power (high-current) ground used by LDRV. PWRGD 9 − Power good. This is an open-drain output which connects to the supply via an external resistor. PVDD 12 O This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV driver stage. PVDD also drives the bootstrap circuit which generates the voltage on BOOT1. RT 7 I External pin for programming the oscillator frequency. Connnected a resistor between this pin and GND. SGND 8 − Signal ground SS/SD 6 I The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability for the controller . SW 14 I This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected to the switched node on the converter. Output short circuit is detected by sensing the voltage at this pin with respect to VDD while the high-side switch is on. Zero current is detected by sensing the pin voltage with respect to ground when the low-side rectifier MOSFET is on. VDD 2 I Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com
APPLICATION INFORMATION
The TPS4002x series of devices are low-input voltage, synchronous, voltage mode-buck controllers. A typical application circuit is shown in Figure 1. These controllers are designed to allow construction of high-performance dc-to-dc converters with input voltages from 2.25 V to 5.5 V, and output voltages as low as 690 mV. Using a top side N-channel MOSFET for the primary buck switch results in lower switch resistance for a given gate charge. The device controls the delays from main switch off to rectifier turn on and from rectifier turn off to main switch turn on in a way that minimizes diode losses (both conduction and recovery) in the synchronous rectifier. The reduction in these losses is significant and can mean that for a given converter power level, smaller FETs can be used, or that heat sinking can be reduced or even eliminated. The TPS40021 is the controller of choice for most general purpose synchronous buck designs, operating in two quadrant mode (i.e. source or sink current) full time. This choice provides the best performance for output voltage load transient response over the widest load current range. The TPS40020 operates in single quadrant mode (source current only) full time, allowing the paralleling of converters. Single quadrant operation ensures one converter does pull current from a paralleled converter. A converter using one of these controllers emulates a non-synchronous buck converter at light loads. When current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as a synchronous buck converter to maximize efficiency. The controller provides for a coarse short circuit current-limit function that provides pulse-by-pulse current limiting, as well as integrates short circuit current pulses to determine the existence of a persistant fault state at the converter output. If a fault is detected, the converter shuts down for a period of time (determined by six soft-start cycles) and then restarts. The current-limit threshold is adjustable with a single resistor connected from VDD to the ILIM/SYNC pin. This overcurrent function is designed to protect against catastrophic faults only, and cannot be guaranteed to protect against all overcurrent conditions. The controller implements a closed-loop soft start function. Startup ramp time is set by a single external capacitor connected to the SS/SD pin. The SS/SD pin also doubles as a shutdown function. VOLTAGE REFERENCE The bandgap cell is designed with a trimmed, curvature corrected (< 1%) 0.69-V output, allowing output voltages as low as 690 mV to be obtained. Oscillator The ramp waveform is a saw-tooth form at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.3 V. The PWM duty cycle is limited to a maximum of 97%, allowing the bootstrap and charge pump capacitors to charge during every cycle. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com The TPS4002X series includes a charge pump to boost the drive voltage to the power MOSFET’s to higher levels when the input supply is low. A capacitor connected from PVDD to PGND is the storage cap for the pump. A capacitor connected from SW to BOOT2 gets charged every switching cycle while LDRV is high and its charge is dumped on the PVDD capacitor when HDRV goes high. An internal switch disables the charge pump when the voltage on PVDD reaches approximately 4.8 V and enables pumping when PVDD falls to approximately 4.6 V. The high-side driver uses the capacitor from SW to BOOT1 as its power supply. When SW is low, this capacitor charges from the PVDD capacitor. When the SW pin goes high, this capacitor provides above-rail drive for the high-side N-channel FET. PVDD, BOOT1 and BOOT2 are pre-charged to the VDD voltage during a shutdown condition. For low-input voltage converters, utilizing higher gate threshold voltage MOSFETs, it may be necessary to add an Schottky diode from VDD (anode) to BOOT1 to guarantee sufficient voltage for initial start up. Once switching starts the charge pump reverses bias on the Schottky diode. When operating the TPS40020 under no load or extremely light-load conditions the controller will be operating in discontinuous Mode (DCM); reverse current is prevented from flowing in the synchronous rectifier. In DCM the on times for both the HDRV and LDRV pulses can become too narrow to provide adequate charging of PVDD and BOOT1 outputs, causing their voltages to collapse. Insufficient PVDD and BOOT1 voltages prevent the external MOSFETS from becomming fully enhanced, causing loss of converter output regulation. Schottky diodes from VIN (anode) to PVDD, and VIN (anode) to BOOT1, as well as a pre-load can be added to maintain PVDD and BOOT1 at voltage levels sufficient enough to fully enhance the external MOSFETs. The amount of pre-load typically ranges from 50 mA to 100 mA depending on operating conditions and external MOSFET selection. Drivers The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.0 V. Using appropriate MOSFETs, a 25-A converter can be achieved. The LDRV driver switches between VDD and ground, while the HDRV driver is referenced to SW and switches between BOOT1 and SW. The maximum voltage between BOOT1 and SW is 5.0 V when PVDD is in regulation. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com 1 µF R10 2.2 Ω C17 15 nF Si7880DP C2 1 µF 10 µF 10 kΩ 470 µF 470 µF 470 /C0109F 10 µF 118 kΩ 30.1 kΩ C13 0.022 µF C15 47 pF C14 2200 pF 8.66 kΩ 10 kΩ 2.87 kΩ 10 kΩ 8.66 kΩ C16 1800 pF 330 µF 330 µF C10 330 µF C11 22 µF C12 22 µF 1.5 kΩ 0.75 µF 1.25 V 20 A ILIM/SYNC VDD OSNS COMP HDRV BOOT2 PVDD LDRV 4F B BOOT1 TPS4002XPWP +++ 3.3 V + + + VDD UDG−03031 Si7858DP Figure 1. Typical Application
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com Synchronous Rectification and Predictive Gate Delay In a normal buck converter, when the high−side switch turns off, current is flowing in the inductor. Since this current cannot be stopped immediately a rectifier or catch device is used to give this current a path to flow and maintain voltage levels at a safe level. This device can be a simple diode or it can be an actively−controlled transistor if a control signal is available to drive it. The TPS4002X provides a signal to drive an N−channel MOSFET as a synchronous rectifier. This control signal is carefully coordinated with the drive signal for the main switch so that there is absolute minimum dead−time between the turn off of one FET and the turn on of the other. This TI−patented function, predictive gate delay, uses information from the current switching cycle to adjust the delays for the next cycle virtually eliminating diode conduction while preventing cross−conduction or shoot through. Figure 2 shows the switch−node voltage waveform for a synchronously rectified buck converter during the synchronous rectification period. Illustrated are the relative effects of a fixed delay drive scheme (constant, pre−set delays for the turn−off to turn−on intervals), an adaptive delay drive scheme (variable delays based on voltages sensed on the current switching cycle) and TI’s predictive delay drive scheme. Since the diode voltage drop is greater than the conduction drop of the FET, the longer time spent in diode conduction, the more power dissipated in the rectifier and the lower the efficiency. Also, not shown in the figure, is the fact that the predictive delay circuit can actually prevent the body diode from becoming forward biased at all, avoiding reverse recovery and its associated losses. This results in a significant power savings when the main FET turns on. The predictive gate drive architecture on the TPS40020/21 requires a minimum pulse width of greater than 150 ns for proper operation. At pulse widths below 150 ns, the low−side FET turn−on could overlap the high−side FET turn−off leading to cross conduction in the power stage. UDG−01144 GND Fixed Delay Adaptive Delay Predictive Delay Channel Conduction Body Diode Conduction Figure 2. Switch Node Waveforms for Synchronous Buck Converter
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com Output Short Circuit Protection Output short circuit protection in the TPS4002x is sensed by looking at the voltage across the main FET while it is on. If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is incremented. If this counter fills up, a fault condition is declared and the chip disables switching for a period of time and then attempts to restart the converter with a full soft-start cycle. The more detailed explanation follows. In each switching cycle, a comparator looks at the voltage across the top side FET while it is on. If the voltage across that FET exceeds a programmable threshold voltage, then the current switching pulse is terminated and a 3-bit counter (eight counts) is incremented by one count. If during the switching cycle the top side FET voltage does not exceed a preset threshold, then this counter is decremented by one count. (The counter does not wrap around from seven to zero or from zero to seven). If the counter reaches a full count of seven, the device declares that a fault condition exists at the output of the converter. In this state, switching stops and the soft-start capacitor is discharged. The counter is decremented by one by the soft start cap discharge. When the soft-start capacitor is fully discharged, the discharge circuit is turned off and the cap is allowed to charge up at the nominal charging rate, When the soft-start capacitor reaches approximately 1.3 V, it is discharged again and the overcurrent counter is decremented by one count. The capacitor is charged and discharged, and the counter decremented until the count reaches zero (a total of six times). When this happens, the outputs are again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting to restart. During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault until the soft-start cycle has been completed. It is possible to have a supply try to bring up a short circuit for the duration of the soft-start period plus seven switching cycles. Power stage designs should take this into account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation. UDG−03029 (+) VTS (−) Internal PWM VTS 0 V External Main Drive Normal Cycle Overcurrent Threshold Voltgage Overcurrent Cycle Figure 3. Switch Node Waveforms for Synchronous Buck Converter
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com Setting the Short Circuit Current Limit Threshold Connecting a resistor from VDD to ILIM sets the current limit. A current sink in the chip causes a voltage drop across the resistor connected to ILIM. This voltage drop is the short circuit current threshold for the part. The current that the ILIM pin sinks is dependent on the value of the resistor connected to RT and is given by: IILIM/C004319.0/C00320.69 V R T The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault protection of the power switches. Given the tolerance of the ILIM sink current, and the R DS(on) range for a MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended for embedded converters where load characteristics are defined and can be controlled. A small capacitor can be added between ILIM and VDD for filtering. However, capacitors should not be used if the synchronization function is to be used. Soft-Start and Shutdown The soft−start and shutdown functions are common to the SS/SD pin. The voltage at this pin over−rides the reference voltage on the error amplifier during startup. This controls the output voltage slew rate and the surge current required to charge the output capacitor at startup, allowing for a smooth startup with no overshoot of the output voltage. Initial HDRV pulse widths during Soft−Start are typically very narrow, likely less than 150ns. As a result, HDRV and LDRV can be on simultaneously, resulting in cross−conduction the MOSFETs of the power stage. To minimize cross−conduction during soft−start, the soft−start time when the pulse widths are less than 150ns should be kept to a minimum. A shutdown feature can be implemented by pulling SS/SD to GND via a transistor as shown in Figure 5. C SS SS/SD TPS4002x SHUTDOWN 3.3 µA Figure 5. Shutdown Implementation
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com The TPS4002x can be synchronized to an external reference frequency higher than the free running oscillator frequency. The recommended method is to use a diode and a push pull drive signal as shown in Figure 6. PREFERRED UDG−03032 ALTERNATE Minumize Output/Stray Capacitance on ILIM Node ILIM/SYNC VDD TPS4002XPWP VDD ILIM/SYNC VDD TPS4002XPWP VDD 50 ns to 100 ns 50 ns to 100 ns Figure 6. Synchronization Methods source is the frequency determining element in the system and not to adversely affect noise immunity. any stray capacitance on the pin. To maximize this slew rate, minimize stray capacitance on this pin. durations may limit the maximum obtainable duty cycle.
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com UDG−03181 VOUT − 1% 1.5 µsVOUT 4 µs VDD 0.3 V 0.6 V 500 ns Transient Comparators Disabled Transient Comparators Enabled SS/SD PWRGD 1.3 V Figure 8. Transient Comparator Waveforms switching node, multiple vias should be used to minimize the trace impedance. minimize trace impedance. If multiple board layers are traversed multiple vias should be used.
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com Manufacturer’s instructions should be followed for proper layout of the external MOSFETs. Thermal impedances given in the manufacturer’s datasheets are for a given mounting technique with a specified surface area under the drain of the MOSFET. PowerPad package information can be found in the APPLICATION INFORMATION section of this datasheet. Refer to TPS40021 EVM−001 High Efficiency Synchronous Buck Converter with PWM Controller Evaluation Module (HPA009) User’s Guide, (Literature No. sluu144A) for a typical board layout. The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP (PWP) package the area is 5 mm x 3.4 mm [3]. Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally Enhanced Package [3] for more information on the PowerPAD package. Not Recommended for New Designs
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com REFERENCE DESIGN This design used the TPS40020 PWM controller to facilitate a step-down application from 3.3-V to 1.5 V. (see Figure 29) Design specifications include: /C0068Input voltage: 2.5 V ≤ VIN ≤ 5.0 V /C0068Nominal output voltage: 3.3 V /C0068Output voltage VOUT : 1.5 V /C0068Output current IOUT : 20 A /C0068Switching frequency: 300 kHz DESIGN PROCEDURE Setting the Frequency Choosing the optimum switching frequency is complicated. The higher the frequency, the smaller the inductance and capacitance needed, so the smaller the size, but then the the switching losses are higher, the efficiency is poorer. For this evaluation module, 300 kHz is chosen for reasonable efficiency and size. A resistor R4, which is connected from pin 7 to ground, programs the oscillator frequency. The approximate operating frequency is calculated in equation (3) R T (k/C0087)/C004337.736/C0032103 fOSC (kHz) /C00425.09(k/C0087) Using equation (2), RT is calculated to be 120 kΩ and a 118-kΩ resistor is chosen for 300 kHz operation. Inductance Value The inductance value can be calculated by equation (2). L(min)/C0043 V OUT f/C0032IRIPPLE /C0032/C04661 /C0042 V OUT V IN(max) /C0467 where IRIPPLE is the ripple current flowing through the inductor, which affects the output voltage ripple and core losses. Based on 24% ripple current and 300 kHz, the inductance value is calculated to 0.71 µH and a 0.75-µH inductor (part number is CDEP149−0R7) is chosen. The DCR of this inductor is 1.1 mΩ and the loss is 440 mW, which is approximately 1.5% of output power. C OUT(min) /C0043 IRIPPLE 8 /C0032f/C0032V RIPPLE ESR OUT /C0043 V RIPPLE IRIPPLE With 1.2% output voltage ripple, the needed capacitance is at least 109 µF and its ESR should be less than 3.75 mΩ. Three 2-V, 470-µF, POSCAP capacitors from Sanyo are used. The ESR is 10 mΩ each. The required input capacitance is calculated in equation (5). The calculated value is approximately 390 µF for a 100-mV input ripple. Three 6.0-V, 330-µF POSCAP capacitors with 10 mΩ ESR are used to handle 10 A of RMS input current. Additionally, two ceramic capacitors are used to reduce the switching ripple current. C IN(min)/C0043IOUT(max) /C0032D (max)/C0032 1 fOSC /C0032V IN(ripple) (4) (5) (6) (7) (8) Not Recommended for New Designs
Figure 27. Reference Design Schematic
/C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0048 /C0084/C0080/C0083/C0052/C0048/C0048/C0050/C0049 SLUS535D − MARCH 2003 − REVISED JULY 2007 www.ti.com REFERENCE DESIGN MOSFETs and Diodes For a 1.5-V output voltage, the lower the RDS(on) of the MOSFET, the higher the efficiency. Due to the high current and high conduction loss, the MOSFET should have very low conduction resistance (RDS(on)) and thermal resistance. Si7858DP is chosen for its low RDS(on) (between 3 mΩ and 4 mΩ) and Power-Pak package. Current Limiting Resistor R3 sets the short current limit threshold. The RDS(on) of the upper MOSFET is used as a current sensor. The current limit, IOUT(CL) is initialized at 30% above the maximum output current, IOUT(max) , which is 28 A. Then R3 can be calculated in equation (11) and yields a value of 1.4 kΩ. An R3 of 1.43 kΩ is selected. ILIM /C0043/C046619 /C0032 V FB R4 /C0467/C0043/C046619 /C00320.69 V 118 k/C0087/C0467/C0043111.1(/C0109A) R3 /C0043 K /C0032R DS(on)/C0032IOUT(CL) ILIM /C00431.5/C00320.004/C003228 A ILIM /C00431.4(k/C0087) where /C0068R DS(on) is the on-resistor of Q1 (4 mΩ) /C0068Temperature coefficient, K=1.5 /C0068VFB = 0.69 V /C0068R4=118 kΩ Voltage Sense Regulator R1 and R2 operate as the output voltage divider. The error amplifier reference voltage (VFB ) is 0.69 V. The relationship between the output voltage and divider is described in equation (8). Using a 10-kΩ resistor for R2 and 1.5-V output regulation, R1 is calculated as 8.52 kΩ, 8.66 kΩ is selected for R1. V FB R1 /C0043 V OUT R1 /C0041R2 /C01790.69 V R1 /C00431.5 V R1 /C004110 k/C0087/C0179R1 /C00438.52 k/C0087 Transient Comparator The output voltage transient comparators provide a quick response, first strike, approach to output voltage transients. The output voltage is sensed through a resistor divider at the OSNS pin, using R5 and R6 shown in Figure 27. If an overvoltage condition is detected, the HDRV gate drive is shut off and the LDRV gate drive is turned on until the output is returned to regulation. Similarly, if an output undervoltage condition is sensed, the HDRV gate drive goes to 95% duty cycle to pump the output back up quickly. The voltage divider should be exactly the same as resistors R1 and R2 discussed previously. Resistor R5=8.66 kΩ and R6=10 kΩ in this evaluation module. (14) (15) (16) Not Recommended for New Designs
Figure 34. Transient Response
www.ti.com 12-Jun-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS40020PWP NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40020 TPS40020PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40020 TPS40020PWPR NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40020 TPS40020PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40020 TPS40021PWP NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40021 TPS40021PWPG4 NRND HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40021 TPS40021PWPR NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40021 TPS40021PWPRG4 NRND HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 40021 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
www.ti.com 12-Jun-2013 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS40021 :
- Enhanced Product: TPS40021-EP NOTE: Qualified Version Definitions:
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40020PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0 TPS40021PWPR HTSSOP PWP 16 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2016 Pack Materials-Page 2
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated