TPS3103 TI1 | Alldatasheet
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3.3 V 1.6 V GND MR Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TPS3103,TPS3106,TPS3110 SLVS363F –AUGUST 2001–REVISED NOVEMBER 2015 TPS3103,TPS3106,TPS3110UltralowSupply-CurrentVoltageMonitor WithOptionalWatchdog
1 Features 3 Description
The TPS310x and TPS311x families of supervisory 1• Precision Supply Voltage Supervision Range:
- Supply Current of 1.2 μA (Typical) During power-on, RESET is asserted low when the• RESET Defined With Input Voltages as Low as supply voltage (VDD) becomes higher than 0.4 V.
0.4 V Thereafter, the supervisory circuit monitors VDD and
keeps the RESET output low as long as VDD remains• Power-On Reset Generator With a Delay Time of below the threshold voltage (VIT–). To ensure proper130 ms system reset, after VDD surpasses the threshold• Push/Pull or Open-Drain RESET Outputs voltage, an internal timer delays the transition of the
- Package Temperature Range: –40°C to 85°C RESET signal from low to high for the specified time. When VDD drops below VIT–, the output transitions low 2 Applications again.
- Applications Using Low-Power DSPs, All the devices of this family have a fixed-sense Microcontrollers, or Microprocessors threshold voltage (VIT–) set by an internal voltage divider.• Portable and Battery-Powered Equipment
- Intelligent Instruments The TPS3103 and TPS3106 devices have an active- low, open-drain RESET output and either an• Wireless Communication Systems integrated power-fail input (PFI) or SENSE input with• Industrial Equipment corresponding outputs for monitoring other voltages.
- Notebook and Desktop Computers The TPS3110 has an active-low push/pull RESET and a watchdog timer to monitor the operation of Typical Application Schematic microprocessors. All three devices have a manual reset pin that can be used to force the outputs low regardless of the sensed voltages. The product spectrum is designed for supply voltages of 0.9 V up to 3.3 V. The circuits are available in 6-pin SOT-23 packages. The TPS31xx family is characterized for operation over a temperature range of –40°C to 85°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS3103xxx TPS3106xxx SOT-23 (6) 2.90 mm × 1.60 mm TPS3110xxx (1) For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS3103,TPS3106,TPS3110 SLVS363F –AUGUST 2001–REVISED NOVEMBER 2015 www.ti.com Table of Contents
4 Revision History
Changes from Revision E (September 2007) to Revision F Page
- Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
- Changed "free-air temperature" to "junction temperature" in Recommended Operating Conditions condition
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5 Available Options
DEVICE RESET OUTPUT RSTSENSE, RSTVDD OUTPUT SENSE INPUT WDI INPUT PFO OUTPUT TPS3103 Open-drain Open-drain TPS3106 Open-drain ✓ TPS3110 Push-pull ✓ ✓
6 Pin Configuration and Functions
NAME TPS3103 TPS3106 TPS3110 GND 2 2 2 — GND Manual-reset input. Pull low to force a reset. RESET remains low as long as MR 3 3 3 I MR is low and for the time-out period after MR goes high. Leave unconnected or connect to VDD when unused. Power-fail input compares to 0.551 V with no additional delay. Connect toPFI 4 — — I VDD if not used. PFO 5 — — O Power-fail output. Goes high when voltage at PFI rises above 0.551 V. RESET 1 — 1 O Active-low reset output. Either push-pull or open-drain output stage. Active-low reset output. Logic level at RSTSENSE only depends on theRSTSENSE — 5 — O voltage at SENSE and the status of MR. Active-low reset output. Logic level at RSTVDD only depends on the voltageRSTVDD — 1 — O at VDD and the status of MR. A reset is asserted if the voltage at SENSE is lower than 0.551 V. ConnectSENSE — 4 4 I to VDD if unused. VDD 6 6 6 I Supply voltage. Powers the device and monitors its own voltage. Watchdog timer input. If WDI remains high or low longer than the time-out WDI — — 5 I period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS3103 TPS3106 TPS3110
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage(2) VDD –0.3 3.6 V MR Pin, RESET (push-pull) VMR, VRESET (push-pull) –0.3 VDD + 0.3 V All other pins(2) –0.3 3.6 V Maximum low output current IOL –5 5 mA Maximum high output current IOH –5 5 mA Input current IIK (VSENSE < 0 V or VSENSE > VDD) –10 10 mA Output current IOK (VO < 0 V or VO > VDD)(3) –10 10 mA Continuous total power dissipation See Thermal Information Operating, TJ –40 85 °C Temperature Storage, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t = 1000h continuously. (3) Output is clamped for push-pull outputs by the back gate diodes internal to the IC. No clamp exists for the open-drain outputs.
7.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification JESD22-C101, ±500all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range, unless otherwise noted. MIN NOM MAX UNIT VDD (1) Supply voltage 0.9 3.3 V VSENSE SENSE voltage 0 VDD V WDI High-level input voltage VIH at MR 0.7 × VDD V WDI Low-level input voltage VIL at MR 0.3 × VDD V WDI Input transition rise and fall rate at Δt/ΔV at MR 100 ns/V MR MR voltage 0 VDD V PFI PFI voltage 0 3.3 V TJ Operating temperature –40 85 °C (1) For proper operation of SENSE, PFI, and WDI functions: VDD ≥ 0.8 V.
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7.4 Thermal Information
THERMAL METRIC(1) DBV (SOT-23) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 183.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 123.3 °C/W RθJB Junction-to-board thermal resistance 29.4 °C/W ψJT Junction-to-top characterization parameter 20.5 °C/W ψJB Junction-to-board characterization parameter 29 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS3103 TPS3106 TPS3110
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7.5 Electrical Characteristics
over operating junction temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD = 3.3 V, IOH = –3 mA VDD = 1.8 V, IOH = –2 mA 0.8 × VDD VOH High-level output voltage VDD = 1.5 V, IOH = –1 mA V VDD = 0.9 V, IOH = –0.4 mA VDD = 0.5 V, IOH = –5 μA 0.7 × VDD VDD = 3.3 V, IOL = 3 mA VDD = 1.5 V, IOL = 2 mA VOL Low-level output voltage 0.3 V VDD = 1.2 V, IOL = 1 mA VDD = 0.9 V, IOL = 500 μA VOL Low-level output voltage RESET only VDD = 0.4 V, IOL = 5 μA 0.1 V TPS31xxE09 0.854 0.86 0.866 TPS31xxE12 1.133 1.142 1.151 TPS31xxE15 1.423 1.434 1.445Negative-going inputVIT– TA = 25°C Vthreshold voltage(1) TPS31xxE16 1.512 1.523 1.534 TPS31xxH20 1.829 1.843 1.857 TPS31xxK33 2.919 2.941 2.963 Negative-going inputVIT–(S) SENSE, PFI VDD ≥ 0.8 V, TA = 25°C 0.542 0.551 0.559 Vthreshold voltage(1) 0.8 V ≤ VIT– < 1.5 V 20 VHYS Hysteresis at VDD input 1.6 V ≤ VIT– < 2.4 V 30 mV 2.5 V ≤ VIT– < 3.3 V 50 Temperature coefficient of VIT−, PFI,T(K) TA = –40°C to 85°C –0.012 –0.019 %/KSENSE VHYS(S) Hysteresis at SENSE, PFI input VDD ≥ 0.8 V 15 mV MR MR = VDD, VDD = 3.3 V –25 25 IIH High-level input current nASENSE, PFI, SENSE, PFI, WDI = VDD, –25 25WDI VDD = 3.3 V MR MR = 0 V, VDD = 3.3 V –47 –33 –25 μA IIL Low-level input current SENSE, PFI, SENSE, PFI, WDI = 0 V, –25 25 nAWDI VDD = 3.3 V High-level output currentIOH Open-drain VDD = VIT– + 0.2 V, VOH = 3.3 V 200 nAat RESET(2) VDD > VIT– (average current), 1.2 3VDD < 1.8 V VDD > VIT– (average current), 2 4.5IDD Supply current μAVDD > 1.8 V VDD < VIT–, VDD < 1.8 V 22 VDD < VIT–, VDD > 1.8 V 27 Internal pullup resistor at MR 70 100 130 kΩ CIN Input capacitance at MR, SENSE, PFI, WDI VIN = 0 V to VDD 1 pF (1) To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed close to the supply terminals. (2) Also refers to RSTVDD and RSTSENSE.
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7.6 Timing Requirements
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted.
7.7 Switching Characteristics
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to 85°C, unless otherwise noted. VDD ≥ 1.1 × VIT–, MR = 0.7 × VDD.tD Delay time 65 130 195 msSee Timing Requirements. Figure 1. RESET Timing Diagram for TPS3103
Figure 2. PFO Timing Diagram for TPS3103 Figure 3. Timing Diagram for TPS3106
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Figure 4. Timing Diagram for TPS3110
7.8 Typical Characteristics
Figure 5. TPS3110E09 Supply Current vs Supply Voltage Figure 6. TPS3110E09 Low-Level Output Voltage vs Low- Figure 7. TPS3110E09 Low-Level Output Voltage vs Low- Figure 8. TPS3110E09 High-Level Output Voltage vs High- Figure 9. TPS3110K33 High-Level Output Voltage vs High- Figure 10. Minimum Pulse Duration at VDDvs Threshold
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Figure 11. Normalized Threshold Voltage vs Free-Air Temperature
8 Detailed Description
8.1 Overview
VHYS). When VDD drops below VIT–, the output becomes active again. regardless of the sensed voltages.
8.2 Functional Block Diagrams
Figure 12. TPS3103 Functional Block Diagram
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8.3 Feature Description
8.3.1 Watchdog
The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, RESET becomes active for the time period (tD). This event also reinitializes the watchdog timer.
8.3.2 Manual Reset (MR)
Many μC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (tD) after MR returns high. The input has an internal 100-kΩ pullup resistor, so it can be left open if it is unused. Connect a normally open momentary switch from MR to GND to create a manual reset function. External debounce is not required. If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1-μF capacitor from MR to GND provides additional noise immunity. If there is a possibility of transient or DC conditions causing MR to rise above VDD, a diode should be used to limit MR to a diode drop above VDD.
8.3.3 PFI, PFO
The TPS3103 has an integrated power-fail (PFI) comparator with a separate open-drain (PFO) output. The PFI and PFO can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply, and has no effect on RESET. An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the power-fail threshold (VIT – (S)), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately 15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power consumption and to assure that the current into the PFI pin can be neglected, compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO unconnected. For proper operation of the PFI-comparator, the supply voltage (VDD) must be higher than 0.8 V.
8.3.4 SENSE
The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls below the sense-threshold (VIT − (S)), reset is asserted. On the TPS3106 device, a dedicated RSTSENSE output is available. On the TPS3110 device, the logic signal from SENSE is OR-wired with the logic signal from VDD or MR. An internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above 0.551 V plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply voltage must be higher than 0.8 V.
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8.4 Device Functional Modes
Table 1. TPS3103 Function Table Table 2. TPS3106 Function Table Table 3. TPS3110 Function Table(1) (1) Function of watchdog timer not shown.
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9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 17. Battery Monitoring With 3-μA Supply Current for Device and Resistor Divider
9.2.1 Design Requirements
the battery should almost be zero, especially when the battery is discharged. TPS3106 device has two reset outputs. One output (RSTVDD) is triggered from the voltage monitored at VDD. the threshold voltage at VDD. The voltage of the battery is monitored using the SENSE input.
9.2.2 Detailed Design Procedure
- VTRIP is the voltage of the battery at which a reset is asserted
- VIT–(S) is the threshold voltage at SENSE = 0.551 V
- R1 was chosen for a resistor current in the 1-μA range
- With VTRIP = 1.6 V
- R1 ≡ 1.9 × R2
- R1 = 820 kΩ, R2 = 430 kΩ (1)
9.2.3 Application Curve
Figure 18. Normalized Threshold Voltage vs Free-Air Temperature
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10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range between 0.9 V and 3.3 V.
11 Layout
11.1 Layout Guidelines
- Place the VDD decoupling capacitor close to the device.
- Avoid using long traces for the VCC supply node. The VCC capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the maximum VDD voltage.
11.2 Layout Example
Figure 19. Example Layout (DBV Package)
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Spice Models
product folders under Tools & Software.
12.1.2 Device Nomenclature
Table 4. Ordering Information(1) (2) Custom threshold voltages are available. Minimum order quantities apply. Contact factory for details and availability.
12.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 5. Related Links
12.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
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12.4 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPS3103 TPS3106 TPS3110
www.ti.com 16-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN0402002DBVR ACTIVE SOT-23 DBV 6 TBD Call TI Call TI -40 to 85 TPS3103E12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFWI TPS3103E12DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFWI TPS3103E12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFWI TPS3103E12DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFWI TPS3103E15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFXI TPS3103E15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFXI TPS3103E15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFXI TPS3103E15DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFXI TPS3103H20DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFYI TPS3103H20DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFYI TPS3103H20DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFYI TPS3103H20DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFYI TPS3103K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGRI TPS3103K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGRI TPS3103K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGRI TPS3103K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGRI
www.ti.com 16-Sep-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS3106E09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFZI TPS3106E09DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFZI TPS3106E09DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFZI TPS3106E09DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PFZI TPS3106E16DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGSI TPS3106E16DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGSI TPS3106E16DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGSI TPS3106E16DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGSI TPS3106K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGBI TPS3106K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGBI TPS3106K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGBI TPS3106K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGBI TPS3110E09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGII TPS3110E09DBVT OBSOLETE SOT-23 DBV 6 TBD Call TI Call TI -40 to 85 PGII TPS3110E09DBVTG4 OBSOLETE SOT-23 DBV 6 TBD Call TI Call TI -40 to 85 TPS3110E12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGJI TPS3110E12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGJI TPS3110E15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGKI TPS3110E15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGKI
www.ti.com 16-Sep-2014 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS3110E15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGKI TPS3110E15DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGKI TPS3110K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGLI TPS3110K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGLI TPS3110K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGLI TPS3110K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PGLI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 16-Sep-2014 Addendum-Page 4 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2014 Pack Materials-Page 1
(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3103E12DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3103E12DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3103E12DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TPS3103E12DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 TPS3103E15DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3103E15DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 TPS3103H20DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3103H20DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3103H20DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 TPS3103H20DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2014 Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3103K33DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3103K33DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 TPS3106E09DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3106E09DBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TPS3106E16DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3106E16DBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TPS3106K33DBVR SOT-23 DBV 6 3000 180.0 180.0 18.0 TPS3106K33DBVT SOT-23 DBV 6 250 180.0 180.0 18.0 TPS3110E09DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3110E12DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3110E12DBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TPS3110E15DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3110E15DBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TPS3110K33DBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TPS3110K33DBVT SOT-23 DBV 6 250 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Sep-2014 Pack Materials-Page 3
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