TPS3106E16 TI | Alldatasheet
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Technical content
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com
features
/C0068Precision Supply Voltage Supervision Range: 0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, 3.3 V /C0068High Trip Point Accuracy: 0.75% /C0068Supply Current of 1.2 µA (Typ) /C0068RESET Defined With Input Voltages as Low as 0.4 V /C0068Power On Reset Generator With a Delay Time of 130 ms /C0068Push/Pull or Open-Drain RESET Outputs /C0068SOT23-6 Package /C0068Temperature Range... −40°C to 85°C typical applications /C0068Applications Using Low-Power DSPs, Microcontrollers or Microprocessors /C0068Portable/Battery-Powered Equipment /C0068Intelligent Instruments /C0068Wireless Communication Systems /C0068Programmable Controls /C0068Industrial Equipment /C0068Notebook/Desktop Computers /C0068Automotive Systems
description
The TPS310x, TPS311x families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor- based systems. During power on, RESET is asserted when the supply voltage (VDD ) becomes higher than 0.4 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state to ensure proper system reset. The delay time starts after VDD has risen above the VIT. When the VDD drops below the VIT, the output becomes active again. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider. Copyright 2001 − 2004 Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. (TOP VIEW) RESET GND MR VDD PFI TPS3103 DBV PACKAGE PFO (TOP VIEW) RSTVDD GND MR VDD SENSE TPS3106 DBV PACKAGE RSTSENSE (TOP VIEW) RESET GND MR VDD SENSE TPS3110 DBV PACKAGE WDI TPS3106E33DBV VDD RSTVDD RSTSENSE GND SENSE GND Vcore VIO RESET R3 DSP 3.3 V 1.6 V GND typical application circuit MR
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com description (continued) The TPS3103 and TPS3106 have an active-low, open drain RESET output. The TPS3110 has an active-low push/pull RESET. The product spectrum is designed for supply voltages of 0.9 V up to 3.3 V. The circuits are available in a 6-pin SOT-23 package. The TPS31xx family is characterized for operation over a temperature range of −40°C to 85°C. AVAILABLE OPTIONS DEVICE RESET OUTPUT RSTSENSE , RSTVDD OUTPUT SENSE INPUT WDI INPUT PFO OUTPUT TPS3103 /C0110 Open drain /C0110 Open drain TPS3106 /C0110 Open drain /C0110 TPS3110 /C0110 Push-pull /C0110 /C0110
PACKAGE INFORMATION
TA DEVICE NAME THRESHOLD VOLTAGE, VIT MARKING TPS3103E12DBVR ‡ TPS3103E12DBVT § 1.142 V PFWI TPS3103E15DBVR ‡ TPS3103E15DBVT § 1.434 V PFXI TPS3103H20DBVR ‡ TPS3103H20DBVT § 1.84 V PFYI TPS3103K33DBVR ‡ TPS3103K33DBVT § 2.941 V PGRI TPS3106E09DBVR /C0123‡ TPS3106E09DBVT § 0.86 V PFZI −40°C to 85°C TPS3106E16DBVR ‡ TPS3106E16DBVT § 1.521 V PGSI−40 C to 85C TPS3106K33DBVR ‡ TPS3106K33DBVT § 2.941 V PGBI TPS3110E09DBVR ‡ TPS3110E09DBVT § 0.86 V PGII TPS3110E12DBVR ‡ TPS3110E12DBVT § 1.142 V PGJI TPS3110E15DBVR ‡ TPS3110E15DBVT § 1.434 V PGKI TPS3110K33DBVR /C0123‡ TPS3110K33DBVT § 2.941 V PGLI † TPS3106E09 and TPS3110K33 will be available in August 2001; all other versions will be available in October 2001. ‡ The DBVR passive indicates tape and reel of 3000 parts. § The DBVT passive indicates tape and reel of 250 parts.
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ordering information
Typical Reset Threshold Voltage Functionality Family DEVICE NAME NOMINAL SUPPLY VOLTAGE, V N(dc) DEVICE NAME TYPICAL RESET THRESHOLD VOLTAGE, VIT TPS310xx09DBV TPS311xx09DBV 0.9 V TPS310XEXXDBV TPS311XEXXDBV VN(dc) − 5% TPS310xx12DBV TPS311xx12DBV 1.2 V TPS310XHXXDBV VN(dc) − 8% TPS310xx15DBV TPS311xx15DBV 1.5 V TPS310XKXXDBV TPS311XKXXDBV VN(dc) − 11% TPS310xx16DBV 1.6 V TPS310xx20DBV 2 V TPS310xx33DBV- TPS311xx33DBV 3.3 V Function Tables TPS3110 † MR V(SENSE) > 0.551 V VDD > VIT RESET L x x L H 00 L H 01 L H 10 L H 1 1 H † Function of watchdog-timer not shown x = Don’t care TPS3103 MR V(PFI) > 0.551 V VDD > VIT RESET PFO L 0 x L L L 1x L H H 00 L L H 01 H L H 10 L H H 1 1 H H TPS3106 MR V(SENSE) > 0.551 V VDD > VIT RSTVDD RSTSENSE L x x L L H 00 L L H 01 H L H 10 L H H 1 1 H H
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com functional block diagram Reset Logic and Timer VIT− 0.551 V VDD MR PFI GND RESET PFO TPS3103 Reset Logic and Timer 0.551 V VDD MR SENSE GND RSTVDD Reset Logic and Timer RSTSENSE TPS3106 VIT−
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com functional block diagram (continued) + Reset Logic and Timer 0.551 V VDD MR SENSE GND RESET Watchdog Logic and Control WDI TPS3110 VIT−
Figure 1. Timing Diagram for TPS3103
Figure 2. Timing Diagram for TPS3106
Figure 3. Timing Diagram for TPS3110
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME PART NO. I/O DESCRIPTION GND ALL 2 GND MR ALL 3 I Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for the timeout period after MR goes high. Leave unconnected or connect to VDD when unused. PFI TPS3103 4 I Power-fail input compares to 0.551 V with no additional delay. Connect to VDD if not used. PFO TPS3103 5 O Power-fail output. Goes high when voltage at PFI rises above 0.551 V. RESET TPS3103 TPS3110 1 O Active-low reset output. Either push-pull or open-drain output stage RSTSENSE TPS3106 5 O Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and the status of MR. RSTVDD TPS3106 1 O Active-low reset output. Logic level at RSTVDD only depends on the voltage at VDD and the status of MR. SENSE TPS3106 TPS3110 I A reset will be asserted if the voltage at SENSE is lower than 0.551 V. Connect to VDD if unused VDD ALL 6 Supply voltage. Powers the device and monitors its own voltageVDD ALL 6 Supply voltage. Powers the device and monitors its own voltage WDI TPS3110 5 I Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge. detailed description watchdog The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, RESET becomes active for the time period (td). This event also reinitializes the watchdog timer. manual reset (MR) Many µC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (td) after MR returns high. The input has an internal 100-kΩ pull-up resistor, so it can be left open if it is unused. Connect a normally open momentary switch from MR to GND to create a manual reset function. External debounce is not required. If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1-µF capacitor from MR to GND provides additional noise immunity. PFI, PFO The TPS3103 has an integrated power-fail (PFI) comparator with a separate open drain (PFO) output can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply. An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the power-fail threshold (VIT−(S)), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately 15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power consumption and to assure that the current into the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO unconnected. For proper operation of the PFI-comparator the supply voltage (VDD ) must be higher than 0.8 V.
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com SENSE The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls below the sense-threshold (VIT−(S)), reset is asserted. On the TPS3106, a dedicated RSTSENSE output is available. On the TPS3110, the logic signal from SENSE is OR-wired with the logic signal from VDD or MR. An internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above 0.551 V plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply voltage must be higher than 0.8 V. ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED) (1) (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t=1000h continuously. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DBV 437 mW 3.5 mW/°C 280 mW 227 mW recommended operating conditions MIN MAX UNIT Supply voltage, VDD (1) 0.4 3.3 V Input voltage, VI 0 VDD + 0.3 V High-level input voltage, VIH at MR, WDI 0.7 × VDD V Low-level input voltage, VIL at MR, WDI 0.3 × VDD V Input transition rise and fall rate at ∆t/∆V at MR, WDI 100 ns/V Operating free-air temperature range, TA −40 85 °C (1)For proper operation of SENSE, PFI, and WDI functions: VDD ≥ 0.8 V
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT VDD = 3.3 V, IOH = −3 mA VDD = 1.8 V, IOH = −2 mA 0.8 VDDVOH High-level output voltage VDD = 1.5 V, IOH = −1 mA 0.8 × VDD VVOH High-level output voltage VDD = 0.9 V, IOH = −0.4 mA V VDD = 0.5 V, IOH = −5 µA 0.7 × VDD VDD = 3.3 V, IOL = 3 mA Low-level output VDD = 1.5 V, IOL = 2 mA 0.3 VOL Low-level output voltage VDD = 1.2 V, IOL = 1 mA 0.3 VVOL voltage VDD = 0.9 V, IOL = 500 µA V RESET only VDD = 0.4 V, IOL = 5 µA 0.1 TPS31xxE09 0.854 0.86 0.866 TPS31xxE12 1.133 1.142 1.151 VIT− Negative-going input (1) TPS31xxE15 TA = 25°C 1.423 1.434 1.445 VVIT− Negative-going input threshold voltage (1) TPS31xxE16 TA = 25°C 1.512 1.523 1.534 Vthreshold voltage TPS31xxH20 1.829 1.843 1.857 TPS31xxK33 2.919 2.941 2.963 VIT−(S) Negative-going input threshold voltage (1) SENSE, PFI VDD ≥ 0.8 V, TA = 25°C 0.542 0.551 0.559 V 0.8 V ≤ VIT < 1.5 V 20 Vhys Hysteresis at VDD input 1.6 V ≤ VIT < 2.4 V 30 mVVhys Hysteresis at VDD input 2.5 V ≤ VIT < 3.3 V 50 mV T(K) Temperature coefficient of VIT−, PFI, SENSE TA = −40°C to 85°C −0.012 −0.019 %/K Vhys Hysteresis at SENSE, PFI input VDD ≥ 0.8 V 15 mV MR MR = VDD , VDD = 3.3 V −25 25 IIH High-level input currentSENSE, PFI, WDI SENSE, PFI, WDI = VDD , VDD = 3.3 V −25 25 nA IIL Low-level input current MR MR = 0 V, VDD = 3.3 V −47 −33 −25 µA IIL Low-level input currentSENSE, PFI, WDI SENSE, PFI, WDI = 0 V, VDD = 3.3 V −25 25 nA IOH High-level output current at RESET (2) Open drain VDD = VIT + 0.2 V, VOH = 3.3 V 200 nA VDD > VIT (average current), VDD < 1.8 V 1.2 3 IDD Supply current VDD > VIT (average current), VDD > 1.8 V 2 4.5 µADD VDD < VIT, VDD < 1.8 V 22 VDD < VIT, VDD > 1.8 V 27 Internal pull-up resistor at MR 70 100 130 kΩ C i Input capacitance at MR, SENSE, PFI, WDI VI = 0 V to VDD 1 pF (1)To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed close to the supply terminals. (2)Also refers to RSTVDD and RSTSENSE
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com TIMING REQUIREMENTS AT R L = 1 MΩ, CL = 50 PF, TA = −40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tt(out)Time-out periodat WDI VDD ≥ 0.85 V 0.55 1.1 1.65 s at VDD VIH = 1.1 × VIT, VIL = 0.9 × VIT−, VIT− = 0.86 V 20 at MR VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 0.1 tw Pulse width at SENSE VDD ≥ VIT, V IH = 1.1 × VIT−(S), VIL = 0.9 × VIT−(S) 20 µstw Pulse width at PFI VDD ≥ 0.85 V, V IH = 1.1 × VIT−(S),VIL = 0.9 × VIT−(S) 20 µs at WDI VDD ≥ VIT,V IL = 0.3 × VDD, VIH = 0.7 × VDD 0.3 SWITCHING CHARACTERISTICS AT R L = 1 MΩ, CL = 50 PF, TA = −40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Delay time VDD ≥ 1.1 × VIT, MR = 0.7 × VDD , See timing diagram 65 130 195 ms tPHL Propagation delay time, high-to-low level outputVDD to RESET or RSTVDD delay VIH = 1.1 × VIT, VIL = 0.9 × VIT µs tPLH Propagation delay time, low-to-high level outputVDD to RESET or RSTVDD delay VIH = 1.1 × VIT, VIL = 0.9 × VIT µs tPHL Propagation delay time, high-to-low level outputSENSE to RESET or RSTSENSE delay VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT 40 µs tPLH Propagation delay time, high-to-low level outputSENSE to RESET or RSTSENSE delay VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT 40 µs tPHL Propagation delay time, high-to-low level outputPFI to PFO delay VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT 40 µs tPLH Propagation delay time, low-to-high level outputPFI to PFO delay VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT 300 µs tPHL Propagation delay time, low-to-high level output MR to RESET. RSTVDD , RSTSENSE delay VDD ≥ 1.1 × VIT, VIL = 0.3 × VDD , 1 5 s tPLH Propagation delay time, low-to-high level output MR to RESET. RSTVDD, RSTSENSE delay DD IT VIL = 0.3 × VDD , VIH = 0.7 × VDD 1 5 µs
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com
APPLICATION INFORMATION
Px.x Py.x V (neg_th)/C00430.551 V/C0042R2 R1 /C0466V DD /C00420.551 V/C0467 † Resistor may be integrated in µC RESET PFO VDD VDD Low Power µC 2 V −2 V MR Figure 12. TPS3103 Monitoring a Negative Voltage
/C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0069/C0120/C0120/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0072/C0050/C0048/C0044 /C0084/C0080/C0083/C0051/C0049/C0120/C0120/C0075/C0051/C0051 /C0085/C0076/C0084/C0082/C0065/C0076/C0079/C0087 /C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0067/C0085/C0082/C0082/C0069/C0078/C0084/C0047/C0083/C0085/C0080/C0080/C0076/C0089/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0083/C0085/C0080/C0069/C0082/C0086/C0073/C0083/C0079/C0082/C0089 /C0067/C0073/C0082/C0067/C0085/C0073/C0084/C0083 SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004 www.ti.com The TPS310x family has a quiescent current in the 1-µA to 2-µA range. When RESET, triggered by the voltage monitored at VDD , is active, the quiescent current increases to about 20 µA (see electrical characteristics). In some applications it is necessary to minimize the quiescent current even during the reset period. This is especially true when the voltage of a battery is supervised and the RESET is used to shut down the system or for an early warning. In this case the reset condition will last for a longer period of time. Especially when the battery is discharged, the current drawn from the battery should almost be zero. For this kind of applications the TPS3103 or TPS3106 are a good fit. To minimize current consumption it must be assured to select a version where the threshold voltage is lower than the voltage monitored at V DD . The TPS3106 has two reset outputs. One output (RSTVDD) is triggered from the voltage monitored at VDD . The other output (RSTSENSE) is triggered from the voltage monitored at SENSE. In the application shown in Figure 13, the TPS3106E09 is used to monitor the input voltage of two NiCd or NiMH cells. The threshold voltage (V (th) = 0.86 V) was chosen as low as possible to ensure that the supply voltage is always higher than the threshold voltage at VDD . The voltage of the battery is monitored using the SENSE input. The voltage divider was calculated to assert a reset using the RSTSENSE output at 2 x 0.8 V = 1.6 V. R1 /C0043R2 /C0032/C0466V TRIP V IT(S) /C00421/C0467 Where: VTRIP is the voltage of the battery at which a reset is asserted VIT(S) is the threshold voltage at SENSE = 0.551 V. R1 was chosen for a resistor current in the 1-µA range. With VTRIP = 1.6 V: R1 ≈ 1.9× R2 R1 = 820 k, R2 = 430 k TPS3106E09DBV SENSE GND VDD RSTVDD RSTSENSE
2 Cell
Figure 13. Battery Monitoring With 3-µA Supply Current for Device and Resistor Divider
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS3103E12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E12DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E12DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103E15DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103H20DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103H20DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103H20DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103H20DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3103K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E09DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E09DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E09DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E16DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E16DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106E16DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 Addendum-Page 1
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS3106K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3106K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E09DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E09DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E09DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E12DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E12DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110E15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110K33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110K33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110K33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS3110K33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 Addendum-Page 3
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