TPS2011APWP

TPS2010A TI | Alldatasheet

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TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C006833-mW (5-V Input) High-Side MOSFET Switch /C0068Short-Circuit and Thermal Protection /C0068Logic-Level Enable Input /C0068Typical Rise Time. . . 6.1 ms /C0068Undervoltage Lockout /C0068Maximum Standby Supply Current...1 0 mA /C0068No Drain-Source Back-Gate Diode /C0068Available in 8-pin SOIC and 14-Pin TSSOP Packages /C0068Ambient Temperature Range, –40°C to 85°C /C00682-kV Human-Body-Model, 200-V Machine-Model ESD Protection

description

The TPS201xA family of power distribution switches is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. These devices are 50-mW N-channel MOSFET high-side power switches. The switch is controlled by a logic enable compatible with 5-V logic and 3-V logic. Gate drive is provided by an internal charge pump designed to control the power-switch rise times and fall times to minimize current surges during switching. The charge pump requires no external components and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short is present, the TPS201xA limits the output current to a safe level by switching into a constant-current mode. When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch remains off until valid input voltage is present. The TPS201xA devices differ only in short-circuit current threshold. The TPS2010A limits at 0.3-A load, the TPS2011 at 0.9-A load, the TPS2012A at 1.5-A load, and the TPS2013A at 2.2-A load (see Available Options). The TPS201xA is available in an 8-pin small-outline integrated-circuit (SOIC) package and in a 14-pin thin-shrink small-outline package (TSSOP) and operates over a junction temperature range of –40°C to 125°C. TPS201xA TPS202x TPS203x 33 mW , single 0.2 A – 2 A

0.2 A – 2 A

80 mW , single 600 mA 1 A 500 mA 500 mA 250 mA 250 mA GENERAL SWITCH CATALOG TPS2042 TPS2052 TPS2046 TPS2056 80 mW , dual 500 mA 500 mA 250 mA 250 mA TPS2100/1260 mW IN1 500 mA IN2 10 mA OUT IN1 IN2 TPS2102/3/4/5 IN1 500 mA IN2 100 mA 1.3 W TPS2043 TPS2053 TPS2047 TPS2057 80 mW , triple 500 mA 500 mA 250 mA 250 mA TPS2044 TPS2054 TPS2048 TPS2058 80 mW , quad 500 mA 500 mA 250 mA 250 mA Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND IN IN EN OUT OUT OUT OUT D PACKAGE (TOP VIEW) GND IN IN IN IN IN EN OUT OUT OUT OUT OUT OUT OUT PWP PACKAGE (TOP VIEW)

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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MAXIMUM CONTINUOUS TYPICAL SHORT-CIRCUIT PACKAGED DEVICES TA ENABLE MAXIMUM CONTINUOUS LOAD CURRENT (A) CURRENT LIMIT AT 25°C (A) SMALL OUTLINE (D)† TSSOP (PWP) ‡ 0.2 0.3 TPS2010AD TPS2010APWPR 40°Ct o8 5°C Active low 0.6 0.9 TPS2011AD TPS2011APWPR –40°C to 85°C Active low 1 1.5 TPS2012AD TPS2012APWPR 1.5 2.2 TPS2013AD TPS2013APWPR † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR) ‡ The PWP package is only available left-end taped-and-reeled. TPS201xA functional block diagram OUTIN EN GND Current LimitDriver UVLO Charge Pump CS Thermal Sense Power Switch †Current Sense Terminal Functions TERMINAL NAME NO. D NO. PWP I/O DESCRIPTION EN 4 7 I Enable input. Logic low turns on power switch. GND 1 1 I Ground IN 2, 3 2–6 I Input voltage OUT 5, 6, 7, 8 8–14 O Power-switch output

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description power switch The power switch is an N-channel MOSFET with a maximum on-state resistance of 50 mW (VI(IN) = 5 V). Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled. charge pump An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current. driver The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 9-ms range. enable (EN The logic enable disables the power switch, the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 mA when a logic high is present on EN . A logic zero input on EN restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels. current sense A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver, in turn, reduces the gate voltage and drives the power FET into its saturation region, which switches the output into a constant current mode and holds the current constant while varying the voltage on the load. thermal sense An internal thermal-sense circuit shuts off the power switch when the junction temperature rises to approximately 140°C. Hysteresis is built into the thermal sense circuit. After the device has cooled approximately 20°C, the switch turns back on. The switch continues to cycle off and on until the fault is removed. undervoltage lockout A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control signal turns off the power switch.

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW PWP 700 mW 5.6 mW/°C 448 mW 364 mW recommended operating conditions MIN MAX UNIT Input voltage VI(IN) 2.7 5.5 V Input voltage VI(EN) 0 5.5 V TPS2010A 0 0.2 Continuous output current IO TPS2011A 0 0.6 AContinuous output current, IO TPS2012A 0 1 A TPS2013A 0 1.5 Operating virtual junction temperature, TJ –40 125 °C

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted) power switch PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT VI(IN) = 5 V, TJ = 25°C, IO = 1.5 A 33 36 VI(IN) = 5 V, TJ = 85°C, IO = 1.5 A 38 46 VI(IN) = 5 V, TJ = 125°C, IO = 1.5 A 44 50 VI(IN) = 3.3 V,TJ = 25°C, IO = 1.5 A 37 41 VI(IN) = 3.3 V,TJ = 85°C, IO = 1.5 A 43 52 rDS(on) Static drain-source on-state resistance VI(IN) = 3.3 V,TJ = 125°C, IO = 1.5 A 51 61 m WrDS(on) Static drain-source on-state resistance VI(IN) = 5 V, TJ = 25°C, IO = 0.18 A 30 34 m W VI(IN) = 5 V, TJ = 85°C, IO = 0.18 A 35 41 VI(IN) = 5 V, TJ = 125°C, IO = 0.18 A 39 47 VI(IN) = 3.3 V,TJ = 25°C, IO = 0.18 A 33 37 VI(IN) = 3.3 V,TJ = 85°C, IO = 0.18 A 39 46 VI(IN) = 3.3 V,TJ = 125°C, IO = 0.18 A 44 56 t Rise time output VI(IN) = 5.5 V, C L = 1 mF, TJ = 25°C, R L = 10 W 6.1 mstr Rise time, output VI(IN) = 2.7 V, C L = 1 mF, TJ = 25°C, R L = 10 W 8.6 ms tf Fall time output VI(IN) = 5.5 V, C L = 1 mF, TJ = 25°C, R L = 10 W 3.4 mstf Fall time, output VI(IN) = 2.7 V, C L = 1 mF, TJ = 25°C, R L = 10 W 3 ms † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. enable input (EN) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage 2.7 V ≤ VI(IN) ≤ 5.5 V 2 V VIL Low-level input voltage VVIL Low -level in ut voltage V II Input current EN = 0 V or EN = VI(IN) –0.5 0.5 mA ton Turnon time C L = 100 mF, RL = 10 W 20 ms toff Turnoff time C L = 100 mF, RL = 10 W 40 ms current limit PARAMETER TEST CONDITIONS † MIN TYP MAX UNIT TPS2010A 0.22 0.3 0.4 IOS Short circuit output current TJ = 25°C, VI = 5.5 V, OUT connected to GND TPS2011A 0.66 0.9 1.1 AIOS Short-circuit output current OUT connected to GND , D evice enable into short circuit TPS2012A 1.1 1.5 1.8 A Device enable into short circuit TPS2013A 1.65 2.2 2.7 † Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted) (continued) supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply current low level output No Load on OUT TJ = 25°C 0.3 1 mASupply current, low-level output No Load on OUT EN = VI(IN) –40°C ≤ TJ ≤ 125°C 10 mA Supply current high level output No Load on OUT EN 0V TJ = 25°C 58 75 mASupply current, high-level output No Load on OUT EN = 0 V –40°C ≤ TJ ≤ 125°C 75 100 mA Leakage current OUT connected to groundEN = VI(IN) –40°C ≤ TJ ≤ 125°C 10 mA undervoltage lockout PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-level input voltage 2 2.5 V Hysteresis TJ = 25°C 100 mV

Figure 1. Test Circuit and Voltage Waveforms

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Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time Figure 4. Turnon Delay and Rise Time Figure 5. Turnoff Delay and Fall Time

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Figure 10. TPS2013A, Ramped Load on Figure 11. TPS2013A, Inrush Current Figure 12. 7.9-W Load Connected to an Enabled Figure 13. 3.7-W Load Connected to an Enabled

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Figure 18. 1.2-W Load Connected to an Enabled Figure 19. 0.9-W Load Connected to an Enabled

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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5.5 0 0.5 1 – Rise Time – ms RISE TIME vs LOAD CURRENT 6.5 1.5 2 IL – Load Current – A tr TA = 25°C C L = 1 mF Figure 23 3.25 2.75 2.5 0 0.5 – Fall Time – ms 3.5 FALL TIME vs LOAD CURRENT 1 1.5 2 IL – Load Current – A tf TA = 25°C C L = 1 mF Figure 24 –50 –25 0 25 50 SUPPLY CURRENT (ENABLED) vs JUNCTION TEMPERATURE 75 100 150 TJ – Junction Temperature – °C Supply Current (Enabled) – Am 125 VI(IN) = 3.3 V VI(IN) = 4 V VI(IN) = 5 V VI(IN) = 5.5 V VI(IN) = 2.7 V Figure 25 –50 –25 0 25 50 SUPPLY CURRENT (DISABLED) vs JUNCTION TEMPERATURE 75 100 150 TJ – Junction Temperature – °C Supply Current (Disabled) – Am 125 VI(IN) = 4 V VI(IN) = 2.7 V VI(IN) = 5 V VI(IN) = 5.5 V VI(IN) = 3.3 V

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Figure 26 2.5 3 3.5 4 4.5 SUPPLY CURRENT (ENABLED) vs INPUT VOLTAGE 5 5.5 6 VI – Input Voltage – V Supply Current (Enabled) – Am TJ = 125°C TJ = 85°C TJ = 25°C TJ = 0°C TJ = –40°C Figure 27 2.5 3 3.5 4 4.5 SUPPLY CURRENT (DISABLED) vs INPUT VOLTAGE 5 5.5 6 VI – Input Voltage – V Supply Current (Disabled) – Am

2 TJ = 85°C

TJ = 0°C TJ = –40°C TJ = 125°C TJ = 25°C SHORT-CIRCUIT CURRENT LIMIT vs INPUT VOLTAGE Figure 28 1.5 0.5 23 4 2.5 3.5 VI – Input Voltage – V – Short-Circuit Current Limit – AIOS TPS2013A TPS2012A TPS2011A TPS2010A TA = 25°C Figure 29 SHORT-CIRCUIT CURRENT LIMIT vs JUNCTION TEMPERATURE 1.5 0.5 –50 –25 0 2.5 3.5 25 100 TJ – Junction Temperature – °C – Short-Circuit Current Limit – AIOS TPS2013A TPS2012A TPS2011A TPS2010A 50 75

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 2.5 3 3.5 VI – Input Voltage – V 4.5 5 WrDS(on) – Static Drain-Source On-State Resistance – m 5.5 TJ = 25°C TJ = 125°C TJ = –40°C IO = 0.18 A Figure 31 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE –50 –25 0 25 150 TJ – Junction Temperature – °C VI = 2.7 V 50 75 100 125 VI = 3.3 V VI = 5.5 V IO = 0.18 A WrDS(on) – Static Drain-Source On-State Resistance – m STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs INPUT VOLTAGE 3 3.5 VI – Input Voltage – V 4.5 5 5.5 TJ = 25°C TJ = 125°C Figure 32 IO = 1.5 A TJ = –40°C WrDS(on) – Static Drain-Source On-State Resistance – m Figure 33 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE –50 –25 0 25 150 TJ – Junction Temperature – °C VI = 3.3 V 50 75 100 125 VI = 4 V VI = 5.5 V IO = 1.5 A WrDS(on) – Static Drain-Source On-State Resistance – m

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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APPLICATION INFORMATION

overcurrent (continued) Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before VI(IN) has been applied (see Figure 6). The TPS201xA senses the short and immediately switches into a constant-current output. In the second condition, the excessive load occurs while the device is enabled. At the instant the excessive load occurs, very high currents may flow for a short time before the current-limit circuit can react (see Figures 12–19). After the current-limit circuit has tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode. In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded (see Figures 7–10). The TPS201xA is capable of delivering current up to the current-limit threshold without damaging the device. Once the threshold has been reached, the device switches into its constant-current mode. power dissipation and junction temperature The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass large currents. The thermal resistances of these packages are high compared to those of power packages; it is good design practice to check power dissipation and junction temperature. The first step is to find r DS(on) at the input voltage and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and read r DS(on) from Figures 30–33. Next, calculate the power dissipation using: P D /C0043rDS (on)/C0032I2 Finally, calculate the junction temperature: TJ /C0043P D /C0032R /C0113JA /C0041TA Where: TA = Ambient Temperature °C R qJA = Thermal resistance SOIC = 172°C/W Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees, repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally sufficient to get an acceptable answer. thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS201xA into constant current mode, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle in this manner until the load fault or input power is removed.

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 undervoltage lockout (UVLO) An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI and voltage overshoots. generic hot-plug applications (see Figure 36) In many applications it may be necessary to remove modules or pc boards while the main unit is still operating. These are considered hot-plug applications. Such implementations require the control of current surges seen by the main power supply and the card being inserted. The most effective way to control these surges is to limit and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply normally turns on. Because of the controlled rise times and fall times of the TPS201xA series, these devices can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS201xA also ensures the switch will be off after the card has been removed, and the switch will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every insertion of the card or module. Power Supply Block of Circuitry TPS2013A GND IN IN EN OUT OUT OUT OUT 0.1 mF1000 mF Optimum 2.7 V to 5.5 V PC Board Figure 36. Typical Hot-Plug Implementation hot-plugging mechanism for any device.

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999

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D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

TPS2010A, TPS2011A, TPS2012A, TPS2013A POWER-DISTRIBUTION SWITCHES SLVS189A – DECEMBER 1998 – REVISED NOVEMBER 1999 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PWP (R-PDSO-G) PowerPAD  PLASTIC SMALL-OUTLINE PACKAGE 4073225/E 03/97 0,50 0,75 0,25 0,15 NOM Thermal Pad (See Note D) Gage Plane 2824 7,70 7,90 6,40 6,60 9,60 9,80 6,60 6,20 0,19 4,50 4,30 0,15 A 0,30 1,20 MAX 1614 5,10 4,90 PINS 4,90 5,10 DIM A MIN A MAX 0,05 Seating Plane 0,65 0,10 M0,10 0°–8° 20-PIN SHOWN NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments Incorporated.

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