TPS2002CDRCTG4.B

TPS2052C TI | Alldatasheet

Document overview

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Technical content

0.1 F/c109

150 F x 2/c109

Sample & Buy T echnical Documents Tools & Software Support & Community TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 TPS20xxC,TPS20xxC-2DualChannel,Current-Limited,Power-DistributionSwitches

1 Features 3 Description

The TPS20xxC and TPS20xxC-2 dual power- 1• Dual Power Switch Family distribution switch family is intended for applications• Rated Currents of 0.5 A, 1 A, 1.5 A, 2 A such as USB where heavy capacitive loads and

• Accurate ±20% Current Limit Tolerance short-circuits may be encountered. This family offers multiple devices with fixed current-limit thresholds for• Fast Overcurrent Response – 2 µs (Typical) applications between 0.5 A and 2 A.• 70-mΩ (Typical) High-Side N-Channel MOSFET The TPS20xxC and TPS20xxC-2 dual family limits• Operating Range: 4.5 V to 5.5 V the output current to a safe level by operating in a• Deglitched Fault Reporting (FLTx) constant-current mode when the output load exceeds
• Selected Parts With (TPS20xxC) and Without the current-limit threshold. This provides a predictable (TPS20xxC-2) Output Discharge fault current under all conditions. The fast overcurrent response time eases the burden on the main 5 V• Reverse Current Blocking supply to provide regulated power when the output is• Built-in Softstart shorted. The power-switch rise and fall times are
• Pin for Pin With Existing TI Switch Portfolio controlled to minimize current surges during turnon and turnoff.• Ambient Temperature Range: –40°C to 85°C Device Information(1)

2 Applications

PART NUMBER PACKAGE BODY SIZE (NOM)• USB Ports or Hubs, Laptops, Desktops TPS2052C• High-Definition Digital TVs TPS2062C TPS2066C• Set Top Boxes TPS2066C-2 MSOP (8) 3.00 mm × 3.00 mm

• Short Circuit Protection TPS2060C TPS2064C TPS2064C-2 TPS2062C SOIC (8) 3.90 mm × 4.90 mmTPS2066C TPS2062C-2 SON (8) 3.00 mm × 3.00 mm TPS2002C VSON (10) 3.00 mm × 3.00 mmTPS2003C (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (January 2013) to Revision H Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision F (November 2012) to Revision G Page Changes from Revision E (August 2012) to Revision F Page
• Changed Feature from: Output Discharge When Disabled to: Selected parts with (TPS20xxC) and without
• Added TPS2052C, TPS2062C-2, TPS2064C-2, and TPS2066C-2 devices to RECOMMENDED OPERATING

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Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C www.ti.com SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 Changes from Revision D (July 2012) to Revision E Page Changes from Revision C (June 2012) to Revision D Page Changes from Revision B (March 2012) to Revision C Page Changes from Revision A (March 2012) to Revision B Page Changes from Original (October 2011) to Revision A Page Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

5 Device Comparison Table

Table 1. Devices Table 2. Device Information

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TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C www.ti.com SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015

6 Pin Configuration and Functions

TYPE(1) DESCRIPTION NAME MSOP SOIC VSON SON GND 1 1 1 1 GND Ground connection Input voltage and power-switch drain; connect a 0.1 µF or greaterIN 2 2 2, 3 2 I ceramic capacitor from IN to GND close to the IC 3(2) 3(3) 4(4) — EN1 I Enable input channel 1, logic high turns on power switch –(5) –(6) –(7) — –(2) –(3) –(4) EN1 3 I Enable input channel 1, logic low turns on power switch 3(5) 3(6) 4(7) 4(2) 4(3) 5(4) — EN2 I Enable input channel 2, logic high turns on power switch –(5) –(6) –(7) — –(2) –(3) –(4) EN2 4 I Enable input channel 2, logic low turns on power switch 4(5) 4(6) 5(7) Active-low open-drain output, asserted during overcurrent, orFLT2 5 5 6 5 O overtemperature conditions on channel 2 NC — — 7 — O No connect – leave floating OUT2 6 6 8 6 O Power-switch output channel 2, connected to load OUT1 7 7 9 7 O Power-switch output channel 1, connected to load Active-low open-drain output, asserted during over-current, orFLT1 8 8 10 8 O overtemperature conditions on channel 1 Internally connected to GND; used to heat-sink the part to thePowerPAD™ PAD — PAD — GND circuit board traces. Connect PAD to GND plane as a heatsink. (1) I = Input, O = Output, GND = Ground (2) Applies to TPS2052C, TPS2066C, TPS2066C-2, TPS2064C, and TPS2064C-2 (3) Applies to TPS2066C (4) Applies to TPS2003C (5) Applies to TPS2062C and TPS2060C (6) Applies to TPS2062C (7) Applies to TPS2002C Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) MIN MAX UNIT Voltage range on IN, OUTx, ENx or ENx, FLTx(4) –0.3 6 V Voltage range from IN to OUT –6 6 V Maximum junction temperature, TJ Internally limited °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Absolute maximum ratings apply over recommended junction temperature range. (3) All voltages are with respect to GND unless otherwise noted. (4) See Input and Output Capacitance.

7.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V(ESD) Electrostatic discharge IEC 61000-4-2, contact discharge(3) ±8000 V IEC 61000-4-2, air-gap discharge(3) ±15000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) VOUT was surged on a PCB with input and output bypassing per Figure 22 (except input capacitor was 22 µF) with no device failure.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage, IN 4.5 5.5 V VEnable Input voltage, ENx or ENx 0 5.5 TPS2052C 0.5 TPS2062C, TPS2062C-2, TPS2066C, 1and TPS2066C-2IOUTx Continuous output current, OUTx A TPS2060C, TPS2064C, and TPS2064C-2 1.5 TPS2002C and TPS2003C 2 TJ Operating junction temperature –40 125 °C IFLTx Sink current into FLTx 0 5 mA

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Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C www.ti.com SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015

7.4 Thermal Information

TPS2066C TPS2062C TPS2002CTPS2066C-2 TPS2062C-2TPS2066C TPS2003CTPS2060CTHERMAL METRIC(1)(2) UNITTPS2064C TPS2064C-2 DGN (MSOP) D (SOIC) DRB (SON) DRC (VSON)

8 PINS 8 PINS 8 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 57.2 129.9 50.8 45.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 110.5 83.5 60.3 58 °C/W RθJB Junction-to-board thermal resistance 60.7 70.4 26.3 21.1 °C/W ψJT Junction-to-top characterization parameter 7.8 36.6 2.1 1.9 °C/W ψJB Junction-to-board characterization parameter 24 66.9 26.5 21.3 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 14.3 n/a 9.8 9.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). (2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

7.5 Electrical Characteristics: TJ = TA = 25°C

VIN = 5 V, VENx = VIN or VENx = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT POWER SWITCH TPS2052C (0.5 A) DGN 70 84 TPS2052C (0.5 A) DGN 70 95–40°C ≤ (TJ, TA) ≤ 85°C TPS2062C, 66C, and 66C-2 (1 A) DGN 70 84 TPS2062C, 66C, and 66C-2 (1 A), DGN 70 95–40°C ≤ (TJ, TA) ≤ 85°C TPS2062C and 66C (1 A) D 90 108 TPS2062C and 66C (1 A) D 90 122–40°C ≤ (TJ, TA) ≤ 85°C rDS(on) On-resistance mΩ TPS2062C-2 (1 A) DRB 73 87 TPS2062C-2 (1 A) DRB 73 101–40°C ≤ (TJ, TA) ≤ 85°C TPS2060C, 64C, and 64C-2 (1.5 A) 70 84 TPS2060C, 64C, and 64C-2 (1.5 A) 70 95–40°C ≤ (TJ, TA) ≤ 85°C TPS2002C and 03C (2 A) 70 84 TPS2002C and 03C (2 A) 70 95–40°C ≤ (TJ, TA) ≤ 85°C CURRENT LIMIT TPS2052C (0.5 A) 0.75 1 1.25 TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.28 1.61 1.94 IOS Current-limit (see Figure 28) A TPS2060C, 64C, and 64C-2 (1.5 A) 1.83 2.29 2.75 TPS2002C and 03C (2 A) 2.55 3.15 3.77 SUPPLY CURRENT ISD Supply current, switch disabled I(OUTx) = 0 mA 0.01 1 IS1E Supply current, single switch enabled I(OUTx) = 0 mA 60 75 IS2E Supply current, both switches enabled I(OUTx) = 0 mA 100 120 µA VOUT = 0 V, VIN = 5.5 V, disabled,Leakage current TPS20xxC-2 0.05 1measured IVINILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.15 1 (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 www.ti.com Electrical Characteristics: TJ = TA = 25°C (continued) VIN = 5 V, VENx = VIN or VENx = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT OUTPUT DISCHARGE RPD Output pulldown resistance(2) VIN = VOUTx = 5 V, disabled TPS20xxC 400 470 600 Ω (2) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.

7.6 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C(1)

4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT POWER SWITCH TPS2052C (0.5 A) DGN 70 112 TPS2062C, 66C, and 66C-2 (1 A) DGN 70 112 TPS2062C and 66C (1 A) D 90 135 rDS(on) On-resistance mΩ TPS2062C-2 (1 A) DRB 73 115 TPS2060C, 64C, and 64C-2 (1.5 A) DGN 70 112 TPS2002C and 03C (2 A) DRC 70 112 ENABLE INPUT (ENx or ENx) VIH ENx (ENx), High-level input voltage 4.5 V ≤ VIN ≤ 5.5 V 2 VIL ENx (ENx), Low-level input Voltage 0.8 V Hysteresis VIN = 5 V 0.14 Leakage current VENx = 5.5 V or 0 V, VENx = 0 V or 5.5 V –1 0 1 µA VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or ENx ↓ ton Turnon time (3) (see Figure 25, Figure 26, and Figure 23) 1.4 1.9 2.4 ms 1 A, 1.5 A, 2 A Rated VIN = 5 V, CL = 1 µF, RL = 100 Ω, ENx ↑ or EN ↓ toff Turnoff time (3) (see Figure 25, Figure 26, and Figure 23) 1.95 2.60 3.25 ms 1 A, 1.5 A, 2 A Rated CL = 1 µF, RL = 100 Ω (see Figure 24)tr Rise time, output (3) 0.58 0.82 1.15 ms1 A, 1.5 A, 2 A Rated CL = 1 µF, RL = 100 Ω (see Figure 24)tf Fall time, output (3) 0.33 0.47 0.66 ms1 A, 1.5 A, 2 A Rated CURRENT LIMIT TPS2052C (0.5 A) 0.7 1 1.3 TPS2062C, 62C-2, 66C, and 66C-2 (1 A) 1.12 1.61 2.10 IOS Current-limit (see Figure 28) A TPS2060C, 64C, and 64C-2 (1.5 A) 1.72 2.29 2.86 TPS2002C and 03C (2 A) 2.35 3.15 3.95 VIN = 5 V (see Figure 27), One-half full load → R(SHORT) = 50 mΩ, Measure fromtIOS Short-circuit response time 2 µsapplication to when current falls below 120% of final value SUPPLY CURRENT ISD Supply current, switch disabled Standard conditions, I(OUTx) = 0 mA 0.01 10 IS1E Supply current, single switch enabled Standard conditions, I(OUTx) = 0 mA 90 IS2E Supply current, both switches enabled Standard conditions, I(OUTx) = 0 mA 150 µA VOUT = 0 V, VIN = 5.5 V, disabled,Leakage current TPS20xxC-2 0.05measured IVINILKG Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measured I(OUTx) 0.20 UNDERVOLTAGE LOCKOUT UVLO Low-level input voltage, IN VIN rising 3.4 4.0 V Hysteresis, IN 0.14 V (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature. (2) Typical values are at 5 V and 25°C. (3) These parameters are provided for reference only, and do not constitute part of TI’s published device specifications for purposes of TI’s product warranty.

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Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C www.ti.com SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 Electrical Characteristics: –40°C ≤ (TJ = TA) ≤ 125°C(1) (continued) 4.5 V ≤ VIN ≤ 5.5 V, VENx = VIN or VENx = 0 V, IOUTx = 0 A (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX UNIT FLTx Output low voltage, FLTx I(FLTx) = 1 mA 0.2 V Off-state leakage V(FLTx) = 5.5 V 1 µA FLTx deglitch (3) FLTx overcurrent assertion and deassertion 7 10 13 ms OUTPUT DISCHARGE VIN = 5 V, VOUT = 5 V, disabled TPS20xxC 300 470 800 Output pulldown resistance(3) Ω VIN = 4 V, VOUT = 5 V, disabled TPS20xxC 350 560 1200 THERMAL SHUTDOWN In current limit 135 Junction thermal shutdown threshold °C Not in current limit 155 Hysteresis 20 °C Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

7.7 Typical Characteristics

Figure 1. TPS2062C Turnon Delay and Figure 2. TPS2062C Turnoff Delay and Figure 3. TPS2062C Turnon Delay and Figure 4. TPS2062C Turnoff Delay and Figure 5. TPS2062C Enable Into Short Figure 6. TPS2062C In-rush Current

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2.0 A rated

1.0 A rated

1.5 A rated

Figure 13. TPS2064C Enable into Short Figure 14. TPS2064C Enable into 3.3 Ω and 150-μF Laod Figure 15. TPS2064C Short Applied Figure 16. TPS2003C Enable into Short Figure 17. TPS2003C Enable into 2.5 Ω and 150-μF Load Figure 18. Current Limit (IOS) vs Temperature

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2.0 A rated/c40IS1E/c41

1.0 A rated/c40IS1E/c41

2.0 A rated/c40IS2E/c41

1.0 A rated/c40IS2E/c41

1.5 A rated/c40IS1E/c41

1.5 A rated/c40IS2E/c41

1 A rated

2 A rated

Figure 19. Input - output Resistance (RDS(ON)) Figure 20. Supply Current (Device Disable) - ISD Figure 21. Supply Current (Enable) - ISE vs Temperature

8 Parameter Measurement Information

Figure 22. Test Circuit for System Operation for the Typical Characteristics Figure 23. Output Rise / Fall Test Load Figure 24. Power-On and Off Timing Figure 25. Enable Timing, Active High Enable Figure 26. Enable Timing, Active Low Enable Figure 27. Output Short Circuit Parameters

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Figure 28. Output Characteristic

9 Detailed Description

9.1 Overview

and deglitched fault reporting. They are pin for pin with existing TI Switch Portfolio.

9.2 Functional Block Diagram

Figure 29. TPS20xxC Functional Block Diagram

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Figure 30. TPS20xxC-2 Functional Block Diagram

9.3 Feature Description

9.3.1 Undervoltage Lockout (UVLO)

surges. FLTx is high impedance when the TPS20xxC and TPS20xxC-2 dual are in UVLO.

9.3.2 Enable (ENx or ENx)

cleared and the output discharge circuit is enabled when the device is disabled.

9.3.3 Deglitched Fault Reporting

another channel continues to operate when one channel is in a fault condition.

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 www.ti.com Feature Description (continued)

9.3.4 Overcurrent Protection

The TPS20xxC and TPS20xxC-2 dual responds to overloads by limiting each channel output current to the static IOS levels shown in Electrical Characteristics: TJ = TA = 25°C. When an overload condition is present, the device maintains a constant current (IOS) and reduces the output voltage accordingly, with the output voltage falling to (IOS × RSHORT). Three possible overload conditions can occur. In the first condition, the output has been shorted before the device is enabled or before voltage is applied to IN. The device senses over-current and immediately switches into a constant-current output. In the second condition, a short or an overload occurs while the device is enabled. At the instant a short-circuit occurs, high currents may flow for several microseconds (tIOS) before the current-limit circuit reacts. The device operates in constant-current mode after the current-limit circuit has responded. In the third condition, the load is increased gradually beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached. The devices are capable of delivering current up to the current-limit threshold without damage. Once the threshold is reached, the device switches into constant-current mode. For all of the above three conditions, the device may begin thermal cycling if the overcurrent condition persists.

9.3.5 Overtemperature Protection

The TPS20xxC and TPS20xxC-2 dual includes per channel overtemperature protection circuitry, which activates at 135°C (minimum) junction temperature while in current limit. There is an overall thermal shutdown of 155°C (minimum) junction temperature when the TPS20xxC and TPS20xxC-2 dual are not in current limit. The device remains off until the junction temperature cools 20°C and then restarts. Thermal shutdown may occur during an overload due to the relatively large power dissipation [(VIN – VOUT) × IOS] driving the junction temperature up. The power switch cycles on and off until the fault is removed. This topology allows one channel to continue normal operation even if the other channel is in an overtemperature condition.

9.3.6 Softstart, Reverse Blocking and Discharge Output

The power MOSFET driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The TPS20xxC and TPS20xxC-2 dual power switch will block current from OUT to IN when turned off by the UVLO or disabled. The TPS20xxC dual includes an output discharge function on each channel. A 470 Ω (typical) discharge resistor will dissipate stored charge and leakage current on OUTx when the device is in UVLO or disabled. However as this circuit is biased from IN, the output discharge will not be active when IN voltage is close to 0 V. The TPS20xxC-2 does not have this function. The output is be controlled by an external loadings when the device is in ULVO or disabled.

9.4 Device Functional Modes

There are no other functional modes.

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Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

validate and test their design implementation to confirm system functionality.

10.1 Application Information

differential data, and two lines are provided for 5-V power distribution. from the 5-V input or its own internal power supply.

• Hosts or self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS20xxC and TPS20xxC-2 can provide power distribution solutions to many of these device classes.

10.2 Typical Application

Figure 31. Typical Application Circuit

10.2.1 Design Requirements

Table 3 shows the design requirements for the typical application. Table 3. Design Parameters

10.2.2 Detailed Design Procedure

10.2.2.1 Input and Output Capacitance

device during heavy transients.

10.2.3 Application Curves

Figure 33. TPS2062C Enable/Disable into 10-Ω LoadFigure 32. TPS2062C Turnon Delay and

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11 Power Supply Recommendations

11.1 Self-Powered and Bus-Powered Hubs

A Self-Powered Hub (SPH) has a local power supply that powers embedded functions and downstream ports. Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs. function, and it is limited to 500 mA from an upstream port.

11.2 Low-Power Bus-Powered and High-Power Bus-Powered Functions

44 Ω and 10 µF at power up, the device must implement inrush current limiting.

12 Layout

12.1 Layout Guidelines

• Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low- inductance trace.
• When large transient currents are expected on the output, TI recommends placing a high-value electrolytic capacitor and a 100-nF bypass capacitor on the output pin.
• The PowerPAD should be directly connected to PCB ground plane using wide and short copper trace.

12.2 Layout Example

Figure 34. Layout Recommendation

TPS2052C,TPS2062C,TPS2062C-2,TPS2066C,TPS2066C-2 TPS2060C,TPS2064C,TPS2064C-2,TPS2002C,TPS2003C SLVSAX6H –OCTOBER 2011–REVISED DECEMBER 2015 www.ti.com

12.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC and TPS20xxC-2 dual. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors such as airflow and maximum ambient temperature are often determined by system considerations. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The following procedure requires iteration because power loss is due to the two internal MOSFETs 2 × I2 × rDS(on), and rDS(on) is a function of the junction temperature. As an initial estimate, use the rDS(on) at 125°C from the typical characteristics, and the preferred package thermal resistance for the preferred board construction from the thermal parameters section. TJ = TA + [2 × IOUT 2 × rDS(on) × θJA] where

• IOUT = rated OUT pin current (A)
• rDS(on) = Power switch on-resistance at an assumed TJ (Ω)
• TA = Maximum ambient temperature (°C)
• TJ = Maximum junction temperature (°C)
• θJA = Thermal resistance (°C/W) (1) If the calculated TJ is substantially different from the original assumption, look up a new value of rDS(on) and recalculate. If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.

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Product Folder Links: TPS2052C TPS2062C TPS2062C-2 TPS2066C TPS2066C-2 TPS2060C TPS2064C TPS2064C-2 TPS2002C TPS2003C

13 Device and Documentation Support

13.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 4. Related Links

13.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.3 Trademarks

PowerPad, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 31-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS2002CDRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCR.A Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCR.B Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCT Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCT.A Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCT.B Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCTG4 Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCTG4.A Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2002CDRCTG4.B Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 VFEQ TPS2003CDRCR Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCR.A Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCR.B Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCRG4 Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCRG4.A Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCRG4.B Active Production VSON (DRC) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCT Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCT.A Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2003CDRCT.B Active Production VSON (DRC) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 VRFQ TPS2052CDGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2052CDGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2052CDGN.B Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2052CDGNR Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2052CDGNR.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2052CDGNR.B Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYNI TPS2060CDGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ TPS2060CDGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ TPS2060CDGN.B Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ TPS2060CDGNR Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ TPS2060CDGNR.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ Addendum-Page 1

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS2060CDGNR.B Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRAQ TPS2062CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2062C TPS2062CD.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2062C TPS2062CDGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ TPS2062CDGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ TPS2062CDGNR Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ TPS2062CDGNR.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRBQ TPS2062CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2062C TPS2062CDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2062C TPS2062CDRBR-2 Active Production SON (DRB) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI TPS2062CDRBR-2.A Active Production SON (DRB) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI TPS2062CDRBT-2 Active Production SON (DRB) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI TPS2062CDRBT-2.A Active Production SON (DRB) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 PYVI TPS2064CDGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2064CDGN-2 Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI TPS2064CDGN-2.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI TPS2064CDGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2064CDGN.B Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2064CDGNR Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2064CDGNR-2 Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI TPS2064CDGNR-2.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYTI TPS2064CDGNR.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2064CDGNR.B Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRCQ TPS2066CD Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C TPS2066CD.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C TPS2066CDG4 Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C TPS2066CDG4.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C TPS2066CDGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 VRDQ TPS2066CDGN-2 Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI TPS2066CDGN-2.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI TPS2066CDGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 VRDQ Addendum-Page 2

www.ti.com 31-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS2066CDGN.B Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAUAG Level-1-260C-UNLIM -40 to 85 VRDQ TPS2066CDGNR Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRDQ TPS2066CDGNR-2 Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI TPS2066CDGNR-2.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 PYUI TPS2066CDGNR.A Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRDQ TPS2066CDGNR.B Active Production HVSSOP (DGN) | 8 2500 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 VRDQ TPS2066CDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C TPS2066CDR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2066C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

www.ti.com 31-Oct-2025 Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2002CDRCR VSON DRC 10 3000 346.0 346.0 33.0 TPS2002CDRCT VSON DRC 10 250 210.0 185.0 35.0 TPS2002CDRCTG4 VSON DRC 10 250 210.0 185.0 35.0 TPS2003CDRCR VSON DRC 10 3000 346.0 346.0 33.0 TPS2003CDRCRG4 VSON DRC 10 3000 346.0 346.0 33.0 TPS2003CDRCT VSON DRC 10 250 182.0 182.0 20.0 TPS2052CDGNR HVSSOP DGN 8 2500 366.0 364.0 50.0 TPS2060CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 TPS2062CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 TPS2062CDR SOIC D 8 2500 340.5 338.1 20.6 TPS2062CDRBR-2 SON DRB 8 3000 335.0 335.0 25.0 TPS2062CDRBT-2 SON DRB 8 250 182.0 182.0 20.0 TPS2064CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 TPS2064CDGNR-2 HVSSOP DGN 8 2500 366.0 364.0 50.0 TPS2066CDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 TPS2066CDGNR-2 HVSSOP DGN 8 2500 366.0 364.0 50.0 TPS2066CDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS2052CDGN DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2052CDGN.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2052CDGN.B DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2060CDGN DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2060CDGN.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2060CDGN.B DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2062CD D SOIC 8 75 507 8 3940 4.32 TPS2062CD.B D SOIC 8 75 507 8 3940 4.32 TPS2062CDGN DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2062CDGN.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2064CDGN DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2064CDGN-2 DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2064CDGN-2.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2064CDGN.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2064CDGN.B DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2066CD D SOIC 8 75 507 8 3940 4.32 TPS2066CD.B D SOIC 8 75 507 8 3940 4.32 TPS2066CDG4 D SOIC 8 75 507 8 3940 4.32 TPS2066CDG4.B D SOIC 8 75 507 8 3940 4.32 TPS2066CDGN DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2066CDGN-2 DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2066CDGN-2.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2066CDGN.A DGN HVSSOP 8 80 330 6.55 500 2.88 TPS2066CDGN.B DGN HVSSOP 8 80 330 6.55 500 2.88 Pack Materials-Page 4

www.ti.com PACKAGE OUTLINE C 8X 0.37 0.25 1.75 0.1 1.95 1.5 0.1 6X 0.65

1 MAX

8X 0.5 0.3 0.05 0.00 (0.65) A 3.1 2.9 B 3.1 2.9 (DIM A) TYP 4X (0.23) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 DIM A OPT 1 OPT 2 (0.1) (0.2) PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.31) (1.75) (2.8) 6X (0.65) (1.5) ( 0.2) VIA TYP (0.5) (0.625) 8X (0.6) (R0.05) TYP (0.825) (0.23) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.31) 8X (0.6) (1.34) (1.55) (2.8) 6X (0.65) (0.725) 4X (0.23) (2.674) (0.65) VSON - 1 mm max heightDRB0008A PLASTIC SMALL OUTLINE - NO LEAD 4218875/A 01/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 4 5 METAL TYP SYMM

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. PowerPAD HVSSOP - 1.1 mm max heightDGN 8 SMALL OUTLINE PACKAGE3 x 3, 0.65 mm pitch 4225482/B TM

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 1.846 1.646 2.15 1.95 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 PowerPAD HVSSOP - 1.1 mm max heightDGN0008G SMALL OUTLINE PACKAGE 4225480/C 11/2024

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. TM A 20 DETAIL A TYPICAL SCALE 4.000 EXPOSED THERMAL PAD

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP (2) NOTE 9 (3) NOTE 9 (1.22) (0.55) ( 0.2) TYP VIA (1.57) (1.89) PowerPAD HVSSOP - 1.1 mm max heightDGN0008G SMALL OUTLINE PACKAGE 4225480/C 11/2024 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SOLDER MASK DEFINED PAD METAL COVERED BY SOLDER MASK SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP (1.57) BASED ON

0.125 THICK

(1.89) BASED ON PowerPAD HVSSOP - 1.1 mm max heightDGN0008G SMALL OUTLINE PACKAGE 4225480/C 11/2024 1.33 X 1.600.175 1.43 X 1.730.15 1.57 X 1.89 (SHOWN)0.125 1.76 X 2.110.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X SYMM SYMM 4 5 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VSON - 1 mm max heightDRC 10 PLASTIC SMALL OUTLINE - NO LEAD3 x 3, 0.5 mm pitch 4226193/A

www.ti.com PACKAGE OUTLINE C 10X 0.30 0.18 2.4 0.1 1.65 0.1 8X 0.5 1.0 0.8 10X 0.5 0.3 0.05 0.00 A 3.1 2.9 B 3.1 2.9 (0.2) TYP 4X (0.25) 2X (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C THERMAL PAD EXPOSED SYMM SYMM11 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND0.07 MAX ALL AROUND 10X (0.24) (2.4) (2.8) 8X (0.5) (1.65) ( 0.2) VIA TYP (0.575) (0.95) 10X (0.6) (R0.05) TYP (3.4) (0.25) (0.5) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 SYMM 5 6 LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X SYMM NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 10X (0.24) 10X (0.6) 2X (1.5) (1.06) (2.8) (0.63) 8X (0.5) (0.5) 4X (0.34) 4X (0.25) (1.53) VSON - 1 mm max heightDRC0010J PLASTIC SMALL OUTLINE - NO LEAD 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X SYMM 5 6 EXPOSED METAL TYP11 SYMM

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