TPS2001DDBVT

TPS2001D_17 TI1 | Alldatasheet

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0.1 /c109F 150 /c109F Fault Signal VOUT EN Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS2001D SLVSE25A – JULY 2017– REVISED OCTOBER 2017 TPS2001DCurrentLimited,Power-DistributionSwitches

1 Features

1• Single Power Switch Family

• Rated Current of 2 A
• ±20% Accurate, Fixed, Constant Current Limit
• Fast Overcurrent Response: 2 µs
• Deglitched Fault Reporting
• Output Discharge
• Reverse Current Blocking
• Built-In Soft Start
• Ambient Temperature Range: –40°C to 85°C
• UL Listed and CB-File No. E169910

2 Applications

• USB Ports and Hubs, Laptops, and Desktops
• High-Definition Digital TVs
• Set-Top Boxes
• Short-Circuit Protection

3 Description

The TPS2001D power-distribution switch is intended for applications where heavy capacitive loads and short circuits are likely to be encountered, such as USB. The TPS2001D limits the output current to a safe level by operating in a constant-current mode when the output load exceeds the current limit threshold. This provides a predictable fault current under all conditions. The fast overload response time eases the burden on the main 5-V supply to provide regulated power when the output is shorted. The power-switch rise and fall times are controlled to minimize current surges during turnon and turnoff. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS2001D VSSOP (8) 3.00 mm × 3.00 mm SOT-23 (5) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. spacer spacer Typical Application Diagram

SLVSE25A – JULY 2017– REVISED OCTOBER 2017 www.ti.com Product Folder Links: TPS2001D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Table of Contents

12.1 Receiving Notification of Documentation Updates 17

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (July 2017) to Revision A Page

www.ti.com SLVSE25A –JULY 2017– REVISED OCTOBER 2017 Product Folder Links: TPS2001D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

5 Device Comparison Table(1)

CURRENT OUTPUT DISCHARGE ENABLE

2 A Yes High

6 Pin Configuration and Functions

Pin Functions - DGK Package PIN I/O DESCRIPTION NAME NO. EN 4 I Enable input, logic high turns on power switch FLT 5 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions GND 1 — Ground connection IN 2, 3 PWR Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND close to the IC OUT 6, 7, 8 PWR Power-switch output, connect to load Pin Functions - DBV Package PIN I/O DESCRIPTION NAME NO. EN or EN 4 I Enable input, logic high turns on power switch FLT 3 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions GND 2 — Ground connection IN 5 PWR Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND close to the IC OUT 1 PWR Power-switch output, connect to load

SLVSE25A – JULY 2017– REVISED OCTOBER 2017 www.ti.com Product Folder Links: TPS2001D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Absolute maximum ratings apply over recommended junction temperature range. (3) Voltages are with respect to GND unless otherwise noted. (4) See Input and Output Capacitance.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) MIN MAX UNIT Voltage on IN, OUT, EN, FLT (4) –0.3 6 V Voltage from IN to OUT –6 6 V Maximum junction temperature, TJ Internally Limited Storage temperature, Tstg –60 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) VOUT was surged on a PCB with input and output bypassing per the Typical Application Diagram on the first page (except input capacitor was 22 µF) with no device failures.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 IEC 61000-4-2 contact discharge ±8000 IEC 61000-4-2 air-gap discharge(3) ±15000 (1) Some package and current rating may request an ambient temperature derating of 85°C.

7.3 Recommended Operating Conditions

VIN Input voltage, IN 4.5 5.5 V VEN Input voltage, EN 0 5.5 V VIH High-level input voltage, EN DGK 2 V DBV 1.8 VIL Low-level input voltage, EN 0.7 V IOUT Continuous output current, OUT(1) 2 A TJ Operating junction temperature –40 125 °C IFLT Sink current into FLT 0 5 mA (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) TPS2001D TPS2001D UNITDBV (SOT-23) DGK (VSSOP)

5 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 220.4 205.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 89.7 94.3 °C/W RθJB Junction-to-board thermal resistance 46.9 126.9 °C/W ψJT Junction-to-top characterization parameter 5.2 24.7 °C/W ψJB Junction-to-board characterization parameter 46.2 125.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W RθJACustom See Power DIssipation and Junction Temperature 134.9 110.3 °C/W

www.ti.com SLVSE25A –JULY 2017– REVISED OCTOBER 2017 Product Folder Links: TPS2001D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature (3) See Current Limit section for explanation of this parameter. (4) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

7.5 Electrical Characteristics: TJ = TA = 25°C

Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A. See Device Comparison Table(1) for the rated current of each part number. Parametrics over a wider operational range are shown in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C(2). PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT POWER SWITCH RDS(on) Input – output resistance 2-A rated output, 25°C DGK 72 84 mΩ 2-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C DGK 72 98 mΩ 2-A rated output, 25°C DBV 66 77 mΩ 2-A rated output, –40°C ≤ (TJ , TA) ≤ 85°C DBV 66 90 mΩ CURRENT LIMIT IOS (3) Current limit, See Figure 6 2-A rated output 2.35 2.9 3.4 A SUPPLY CURRENT ISD Supply current, switch disabled IOUT = 0 A 0.01 1 µA –40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 2 ISE Supply current, switch enabled IOUT = 0 A 60 70 µA –40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 85 Ilkg Leakage current VOUT = 0 V, VIN = 5 V, disabled, measure IVIN 0.05 1 µA–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 0 V, VIN = 5 V, disabled, measure IVIN IREV Reverse leakage current VOUT = 5 V, VIN = 0 V, measure IVOUT 0.1 1 µA–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure IVOUT OUTPUT DISCHARGE RPD Output pulldown resistance(4) VIN = VOUT = 5 V, disabled 400 470 600 Ω

SLVSE25A – JULY 2017– REVISED OCTOBER 2017 www.ti.com Product Folder Links: TPS2001D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature (2) See Current Limit for explanation of this parameter. (3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

7.6 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C

Unless otherwise noted:4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C. PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT POWER SWITCH RDS(ON) Input – output resistance 2-A rated output DGK 72 112 mΩ 2-A rated output DBV 66 106 mΩ ENABLE INPUT (EN) Threshold Input rising DGK 1 1.45 2 V DBV 1 1.45 1.8 Hysteresis 0.07 0.13 0.2 V Leakage current VEN = 0 V or 5.5 V –1 0 1 µA CURRENT LIMIT IOS (2) Current limit, See Figure 20 2-A rated output 2.3 2.9 3.6 A tIOS Short-circuit response time(3) VIN = 5 V (see Figure 6), One-half full load → RSHORT = 50 mΩ, Measure from application to when current falls below 120% of final value 2 µs SUPPLY CURRENT ISD Supply current, switch disabled IOUT = 0 A 0.01 10 µA ISE Supply current, switch enabled IOUT = 0 A 65 90 µA IREV Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measure IVOUT 0.2 20 µA UNDERVOLTAGE LOCKOUT VUVLO Rising threshold VIN↑ 3.5 3.75 4 V Hysteresis(3) VIN↓ 0.14 V FLT Output low voltage, FLT IFLT = 1 mA 0.2 V OFF-state leakage VFLT = 5.5 V 1 µA tFLT FLT deglitch FLT assertion or deassertion deglitch 6 9 12 ms OUTPUT DISCHARGE RPD Output pulldown resistance VIN = 4 V, VOUT = 5 V, disabled 350 560 1200 Ω VIN = 5 V, VOUT = 5 V, disabled 300 470 800 THERMAL SHUTDOWN Rising threshold (TJ) In current limit 135 °CNot in current limit 155 Hysteresis (3) 20

7.7 Timing Requirements: TJ = TA = 25°C

ENABLE INPUT (EN) tON Turnon time VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑. See Figure 1, Figure 3, and Figure 4 1.2 1.7 2.2 ms tOFF Turnoff time VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓. See Figure 1, Figure 3, and Figure 4 1.7 2.1 2.5 ms tR Rise time, output CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2 0.5 0.7 1 ms tF Fall time, output CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2 0.3 0.43 0.55 ms

7.8 Typical Characteristics

Figure 7. Deglitch Period (TFLT) vs Temperature Figure 8. Output Discharge Current vs Output Voltage Figure 9. Short Circuit Current (IOS) vs Temperature Figure 10. Reverse Leakage Current (IREV) vs Temperature Figure 11. Disabled Supply Current (ISD) vs Temperature Figure 12. Disabled Supply Current (ISD) vs Input Voltage

8 Detailed Description

8.1 Overview

overtemperature protection, and deglitched fault reporting.

8.2 Functional Block Diagram

Figure 19. TPS2001D Block Diagram

8.3 Feature Description

8.3.1 Undervoltage Lockout

surges. FLT is high impedance when the TPS2001D is in UVLO.

8.3.2 Enable

elements experiences a fall time determined by the (R × C) time constant if it is longer than the tF. The enable must not be left open, and may be tied to VIN or GND depending on the device.

8.3.3 Internal Charge Pump

8.3.4 Current Limit

1. input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS)
2. input voltage is present and the TPS2001D is enabled into a short circuit.

overload condition is removed or the device begins to thermal cycle. limit. The device remains off until the junction temperature cools 20°C and then restarts. in Figure 20. This is why the IOC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C. Figure 20. Current Limit Profiles

SLVSE25A – JULY 2017– REVISED OCTOBER 2017 www.ti.com Product Folder Links: TPS2001D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Feature Description (continued)

8.3.5 FLT

The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer does not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS as the ripple drives the device in and out of current limit. If the TPS2001D is in current limit and the overtemperature circuit goes active, FLT goes true immediately; however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is entered. Disabling the TPS2001D clears an active FLT as soon as the switch turns off. FLT is high impedance when the TPS2001D is disabled or in undervoltage lockout (UVLO).

8.3.6 Output Discharge

A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS2001D is in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge resistance as VIN falls towards 0 V. The output is be controlled by an external loadings when the device is in ULVO or disabled.

8.4 Device Functional Modes

There are no other functional modes.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

load current. The device enters constant-current mode when the load exceeds the current limit threshold.

9.2 Typical Application

Figure 21. Typical Application Schematic

9.2.1 Design Requirements

1. The TPS2001D operates from a 5-V to ±0.5-V input rail.
2. What is the normal operation current, for example, the maximum allowable current drawn by portable

limit of power switch must exceed 900 mA to avoid false trigger during normal operation.

1. What is the maximum allowable current provided by up-stream power, the maximum current limit of power

encountered at the output of power switch.

9.2.2 Detailed Design Procedure

1. Normal input operation voltage
2. Output continuous current
3. Maximum up-stream power supply output current

9.2.2.1 Input and Output Capacitance

capacitor between IN and GND, as close to the device as possible for local noise decoupling. All protection circuits have the potential for input voltage overshoots and output voltage undershoots.

time and limiting the transient seen on the input power bus. Momentary input transients to 6.5 V are permitted. ceramic capacitance on the output. The voltage undershoot must be controlled to less than 1.5 V for 10 µs.

9.2.3 Application Curves

Figure 22. TPS2001D Turnon into 2.5 Ω Figure 23. TPS2001D Enable into Short Figure 24. TPS2001D Pulsed Output Short

10 Power Supply Recommendations

of the power supply should exceed the maximum current limit of the power switch.

11 Layout

11.1 Layout Guidelines

1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low
2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections

using a low inductance trace.

11.2 Layout Example

Figure 25. DGK Package PCB Layout Example Figure 26. DBV Package PCB Layout Example

SLVSE25A – JULY 2017– REVISED OCTOBER 2017 www.ti.com Product Folder Links: TPS2001D Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS2001D. The system designer can control choices of package, proximity to other power dissipating devices, and printed-circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the pad improve the efficiency and reliability of both the TPS2001D part and the system. The following examples were used to determine the θJA Custom thermal impedances noted in Thermal Information. They were based on use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers. The θJA is 110.3°C/W. These values may be used in Equation 1 to determine the maximum junction temperature. As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred board construction from the Thermal Information table. TJ = TA + ((IOUT 2 × RDS(ON)) × θJA) where

• IOUT = rated OUT pin current (A)
• RDS(ON) = Power switch ON-resistance at an assumed TJ (Ω)
• TA = Maximum ambient temperature (°C)
• TJ = Maximum junction temperature (°C)
• θJA = Thermal resistance (°C/W) (1) If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using the typical characteristic plot and recalculate. If the resulting TJ is not less than 125°C, try a PCB construction or a package with lower θJA.

www.ti.com SLVSE25A –JULY 2017– REVISED OCTOBER 2017 Product Folder Links: TPS2001D Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 17-Nov-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPS2001DDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1E6L TPS2001DDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 1E6L TPS2001DDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1D6K TPS2001DDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 1D6K (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 17-Nov-2017 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2001DDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0 TPS2001DDBVT SOT-23 DBV 5 250 210.0 185.0 35.0 TPS2001DDGKR VSSOP DGK 8 2500 366.0 364.0 50.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2017 Pack Materials-Page 2

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