TPS20001C

TPS20XXC TI1 | Alldatasheet

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Technical content

• Rated currents of 0.5 A, 1 A, 1.5 A, 2 A encountered. This family offers multiple devices with fixed current-limit thresholds for applications between• ±20% Accurate, Fixed, Constant Current Limit 0.5 A and 2 A.• Fast Over-Current Response– 2 µs The TPS20xxC family limits the output current to a• Deglitched Fault Reporting safe level by operating in a constant-current mode• Output Discharge When Disabled when the output load exceeds the current-limit
• Reverse Current Blocking threshold. This provides a predictable fault current under all conditions. The fast overload response time• Built-in Softstart eases the burden on the main 5 V supply to provide• Ambient Temperature Range:–40°C to 85°C regulated power when the output is shorted. The power-switch rise and fall times are controlled toAPPLICATIONS minimize current surges during turn-on and turn-off.
• USB Ports/Hubs, Laptops, Desktops
• High-Definition Digital TVs
• Set Top Boxes
• Short-Circuit Protection TYPICAL APPLICATION

Figure 1. Typical Application Table 1. DEVICES(1)

0.5 TPS2051C - Preview

1 TPS2065C Active Preview

1.5 TPS2069C Active -

2 TPS2000C / 1C Active -

(1) For more details, see theDEVICE INFORMATIONtable. Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2PowerPAD is a trademark of Texas Instruments. 3 is a trademark of ~ Texas Instruments. UNLESS OTHERWISE NOTED this document contains Copyright © 2011, Texas Instruments IncorporatedPRODUCTION DATA information current as of publication date. necessarily include testing of all parameters.

SLVSAU6A –JUNE 2011–REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION (1) PACKAGED DEVICE (2) MAXIMUM OUTPUT BASE PARTOPERATING ENABLE MARKINGMSOP-8 (DGN) SOT23-5DISCHARGE NUMBERCURRENT PowerPAD ™ (DBV)

0.5 Y High TPS2051C – √ VBYQ

1 Y High TPS2065C √ √ VCAQ

1.5 Y High TPS2069C √ – VBUQ

2 Y Low TPS2000C √ – BCMS

2 Y High TPS2001C √ – VBWQ

(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI website atwww.ti.com. (2) "-" indicates the device is not available in this package. ABSOLUTE MAXIMUM RATINGS (1)(2) VALUE UNIT MIN MAX Voltage range on IN, OUT, EN or EN, FLT(3) –0.3 6 V Voltage range from IN to OUT –6 6 V Maximum junction temperature, TJ Internally Limited HBM 2 kV Electrostatic Discharge CDM 500 V IEC 61000-4-2, Contact / Air(4) 8 15 kV (1) Absolute maximum ratings apply over recommended junction temperature range. (2) Voltages are with respect to GND unless otherwise noted. (3) See the Input and Output Capacitancesection. (4) V OUT was surged on a pcb with input and output bypassing perFigure 1(except input capacitor was 22µF) with no device failures. THERMAL INFORMATION 0.5 A or 1 A 1.5 A or 2 A 0.5 A or 1 A 1.5 A or 2 A Rated Rated Rated RatedTHERMAL METRIC (1) UNITS(See DEVICE INFORMATION table.) DBV DBV DGN DGN

5 PINS 5 PINS 8 PINS 8 PINS

θJA Junction-to-ambient thermal resistance 224.9 220.4 72.1 67.1 θJCtop Junction-to-case (top) thermal resistance 95.2 89.7 87.3 80.8 θJB Junction-to-board thermal resistance 51.4 46.9 42.2 37.2 ψJT Junction-to-top characterization parameter 6.6 5.2 7.3 5.6 °C/W ψJB Junction-to-board characterization parameter 50.3 46.2 42.0 36.9 θJCbot Junction-to-case (bottom) thermal resistance N/A N/A 39.2 32.1 See thePower DIssipation and JunctionθJACustom 139.3 134.9 66.5 61.3Temperature section (1) For more information about traditional and new thermal metrics, see theIC Package Thermal Metricsapplication report,SPRA953.

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www.ti.com SLVSAU6A –JUNE 2011–REVISED JULY 2011 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VIN Input voltage, IN 4.5 5.5 V VEN Input voltage, EN or EN 0 5.5 V TPS2051C 0.5 TPS2065C 1Continuous output current,IOUT AOUT TPS2069C 1.5 TPS2000C/01C 2 TJ Operating junction temperature –40 125 °C IFLT Sink current into FLT 0 5 mA ELECTRICAL CHARACTERISTICS: T J = TA = 25°C (1) Unless otherwise noted:, VIN = 5 V, VEN = VIN or VEN = GND, IOUT = 0 A. See the DEVICE INFORMATION table for the rated current of each part number. Parametrics over a wider operational range are shown in the second ELECTRICAL CHARACTERISTICS table. PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT POWER SWITCH

0.5 A rated output, 25°C DBV 97 110 m Ω

0.5 A rated output, DBV 96 130 m Ω–40°C ≤ (TJ , TA) ≤ 85°C

1 A rated output, 25°C mΩ

DBV 96 1301 A rated output, mΩRDS(ON) Input – output resistance –40°C ≤ (TJ , TA) ≤ 85°C DGN 86 120

1.5 A rated output, 25°C DGN 69 84 m Ω

1.5 A rated output, DGN 69 98 m Ω–40°C ≤ (TJ , TA) ≤ 85°C

2 A rated output, 25°C DGN 72 84 m Ω

2 A rated output, DGN 72 98 m Ω–40°C ≤ (TJ , TA) ≤ 85°C

0.5A rated output 0.67 0.85 1.01 1 A rated output 1.3 1.55 1.8Current-limit,IOS (2) ASee Figure 7 1.5 A rated output 1.7 2.15 2.5 2 A rated output 2.35 2.9 3.4 SUPPLY CURRENT 0.01 1 ISD Supply current, switch disabled µA –40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V 2 60 70 ISE Supply current, switch enabled µA –40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V 85 VOUT = 5 V, VIN = 0 V, measure IVOUT 0.1 1 IREV Reverse leakage current µA–40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 5V, measure IVOUT OUTPUT DISCHARGE RPD Output pull-down resistance(3) VIN = VOUT = 5 V, disabled 400 470 600 Ω (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature (2) See CURRENT LIMITsection for explanation of this parameter. (3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty. Copyright © 2011, Texas Instruments Incorporated 3

SLVSAU6A –JUNE 2011–REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: –40°C ≤ TJ ≤ 125°C Unless otherwise noted:4.5 V≤ VIN ≤ 5.5 V, VEN = VIN or VEN = GND, IOUT = 0 A, typical values are at 5 V and 25°C. See the DEVICE INFORMATION table for the rated current of each part number. PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT POWER SWITCH

0.5 A rated output DBV 97 154 m Ω

1 A rated output mΩ

RDS(ON) Input – output resistance DGN 86 140

1.5 A rated output DGN 69 112 m Ω

2 A rated output DGN 72 112 m Ω

ENABLE INPUT (EN or EN) Threshold Input rising 1 1.45 2 V Hysteresis 0.07 0.13 0.20 V Leakage current (VEN or VEN) = 0 V or 5.5 V –1 0 1 µA VIN = 5 V, CL = 1µF, RL = 100Ω, EN↑ or EN↓. See Figure 2, Figure 4, andFigure 5 tON Turnon time ms0.5A / 1A Rated 1 1.4 1.8 1.5A / 2A Rated 1.2 1.7 2.2 VIN = 5 V, CL = 1µF, RL = 100Ω, EN↓ or EN↑. See Figure 2, Figure 4, andFigure 5 tOFF Turnoff time ms0.5A and 1A Rated 1.3 1.65 2 1.5A / 2A Rated 1.7 2.1 2.5 CL = 1µF, RL = 100Ω, VIN = 5 V. SeeFigure 3 tR Rise time, output 0.5A / 1A Rated 0.4 0.55 0.7 ms 1.5A / 2A Rated 0.5 0.7 1.0 CL = 1µF, RL = 100Ω, VIN = 5 V. SeeFigure 3 tF Fall time, output 0.5A / 1A Rated 0.25 0.35 0.45 ms 1.5A / 2A Rated 0.3 0.43 0.55 CURRENT LIMIT 0.5 A rated 0.65 0.85 1.05output 1 A rated output 1.2 1.55 1.9Current-limit,IOS (2) ASee Figure 8 1.5 A rated 1.6 2.15 2.7output 2 A rated output 2.3 2.9 3.6 VIN = 5 V (seeFigure 7), One-half full load→ RSHORT = 50 mΩ,tIOS Short-circuit response time(3) 2 µsMeasure from application to when current falls below 120% of final value SUPPLY CURRENT ISD Supply current, switch disabled 0.01 10 µA ISE Supply current, switch enabled 65 90 µA IREV Reverse leakage current V OUT = 5.5 V, VIN = 0 V, Measure IVOUT 0.2 20 µA UNDERVOLTAGE LOCKOUT VUVLO Rising threshold VIN↑ 3.5 3.75 4 V Hysteresis(3) VIN↓ 0.14 V (1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature (2) See CURRENT LIMITsection for explanation of this parameter. (3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

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P ump Driver UVLO Current L imit Thermal S ense 9-ms D eglitch IN G ND OUT FLT Current S ense (Disabled+ U VLO) OTSD CS EN or E N TPS20xxC SLVSAU6A –JUNE 2011–REVISED JULY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM DEVICE INFORMATION PIN FUNCTIONS NAME PINS DESCRIPTION 8-PIN PACKAGE EN or EN 4 Enable input, logic high turns on power switch GND 1 Ground connection IN 2, 3 Input voltage and power-switch drain; connect a 0.1µF or greater ceramic capacitor from IN to GND close to the IC FLT 5 Active-low open-drain output, asserted during over-current, or over-temperature conditions OUT 6, 7, 8 Power-switch output, connect to load PowerPAD PAD Internally connected to GND. Connect PAD to GND plane as a heatsink for the best thermal performance. (DGN ONLY) PAD may be left floating if desired. SeePOWER DISSIPATION AND JUNCTION TEMPERATUREsection for guidance. 5-PIN PACKAGE EN or EN 4 Enable input, logic high turns on power switch GND 2 Ground connection IN 5 Input voltage and power-switch drain; connect a 0.1µF or greater ceramic capacitor from IN to GND close to the IC FLT 3 Active-low open-drain output, asserted during over-current, or over-temperature conditions OUT 1 Power-switch output, connect to load.

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Figure 13. TPS2065C Short Applied Figure 14. TPS2065C Pulsed 1.45-A Load Figure 15. NEW FIG Figure 16. TPS2065C Power Up - Enabled Figure 17. TPS2065C Power Down - Enabled Figure 18. TPS2001C Turn ON into 2.5Ω

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Figure 25. TPS2069CDGN Enable into Short Figure 26. TPS2069CDGN Pulsed Output Short Figure 27. Deglitch Period (tFLT) vs Temperature Figure 28. Output Discharge Current vs Output Voltage Figure 29. Short Circuit Current (IOS ) vs Temperature Figure 30. Reverse Leakage Current (IREV ) vs Temperature

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Figure 37. Output Rise Time (tR ) vs Temperature Figure 38. Input-Output Resistance (RDS(ON) ) vs Figure 39. Recovery Vs Current Peak

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www.ti.com SLVSAU6A –JUNE 2011–REVISED JULY 2011 DETAILED DESCRIPTION The TPS20xxC are current-limited, power-distribution switches providing between 0.5 A and 2 A of continuous load current in 5 V circuits. These parts use N-channel MOSFETs for low resistance, maintaining voltage regulation to the load. They are designed for applications where short circuits or heavy capacitive loads will be encountered. Device features include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection, over-temperature protection, and deglitched fault reporting. UVLO The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large current surges. FLT is high impedance when the TPS20xxC is in UVLO. ENABLE The logic enable input (EN, or EN), controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPS20xxC is disabled. Disabling the TPS20xxC will immediately clear an active FLT indication. The enable input is compatible with both TTL and CMOS logic levels. The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times are internally controlled. The rise time is controlled by both the TPS20xxC and the external loading (especially capacitance). The fall time is controlled by the TPS20xxC, the loading (R and C), and the output discharge (RPD). An output load consisting of only a resistor will experience a fall time set by the TPS20xxC. An output load with parallel R and C elements will experience a fall time determined by the (R× C) time constant if it is longer than the TPS20xxC’s tF. The enable should not be left open, and may be tied to VIN or GND depending on the device. INTERNAL CHARGE PUMP The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or disabled. CURRENT LIMIT The TPS20xxC responds to overloads by limiting output current to the static IOS levels shown in the Electrical Characteristics table. When an overload condition is present, the device maintains a constant output current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur. The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit is present (load which draws IOUT > IOS), or 2) input voltage is present and the TPS20xxC is enabled into a short circuit. The output voltage is held near zero potential with respect to ground and the TPS20xxC ramps the output current to IOS. The TPS20xxC will limit the current to IOS until the overload condition is removed or the device begins to thermal cycle. This is demonstrated inFigure 11 where the device was enabled into a short, and subsequently cycles current off and on as the thermal protection engages. The second condition is when an overload occurs while the device is enabled and fully turned on. The device responds to the overload condition within tIOS (Figure 6and Figure 7) when the specified overload (per Electrical Characteristics table) is applied. The response speed and shape will vary with the overload level, input circuit, and rate of application. The current-limit response will vary between simply settling to IOS, or turnoff and controlled return to IOS. Similar to the previous case, the TPS20xxC will limit the current to IOS until the overload condition is removed or the device begins to thermal cycle. This is demonstrated byFigure 12, Figure 13, and Figure 14. Copyright © 2011, Texas Instruments Incorporated 13

temperature up. The device turns off when the junction temperature exceeds 135°C (min) while in current limit. The device remains off until the junction temperature cools 20°C and then restarts. There are two kinds of current limit profiles typically available in TI switch products similar to the TPS20xxC. Figure 40. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the Figure 40. This is why the IOC parameter is not present in the Electrical Characteristics tables. Figure 40. Current Limit Profiles ripple will drive the TPS20xxC in and out of current limit. off (seeFigure 11). FLT is high impedance when the TPS20xxC is disabled or in under-voltage lockout (UVLO). discharge resistance as VIN falls towards 0 V.

14 Copyright © 2011, Texas Instruments Incorporated

www.ti.com SLVSAU6A –JUNE 2011–REVISED JULY 2011

APPLICATION INFORMATION

INPUT AND OUTPUT CAPACITANCE Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular application. For all applications, a 0.1 µF or greater ceramic bypass capacitor between IN and GND is recommended as close to the device as possible for local noise decoupling. All protection circuits such as the TPS20xxC will have the potential for input voltage overshoots and output voltage undershoots. Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high impedance (before turn on). Theoretically, the peak voltage is 2 times the applied. The second cause is due to the abrupt reduction of output short circuit current when the TPS20xxC turns off and energy stored in the input inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the TPS20xxC output is shorted. Applications with large input inductance (e.g. connecting the evaluation board to the bench power-supply through long cables) may require large input capacitance reduce the voltage overshoot from exceeding the absolute maximum voltage of the device. The fast current-limit speed of the TPS20xxC to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of 1µF to 22µF adjacent to the TPS20xxC input aids in both speeding the response time and limiting the transient seen on the input power bus. Momentary input transients to 6.5V are permitted. Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred and the TPS20xxC has abruptly reduced OUT current. Energy stored in the inductance will drive the OUT voltage down and potentially negative as it discharges. Applications with large output inductance (such as from a cable) benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB standard applications, a 120µF minimum output capacitance is required. Typically a 150µF electrolytic capacitor is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of capacitance, and there is potential to drive the output negative, a minimum of 10 µF ceramic capacitance on the output is recommended. The voltage undershoot should be controlled to less than 1.5 V for 10 µs. POWER DISSIPATION AND JUNCTION TEMPERATURE It is good design practice to estimate power dissipation and maximum expected junction temperature of the TPS20xxC. The system designer can control choices of package, proximity to other power dissipating devices, and printed circuit board (PCB) design based on these calculations. These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the pad improve the efficiency and reliability of both TPS20xxC parts and the system. The following examples were used to determine theθJACustom thermal impedances noted in the THERMAL INFORMATION table. They were based on use of the JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1oz. copper weight, layers. While it is recommended that the DGN package PAD be soldered to circuit board copper fill and vias for low thermal impedance, there may be cases where this is not desired. For example, use of routing area under the IC. The TPS20xxC will operate properly with the pad not connected to GND.θJA for a 4 layer board with the pad not soldered is approximately 141°C/W for the 0.5-A and 1-A rated parts and 139°C/W for the 1.5-A and 2-A rated parts. These values may be used inEquation 1below to determine the maximum junction temperature. Copyright © 2011, Texas Instruments Incorporated 15

VIN: 0.0145in2 area & 2 x 0.018in vias GND: 0.056in2 total area & 3 x 0.018in vias COUT VOUT: 0.048in 2 total area 5 x 0.01in vias 0.050in trace COUT VIN: 0.00925in 2 & 3 x 0.018in vias VOUT: 0.041in 2 total 0.050in trace 4 x 0.01in vias CIN GND : 0.052in2 Total & 3 x 0.018in vias TPS20xxC SLVSAU6A –JUNE 2011–REVISED JULY 2011 www.ti.com Figure 41. DBV Package PCB Layout Example Figure 42. DGN Package PCB Layout Example construction from the THERMAL INFORMATION table. the typical characteristic plot and recalculate. If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lowerθJA .

REVISION HISTORY

Changes from Original (June 2011) to Revision A Page

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www.ti.com 11-Aug-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS2000CDGN PREVIEW MSOP- PowerPAD DGN 8 80 TBD Call TI Call TI TPS2000CDGNR PREVIEW MSOP- PowerPAD DGN 8 2500 TBD Call TI Call TI TPS2001CDGN PREVIEW MSOP- PowerPAD DGN 8 80 TBD Call TI Call TI TPS2001CDGNR ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2051CDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI TPS2051CDBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI TPS2065CDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI TPS2065CDBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI TPS2065CDGN ACTIVE MSOP- PowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2065CDGNR ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2069CDGN ACTIVE MSOP- PowerPAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2069CDGNR ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

www.ti.com 11-Aug-2011 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPS2000CDGNR MSOP- Power PAD TPS2000CDGNR MSOP- Power PAD TPS2001CDGNR MSOP- Power PAD TPS2001CDGNR MSOP- Power PAD TPS2065CDGNR MSOP- Power PAD TPS2065CDGNR MSOP- Power PAD TPS2069CDGNR MSOP- Power PAD PACKAGE MATERIALS INFORMATION www.ti.com 15-Aug-2011 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Power PAD *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2000CDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2000CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0 TPS2001CDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2001CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0 TPS2065CDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 TPS2065CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0 TPS2069CDGNR MSOP-PowerPAD DGN 8 2500 360.0 162.0 98.0 TPS2069CDGNR MSOP-PowerPAD DGN 8 2500 370.0 355.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Aug-2011 Pack Materials-Page 2

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