TPS1120 TI | Alldatasheet
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TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low rDS(on) . . . 0.18 Ω at VGS = –10 V /C00683-V Compatible /C0068Requires No External VCC /C0068TTL and CMOS Compatible Inputs /C0068VGS(th) = –1.5 V Max /C0068ESD Protection Up to 2 kV per MIL-STD-883C, Method 3015
description
The TPS1120 incorporates two independent p-channel enhancement-mode MOSFETs that have been optimized, by means of the Texas Instruments LinBiCMOS process, for 3-V or 5-V power distribution in battery-powered systems. With a maximum V GS(th) of –1.5 V and an IDSS of only 0.5 µA, the TPS1120 is the ideal high-side switch for low-voltage portable battery-management systems, where maximizing battery life is a primary concern. Because portable equipment is potentially subject to electrostatic discharge (ESD), the MOSFETs have built-in circuitry for 2-kV ESD protection. End equipment for the TPS1120 includes notebook computers, personal digital assistants (PDAs), cellular telephones, bar-code scanners, and PCMCIA cards. For existing designs, the TPS1120D has a pinout common with other p-channel MOSFETs in small-outline integrated circuit SOIC packages. The TPS1120 is characterized for an operating junction temperature range, T J, from –40°C to 150°C. AVAILABLE OPTIONS PACKAGED DEVICES † CHIP FORMTJ SMALL OUTLINE (D) CHIP FORM (Y) –40°C to 150°C TPS1120D TPS1120Y † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS1120DR). The chip form is tested at 25°C. Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. LinBiCMS is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1SOURCE 1GATE 2SOURCE 2GATE 1DRAIN 1DRAIN 2DRAIN 2DRAIN D PACKAGE (TOP VIEW)
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995
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1DRAIN † ESD- Protection Circuitry 2GATE 2SOURCE 2DRAIN † ESD- Protection Circuitry † For all applications, both drain pins for each device should be connected. TPS1120Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1120C. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS TPS1120Y (2) (6) (1) (3) (7) (8) (5)(4) 1DRAIN1SOURCE 1GATE 2SOURCE 2GATE 1DRAIN 2DRAIN 2DRAIN (2) (1) (3) (4) (6) (7) (8) (5)
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS –15 V Gate-to-source voltage, VGS 2 or –15 V VGS =2 7 V TA = 25°C ± 0.39 VGS = –2.7 V TA = 125°C ± 0.21 VGS =3 V TA = 25°C ± 0.5 Continuous drain current each device (TJ = 150°C) ID VGS = –3 V TA = 125°C ± 0.25 AContinuous drain current, each device (TJ = 150°C), ID VGS =4 5 V TA = 25°C ± 0.74 A VGS = –4.5 V TA = 125°C ± 0.34 VGS =1 0 V TA = 25°C ± 1.17 VGS = –10 V TA = 125°C ± 0.53 Pulse drain current, ID TA = 25°C ± 7 A Continuous source current (diode conduction), IS TA = 25°C –1 A Continuous total power dissipation See Dissipation Rating Table Storage temperature range, Tstg –55 to 150 °C Operating junction temperature range, TJ –40 to 150 °C Operating free-air temperature range, TA –40 to 125 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 840 mW 6.71 mW/°C 538 mW 437 mW 169 mW ‡ Maximum values are calculated using a derating factor based on RθJA = 149°C/W for the package. These devices are mounted on an FR4 board with no special thermal considerations.
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995
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electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER TEST CONDITIONS TPS1120 UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VGS(th) Gate-to-source threshold voltage VDS = VGS , ID = –250 µA –1 –1.25 –1.50 V VSD Source-to-drain voltage (diode forward voltage)† IS = –1 A, VGS = 0 V –0.9 V IGSS Reverse gate current, drain short circuited to sourceVDS = 0 V, VGS = –12 V ± 100 nA IDSS Zero gate voltage drain current VDS = –12 V, TJ = 25°C –0.5 µAIDSS Zero-gate-voltage drain current DS , VGS = 0 V TJ = 125°C –10 µA VGS = –10 V ID = –1.5 A 180 rDS( ) Static drain to source on state resistance† VGS = –4.5 V ID = –0.5 A 291 400 m ΩrDS(on) Static drain-to-source on-state resistance† VGS = –3 V ID =0 2 A 476 700 m Ω VGS = –2.7 V ID = –0.2 A 606 850 gfs Forward transconductance† VDS = –10 V, ID = –2 A 2.5 S † Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2% static PARAMETER TEST CONDITIONS TPS1120Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VGS(th) Gate-to-source threshold voltage VDS = VGS , ID = –250 µA –1.25 V VSD Source-to-drain voltage (diode forward voltage)† IS = –1 A, VGS = 0 V –0.9 V VGS = –10 V ID = –1.5 A 180 rDS( ) Static drain to source on state resistance† VGS = –4.5 V ID = –0.5 A 291 m ΩrDS(on) Static drain-to-source on-state resistance† VGS = –3 V ID =0 2 A 476 m Ω VGS = –2.7 V ID = –0.2 A 606 gfs Forward transconductance† VDS = –10 V, ID = –2 A 2.5 S † Pulse test: pulse width ≤ 300 µs, duty cycle ≤ 2% dynamic PARAMETER TEST CONDITIONS TPS1120, TPS1120Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT Q g Total gate charge 5.45 Q gs Gate-to-source charge VDS = –10 V, VGS = –10 V, I D = –1 A 0.87 nC Q gd Gate-to-drain charge 1.4 td(on) Turn-on delay time 4.5 ns td(off) Turn-off delay time VDD = –10 V, R L = 10 Ω ,I D = –1 A, 13 ns tr Rise time DD , R G = 6 Ω , L , See Figures 1 and 2 D , tf Fall time 2 ns trr(SD) Source-to-drain reverse recovery timeIF = 5.3 A, di/dt = 100 A/µs 16
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995
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TYPICAL CHARACTERISTICS † Table of Graphs FIGURE Drain current vs Drain-to-source voltage 3 Drain current vs Gate-to-source voltage 4 Static drain-to-source on-state resistance vs Drain current 5 Capacitance vs Drain-to-source voltage 6 Static drain-to-source on-state resistance (normalized)vs Junction temperature 7 Source-to-drain diode current vs Source-to-drain voltage 8 Static drain-to-source on-state resistance vs Gate-to-source voltage 9 Gate-to-source threshold voltage vs Junction temperature 10 Gate-to-source voltage vs Gate charge 11 – 5 – 4 – 2 – 1 – 3 – Drain Current – A – 7 – 6 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 7 – 8 – 9 – 10 VGS = –6 V ÁÁ ÁÁ ID VDS – Drain-to-Source Voltage – V VGS = –8 V VGS = –7 V VGS = –3 V VGS = –4 V VGS = –2 V VGS = –5 V TJ = 25°C Figure 3 Figure 4 0 – 2 – 3 – 5 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE – 7– 1 – 4 – 6 – Drain Current – A ÁÁ ÁÁ ID VGS – Gate-to-Source Voltage – V TJ = 150°CTJ = 25°C TJ = –40°C VDS = –10 V – 5 – 4 – 2 – 1 – 3 – 7 – 6 † All characteristics data applies for each independent MOSFET incorporated on the TPS1120.
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995
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0.2 0.1 – 1 – 3 – 5 – 7 0.3 0.4 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs GATE-TO-SOURCE VOLTAGE 0.5 – 9 – 11 – 13 – 15 VGS – Gate-to-Source Voltage – V 0.6 0.7 ID = –1 A TJ = 25°C – Static Drain-to-Source On-State rDS(on) ΩResistance – Figure 9 Figure 10 – 1.2 – 1.1 – Gate-to-Source Threshold Voltage – V – 1.3 – 1.4 GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE – 1.5 –50 0 50 100 150 – 1 – 0.9 TJ – Junction Temperature – °C ÁÁ ÁÁ ÁÁ VGS(th) ID = –250 µA – 6 – 4 – 2 02 35 – 8 GATE-TO-SOURCE VOLTAGE vs GATE CHARGE – 10 14 6 – Gate-to-Source Voltage – V Q g – Gate Charge – nC VGS VDS = –10 V ID = –1 A TJ = 25°C Figure 11
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and 1-oz tin/lead (63/37) plate. Use of vias or through-holes to enhance thermal conduction was avoided. Figure 14. Profile of Heat Sinks
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION Figure 16 illustrates the thermally enhanced (SO) lead frame. Attaching the two MOSFET dies directly to the source terminals allows maximum heat transfer into a power plane. Lead 8 Lead 7 Lead 6 Lead 5 Lead 1 Lead 2 Lead 3 Lead 4 1GATE 1SOURCE 2GATE 2SOURCE 1DRAIN 1DRAIN 2DRAIN 2DRAIN MOSFET 2 MOSFET 1 Pad 1 Pad 1 Figure 16. TPS1120 Dual MOSFET SO-8 Lead Frame
APPLICATION INFORMATION
3 V or 5 V
Figure 17. Notebook Load Management Figure 18. Cellular Phone Output Drive
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPS1120D Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM - 1120 TPS1120D.A Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM See TPS1120D 1120 TPS1120D.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-1-260C-UNLIM See TPS1120D 1120 TPS1120DR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - 1120 TPS1120DR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See TPS1120DR 1120 TPS1120DR.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See TPS1120DR 1120 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 23-May-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS1120DR SOIC D 8 2500 350.0 350.0 43.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPS1120D D SOIC 8 75 505.46 6.76 3810 4 TPS1120D.A D SOIC 8 75 505.46 6.76 3810 4 TPS1120D.B D SOIC 8 75 505.46 6.76 3810 4 Pack Materials-Page 3
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