TPS1110 TI1 | Alldatasheet
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TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low rDS(on) . . . 65 mΩ Typ at VGS = –4.5 V /C0068High Current Capability 6 A at VGS = –4.5 V /C0068Logic-Level Gate Drive (3 V Compatible) VGS(th) = –0.9 V Max /C0068Low Drain-Source Leakage Current <100 nA From 25°C to 75°C at VDS = –6 V /C0068Fast Switching... 5.8 ns Typ td(on) /C0068Small-Outline Surface-Mount Power Package
description
The TPS1110 is a single, low-rDS(on), P-channel enhancement-mode power MOS transistor. The device features extremely low-rDS(on) values coupled with logic-level gate-drive capability and very low drain-source leakage current. With a maximum VGS(th) of –0.9 V and an IDSS of only –100 nA, the TPS1110 is the ideal high-side switch for low-voltage, portable battery-management power-distribution systems where maximizing battery life is an important concern. The thermal performance of the 8-pin small-outline (D) package has been greatly enhanced over the standard 8-pin SOIC, further making the TPS1110 ideally suited for many power applications. For compatibility with existing designs, the TPS1110 has a pinout common with other P-channel MOSFETs in small-outline integrated circuit (SOIC) packages. The TPS1110 is characterized for an operating junction temperature range, T J, from –40°C to 150°C. The D package is available packaged in standard sleeves or in taped and reeled formats. When ordering the tape-and-reel format, add an R suffix to the device type number (e.g., TPS1110DR). AVAILABLE OPTIONS PACKAGED DEVICE † CHIP FORMTJ SMALL OUTLINE (D) CHIP FORM (Y) –40°C to 150°C TPS1110D TPS1110Y † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS1110DR). The chip form is tested at 25°C. schematic GATE SOURCE DRAIN 12 3 56 78 Copyright 1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN D PACKAGE (TOP VIEW)
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
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This chip, when properly assembled, displays characteristics similar to the TPS1110C. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS TPS1110Y (2) (6) (1) (3) (7) (8) (5)(4) DRAINSOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN (2) (1) (3) (4) (6) (7) (8) (5)
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS –7 V Gate-to-source voltage, VGS ±7 V VGS =2 7 V TP = 25°C ‡ –5 Continuous drain current ID VGS = –2.7 V TP = 125°C ‡ –2.3 AContinuous drain current, ID VGS =4 5 V TP = 25°C ‡ –6 A VGS = –4.5 V TP = 125°C ‡ –2.7 Pulse drain current, ID TA = 25°C –24 A Continuous source current (diode conduction), IS TA = 25°C –6 A Continuous total power dissipation TP = 25°C ‡ 4 W Junction-to-pin thermal resistance (θJP) 31 °C/W Continuous total power dissipation TA = 25°C 1.25 W Junction-to-ambient thermal resistance (θJA) 100 °C/W Storage temperature range, Tstg –65 to 150 °C Operating junction temperature range, TJ –40 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ TP – Temperature of drain pins measured close to the package electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER TEST CONDITIONS TPS1110 TPS1110Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT VGS(th) Gate-to-source threshold voltageVDS = VGS , See Figure 9 VSD Source-to-drain voltage (diode forward voltage)§ ISD = –3 A, See Figure 8 IGSS Reverse gate current, drain short circuited to source VDS = 0 V, VGS = –6 V ± 100 nA I Z t lt d i t VDS = –7 V, VGS = 0 V TJ = 25°C –100 nA IDSS Zero-gate-voltage drain current VDS = –6 V, TJ = 75°C –100 nADS , VGS = 0 V TJ = 125°C –10 µA rDS( ) Static drain-to-source on-state VGS = –4.5 V, See Figure 5 ID = –6 A, 65 75 65 m ΩrDS(on) resistance§ VGS = –2.7 V, See Figure 5 ID = –2 A, 100 110 100 m Ω gfs Forward transconductance§ VDS = –5 V, ID = –6 A 5 5 S C iss Short-circuit input capacitance, common source 275 275 C oss Short-circuit output capacitance, common source VDS = –6 V, f = 1 MHz VGS = 0 V, See Figure 6 415 415 pF C rss Short-circuit reverse transfer capacitance, common source 73 73 § Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2%
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Figure 1. Gate-Charge Test Circuit and Waveform
Figure 2. Resistive Switching
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
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Drain current vs Drain-to-source voltage 3 Drain current vs Gate-to-source voltage 4 Static drain-to-source on-state resistance vs Drain current 5 Capacitance vs Drain-to-source voltage 6 Static drain-to-source on-state resistance (normalized)vs Junction temperature 7 Source-to-drain diode current vs Source-to-drain voltage 8 Gate-to-source threshold voltage vs Junction temperature 9 Gate-to-source voltage vs Gate charge 10 – 10 – 8 – 4 – 2 – 6 – Drain Current – A – 14 – 12 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 7 VGS = –3 V ÁÁ ÁÁ ID VDS – Drain-to-Source Voltage – V 0 – 1 – 1.5 – 2.5 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE – 0.5 – 2 – 3 – Drain Current – A Á Á ID VGS – Gate-to-Source Voltage – V TJ = 150°C VDS = –5 V Pulse Test VGS = –2.5 V VGS = –1.5 V – 5 – 4 – 2 – 1 – 3 – 7 – 6 – 16 – 20 – 18 VGS = –1 V VGS = –2 V VGS = –3.5 V VGS = –4.5 V VGS = –4 V TJ = –40°C TJ = 25°C TJ = 25°C Pulse Test VGS = –5 V Figure 3 Figure 4
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
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– 0.7 – 0.6 – Gate-to-Source Threshold Voltage – V – 0.8 – 0.9 GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE – 1 –50 0 50 100 150 – 0.5 – 0.4 TJ – Junction Temperature – °C ÁÁÁ ÁÁÁ ÁÁÁ VGS(th) VDS = VGS ID = –250 µA GATE-TO-SOURCE VOLTAGE vs GATE CHARGE – Gate-to-Source Voltage – V Q g – Gate Charge – nC VGS – 3 – 2 – 1 02 35 – 4 – 5 ID = –3 A TJ = 25°C Pulse Test– 6 – 7 VDS = –5 V VDS = –6 V VDS = –4 V Figure 9 Figure 10
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION Table of Graphs FIGURE Maximum drain current vs Drain-to-source voltage 11 Junction-to-pin thermal resistance (normalized)vs Pulse duration 12 Junction-to-ambient thermal resistance (normalized)vs Pulse duration 13 – 10 – 1 – 0.1 – 100 – 0.1 – 1 – 10 – Maxmum Drain Current – A MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE ID VDS – Drain-to-Source Voltage – V 100 ms TJ = 150°C TP = 25°C † Single Pulse 10 ms 1 ms 1 s DC Conditions † TP – Temperature of drain pins measured close to the package Figure 11
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
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JUNCTION-TO-PIN THERMAL RESISTANCE (NORMALIZED) vs PULSE DURATION tw – Pulse Duration – s 0.0001 0.001 0.1 0.01 0.001 0.01 0.1 1 100 tw tc PD d = 0.5 d = 0.2 d = 0.1 d = 0.02 Single Pulse d = 0.05 d = 0.01 NOTE A: Z θJP(t) = rJP(t) ⋅ θJP tw = pulse duration tc = cycle time d = duty cycle = tw /tc peak TJ = PD ⋅ZθJP(t) + TP JA(t)– Junction-to-Pin Thermal Resistance (Normalized)r Figure 12
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION JUNCTION-TO-AMBIENT THERMAL RESISTANCE (NORMALIZED) † vs PULSE DURATION † Device mounted on FR4 printed-circuit board with no special thermal considerations. tw – Pulse Duration – s 0.0001 0.001 0.1 0.01 0.001 0.01 0.1 1 100 tw tc PD d = 0.5 d = 0.2 d = 0.1 d = 0.02 Single Pulse d = 0.05 d = 0.01 NOTE A: Z θJA(t) = rJA(t) ⋅ θJA tw = pulse duration tc = cycle time d = duty cycle = tw /tc peak TJ = PD ⋅ZθJA(t) + TA JA(t)– Juntion-to-Ambient Thermal Resistance (Normalized)r Figure 13
TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
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D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°–8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad. E. Falls within JEDEC MS-012
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TPS1110D OBSOLETE SOIC D 8 TBD Call TI Call TI TPS1110DR OBSOLETE SOIC D 8 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1
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