TPS1101D

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TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low rDS(on) . . . 0.09 Ω Typ at VGS = –10 V /C00683 V Compatible /C0068Requires No External VCC /C0068TTL and CMOS Compatible Inputs /C0068VGS(th) = –1.5 V Max /C0068Available in Ultrathin TSSOP Package (PW) /C0068ESD Protection Up to 2 kV per MIL-STD-883C, Method 3015

description

The TPS1101 is a single, low-rDS(on), P-channel, enhancement-mode MOSFET. The device has been optimized for 3-V or 5-V power distribution in battery-powered systems by means of the Texas Instruments LinBiCMOS process. With a maximum V GS(th) of –1.5 V and an IDSS of only 0.5 µA, the TPS1101 is the ideal high-side switch for low-voltage, portable battery-management systems where maximizing battery life is a primary concern. The low r DS(on) and excellent ac characteristics (rise time 5.5 ns typical) of the TPS1101 make it the logical choice for low-voltage switching applications such as power switches for pulse-width-modulated (PWM) controllers or motor/bridge drivers. The ultrathin thin shrink small-outline package or TSSOP (PW) version fits in height-restricted places where other P-channel MOSFETs cannot. The size advantage is especially important where board height restrictions do not allow for an small-outline integrated circuit (SOIC) package. Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other P-channel MOSFETs in SOIC packages. AVAILABLE OPTIONS PACKAGED DEVICES † CHIP FORMTJ SMALL OUTLINE (D) TSSOP (PW) CHIP FORM (Y) –40°C to 150°C TPS1101D TPS1101PWLE TPS1101Y † The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS1101DR). The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS1101PWLE). The chip form is tested at 25°C. Copyright  1995, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS is a trademark of Texas Instruments Incorporated. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN D PACKAGE (TOP VIEW) NC SOURCE SOURCE SOURCE SOURCE SOURCE GATE NC NC DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN NC PW PACKAGE (TOP VIEW) NC – No internal connection D PACKAGE PW PACKAGE

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

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NOTE A: For all applications, all source terminals should be connected and all drain terminals should be connected. SOURCE DRAIN GATE ESD- Protection Circuitry TPS1101Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1101. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS TPS1100Y (2) (6) (1) (3) (7) (8) (5)(4) DRAINSOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN (2)(1) (3) (4) (6)(7)(8) (5)

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS – 15 V Gate-to-source voltage, VGS 2 or – 15 V D package TA = 25°C ± 0.62 VGS =2 7 V D package TA = 125°C ± 0.39 VGS = –2.7 V PW package TA = 25°C ± 0.61 PW package TA = 125°C ± 0.38 D package TA = 25°C ± 0.88 VGS =3 V D package TA = 125°C ± 0.47 VGS = –3 V PW package TA = 25°C ± 0.86 Continuous drain current (TJ = 150°C) ID ‡ PW package TA = 125°C ± 0.45 AContinuous drain current (TJ = 150°C), ID ‡ D package TA = 25°C ± 1.52 A VGS =4 5 V D package TA = 125°C ± 0.71 VGS = –4.5 V PW package TA = 25°C ± 1.44 PW package TA = 125°C ± 0.67 D package TA = 25°C ± 2.30 VGS =1 0 V D package TA = 125°C ± 1.04 VGS = –10 V PW package TA = 25°C ± 2.18 PW package TA = 125°C ± 0.98 Pulsed drain current, ID ‡ TA = 25°C ± 10 A Continuous source current (diode conduction), IS TA = 25°C –1.1 A Storage temperature range, Tstg –55 to 150 °C Operating junction temperature range, TJ –40 to 150 °C Operating free-air temperature range, TA –40 to 125 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 176°C/W for the PW package. These devices are mounted on an FR4 board with no special thermal considerations. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW PW 710 mW 5.68 mW/°C 454 mW 369 mW 142 mW ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 176°C/W for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

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electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER TEST CONDITIONS TPS1101 TPS1101Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT VGS(th) Gate-to-source threshold voltage VDS = VGS , ID = –250 µA –1 –1.25 –1.5 –1.25 V VSD Source-to-drain voltage (diode-forward voltage)† IS = –1 A, VGS = 0 V –1.04 –1.04 V IGSS Reverse gate current, drain short circuited to source VDS = 0 V, VGS = –12 V ± 100 nA IDSS Zero-gate-voltage drainVDS =1 2 V VGS =0V TJ = 25°C –0.5 µAIDSS gg current VDS = –12 V, VGS = 0 V TJ = 125°C –10 µA VGS = –10 V ID = –2.5 A 90 90 rDS( ) Static drain-to-sourceVGS = –4.5 V ID = –1.5 A 134 190 134 m ΩrDS(on) Static drain to source on-state resistance† VGS = –3 V ID =0 5 A 198 310 198 m Ω VGS = –2.7 V ID = –0.5 A 232 400 232 gfs Forward transconductance† VDS = –10 V, ID = –2 A 4.3 4.3 S † Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2% dynamic PARAMETER TEST CONDITIONS TPS1101, TPS1101Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT Q g Total gate charge 11.25 Q gs Gate-to-source charge VDS = –10 V, VGS = –10 V, I D = –1 A 1.5 nC Q gd Gate-to-drain charge 2.6 td(on) Turn-on delay time 6.5 ns td(off) Turn-off delay time VDD = –10 V,R L = 10 Ω ,I D = –1 A, 19 ns tr Rise time DD , R G = 6 Ω , L , See Figures 1 and 2 D , 5.5 tf Fall time 13 ns trr(SD) Source-to-drain reverse recovery timeIF = 5.3 A, di/dt = 100 A/µs 16

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

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– 5 – 4 – 2 – 1 – 9 – 3 – Drain Current – A – 7 – 6 – 8 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 10 – 7 – 8 – 9 – 10 VGS = –8 V VGS = –3 V VGS = –4 V VGS = –2 V ÁÁ ÁÁ ID VDS – Drain-to-Source Voltage – V VGS = –5 V TJ = 25°C Figure 4 – 6 – 4 – 2 0 – 2 – 3 – 5 – 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE – 10 – 1 – 4 – Drain Current – A ÁÁ ÁÁ ID TJ = 25°C TJ = 150°C VGS – Gate-to-Source Voltage – V TJ = –40°C VDS = –10 V Figure 5 0.3 0.2 0.1 – 0.1 – 1 – Static Drain-to-Source On-State 0.4 0.5 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT – 10 ID – Drain Current – A rDS(on) VGS = –4.5 V VGS = –10 V TJ = 25°C Resistance –Ω VGS = –2.7 V VGS = –3 V Figure 6 500 400 200 100 C – Capacitance – pF 600 700 CAPACITANCE † vs DRAIN-TO-SOURCE VOLTAGE 800 – 7 – 8 – 9 –12 300 –10 –11 C oss C rss‡ VDS – Drain-to-Source Voltage – V C iss† VGS = 0 V f = 1 MHz TJ = 25°C C rss /C0043C gd,C oss /C0043C ds /C0041 C gs C gd C gs /C0041C gd ≈ C ds /C0041C gd‡ C iss/C0043C gs /C0041C gd,C ds(shorted)

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

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– 6 – 4 – 2 04 6 1 0 – 8 GATE-TO-SOURCE VOLTAGE vs GATE CHARGE – 10 28 1 2 Q g – Gate Charge – nC VDS = –10 V ID = –1 A TJ = 25°C – Gate-to-Source Voltage – VVGS Figure 11

TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION Figure 12 – 1 – 0.1 – 0.01 – 10 – 0.1 – 1 – 10 – 100 – Drain Current – A DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE ID VDS – Drain-to-Source Voltage – V – 100 DC 10 s 1 s 0.1 s 0.01 s 0.001 s Single Pulse See Note A TJ = 150°C TA = 25°C NOTE A: Values are for the D package and are FR4-board-mounted only. Figure 13 0.1 100 0.001 0.01 0.1 1 10 Single Pulse See Note A – Transient Junction-to-AmbientZ C/W° θJA Thermal Impedance – TRANSIENT JUNCTION-TO-AMBIENT THERMAL IMPEDANCE vs PULSE DURATION tw – Pulse Duration – s NOTE A: Values are for the D package and are FR4-board-mounted only.

APPLICATION INFORMATION

3 V or 5 V

Figure 14. Notebook Load Management Figure 15. Cellular Phone Output Drive

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