TPS1100PW

TPS1100 TI | Alldatasheet

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TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low rDS(on) . . . 0.18 Ω Typ at VGS = –10 V /C00683 V Compatible /C0068Requires No External VCC /C0068TTL and CMOS Compatible Inputs /C0068VGS(th) = –1.5 V Max /C0068Available in Ultrathin TSSOP Package (PW) /C0068ESD Protection Up to 2 kV Per MIL-STD-883C, Method 3015

description

The TPS1100 is a single P-channel enhancement-mode MOSFET. The device has been optimized for 3-V or 5-V power distribution in battery-powered systems by means of Texas Instruments LinBiCMOS process. With a maximum V GS(th) of –1.5 V and an IDSS of only 0.5 µA, the TPS1100 is the ideal high-side switch for low-voltage, portable battery-management systems where maximizing battery life is a primary concern. The low r DS(on) and excellent ac characteristics (rise time 10 ns typical) make the TPS1100 the logical choice for low-voltage switching applications such as power switches for pulse-width-modulated (PWM) controllers or motor/bridge drivers. The ultrathin thin shrink small-outline package or TSSOP (PW) version with its smaller footprint and reduction in height fits in places where other P-channel MOSFETs cannot. The size advantage is especially important where board real estate is at a premium and height restrictions do not allow for a small-outline integrated circuit (SOIC) package. AVAILABLE OPTIONS PACKAGED DEVICES CHIP FORMTA SMALL OUTLINE (D) PLASTIC DIP (P) CHIP FORM (Y) –40°C to 85°C TPS1100D TPS1100PWLE TPS1100Y The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS1100DR). The PW package is available only left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS1100PWLE). The chip form is tested at 25°C. Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. LinBiCMOS is a trademark of Texas Instruments Incorporated. Copyright  1995, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN D OR PW PACKAGE (TOP VIEW) D PACKAGE PW PACKAGE SOURCE DRAIN GATE ESD- Protection Circuitry NOTE A: For all applications, all source pins should be connected and all drain pins should be connected. schematic

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued) Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other p-channel MOSFETs in SOIC packages. TPS1100Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1100. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ± 10% ALL DIMENSIONS ARE IN MILS TPS1100Y (2) (6) (1) (3) (7) (8) (5)(4) DRAINSOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN (2) (1) (3) (4) (6) (7) (8) (5)

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS –15 V Gate-to-source voltage, VGS 2 or –15 V D package TA = 25°C ± 0.41 VGS =2 7 V D package TA = 125°C ± 0.28 VGS = –2.7 V PW package TA = 25°C ± 0.4 PW package TA = 125°C ± 0.23 D package TA = 25°C ± 0.6 VGS =3 V D package TA = 125°C ± 0.33 VGS = –3 V PW package TA = 25°C ± 0.53 Continuous drain current (TJ = 150°C) ID ‡ PW package TA = 125°C ± 0.27 AContinuous drain current (TJ = 150°C), ID ‡ D package TA = 25°C ± 1 A VGS =4 5 V D package TA = 125°C ± 0.47 VGS = –4.5 V PW package TA = 25°C ± 0.81 PW package TA = 125°C ± 0.37 D package TA = 25°C ± 1.6 VGS =1 0 V D package TA = 125°C ± 0.72 VGS = –10 V PW package TA = 25°C ± 1.27 PW package TA = 125°C ± 0.58 Pulsed drain current, ID ‡ TA = 25°C ± 7 A Continuous source current (diode conduction), IS TA = 25°C –1 A Storage temperature range, Tstg –55 to 150 °C Operating junction temperature range, TJ –40 to 150 °C Operating free-air temperature range, TA –40 to 125 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 248°C/W for the PW package. These devices are mounted on a FR4 board with no special thermal considerations. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ‡ ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW PW 504 mW 4.03 mW/°C 323 mW 262 mW 101 mW ‡ Maximum values are calculated using a derating factor based on RθJA = 158°C/W for the D package and RθJA = 248°C/W for the PW package. These devices are mounted on an FR4 board with no special thermal considerations when tested.

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER TEST CONDITIONS TPS1100 TPS1100Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT VGS(th) Gate-to-source threshold voltage VDS = VGS , ID = –250 µA –1 –1.25 –1.50 –1.25 V VSD Source-to-drain voltage (diode-forward voltage)† IS = –1 A, VGS = 0 V –0.9 –0.9 V IGSS Reverse gate current, drain short circuited to source VDS = 0 V, VGS = –12 V ± 100 nA IDSS Zero-gate-voltage drainVDS =1 2 V VGS =0V TJ = 25°C –0.5 µAIDSS gg current VDS = –12 V, VGS = 0 V TJ = 125°C –10 µA VGS = –10 V ID = –1.5 A 180 180 rDS( ) Static drain-to-sourceVGS = –4.5 V ID = –0.5 A 291 400 291 m ΩrDS(on) on-state resistance† VGS = –3 V ID =0 2 A 476 700 476 m Ω VGS = –2.7 V ID = –0.2 A 606 850 606 gfs Forward transconductance† VDS = –10 V, ID = –2 A 2.5 2.5 S † Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2% dynamic PARAMETER TEST CONDITIONS TPS1100, TPS1100Y UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT Q g Total gate charge 5.45 Q gs Gate-to-source charge VDS = –10 V, VGS = –10 V, I D = –1 A 0.87 nC Q gd Gate-to-drain charge 1.4 td(on) Turn-on delay time 4.5 ns td(off) Turn-off delay time VDD = –10 V, R L = 10 Ω ,I D = –1 A, 13 ns tr Rise time DD , R G = 6 Ω , L , See Figures 1 and 2 D , tf Fall time 2 ns trr(SD) Source-to-drain reverse recovery timeIF = 5.3 A, di/dt = 100 A/µs 16

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– 5 – 4 – 2 – 1 – 3 – Drain Current – A – 7 – 6 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 7 – 8 – 9 – 10 VGS = –6 V ÁÁ ÁÁ ID VDS – Drain-to-Source Voltage – V VGS = –8 V VGS = –7 V VGS = –3 V VGS = –4 V VGS = –2 V VGS = –5 V TJ = 25°C Figure 3 Figure 4 0 – 2 – 3 – 5 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE – 7– 1 – 4 – 6 – Drain Current – A ÁÁ ÁÁ ID VGS – Gate-to-Source Voltage – V TJ = 150°CTJ = 25°C TJ = –40°C VDS = –10 V – 5 – 4 – 2 – 1 – 3 – 7 – 6 0.3 0.2 0.1 – 0.1 – 1 0.4 0.5 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 0.6 – 10 ID – Drain Current – A 0.7 VGS = –2.7 V VGS = –3 V VGS = –4.5 V VGS = –10 V TJ = 25°C – Static Drain-to-SourcerDS(on) ΩOn-State Resistance – Figure 5 200 150 C – Capacitance – pF 250 300 CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 350 – 7 – 8 – 9 –12 100 –10 –11 C oss VDS – Drain-to-Source Voltage – V C iss† C rss‡ VGS = 0 f = 1 MHz TJ = 25°C Figure 6 C rss /C0043C gd,C oss /C0043C ds /C0041 C gs C gd C gs /C0041C gd ≈ C ds /C0041C gd‡ C iss/C0043C gs /C0041C gd,C ds(shorted)

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

– 6 – 4 – 2 02 35 – 8 GATE-TO-SOURCE VOLTAGE vs GATE CHARGE – 10 14 6 – Gate-to-Source Voltage – V Q g – Gate Charge – nC VGS VDS = –10 V ID = –1 A TJ = 25°C Figure 11

TPS1100, TPS1100Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 THERMAL INFORMATION – 1 – 0.1 – 0.001 – 10 – 0.1 – 1 – 10 – 100 – Drain Current – A DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE ID VDS – Drain-to-Source Voltage – V 0.001 s 0.01 s 0.1 s 1 s 10 s DC TJ = 150°C TA = 25°C Single Pulse See Note A Figure 12 0.1 100 0.001 0.01 0.1 1 10 TRANSIENT JUNCTION-TO-AMBIENT THERMAL IMPEDANCE vs PULSE DURATION tw – Pulse Duration – s – Transient Junction-to-AmbientZ C/W° θJA Single Pulse See Note A Thermal Impedance – Figure 13 NOTE A: Values are for the D package and are FR4-board mounted only.

APPLICATION INFORMATION

3 V or 5 V

Figure 14. Notebook Load Management Figure 15. Cellular Phone Output Drive

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