TPPM0302 TI | Alldatasheet
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400-mA LOW-DROPOUT REGULATOR WITH AUXILIARY POWER MANAGEMENT AND POK SLVS316 – NOVEMBER 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Automatic Input Voltage Source Selection /C0068Glitch-Free Regulated Output /C00685-V Input Voltage Source Detector With Hysteresis /C0068400-mA Load Current Capability With 5-V or 3.3-V Input Source /C0068Power OK Feature Based on Voltage Supervisor of 3.3VOUT /C0068Low rDS(on) Auxiliary Switch /C0068Thermally Enhanced PowerPAD Packaging Concept for Efficient Heat Management
description
The TPPM0302 is a low-dropout regulator with auxiliary power management that provides a constant 3.3-V supply at the output capable of driving a 400-mA load. The TPPM0302 provides a regulated power output for systems that have multiple input sources and require a constant voltage source with a low-dropout voltage. This is a single output, multiple input, intelligent power source selection device with a low-dropout regulator for either 5VCC or 5VAUX inputs, and a low-resistance bypass switch for the 3.3VAUX input. Transitions may occur from one input supply to another without generating a glitch, outside of the specification range, on the 3.3-V output. The device has an incorporated reverse blocking scheme to prevent excess leakage from the input terminals in the event that the output voltage is greater than the input voltage. The output voltage is continually monitored for constant output, and any deviation from the internal set limit (≈2.8 V) is reported by a low signal on the POK output. The input voltage is prioritized in the following order: 5VCC, 5VAUX, and 3.3VAUX. Copyright 2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGN PACKAGE (TOP VIEW) 5VAUX 5VCC 3.3VOUT 3.3VAUX NC GND NC POK NC – No connect PowerPAD is a trademark of Texas Instruments.
400-mA LOW-DROPOUT REGULATOR WITH AUXILIARY POWER MANAGEMENT AND POK SLVS316 – NOVEMBER 2000
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3.3VOUT 5VAUX 5VAUX Detection Current Sensor Gate Drive and Control GND 3.3VAUX 3VAUX Detection Current Sensor Low ON Resistance Switch Gate Drive5-V Detection and Control POKResetVoltage Supervisor3.3VOUT Linear Regulator With LDO Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION 3.3VAUX 4 I 3.3-V auxiliary input 3.3VOUT 3 O 3.3-V output with a typical capacitance load of 4.7 mF 5VAUX 1 I 5-V auxiliary input 5VCC 2 I 5-V main input GND 7 I Ground NC 6, 8 I No internal connection POK 5 O Power OK
Table 1. Input Selection implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND.
- Absolute negative voltage on these terminal should not be below –0.5 V.
- Refer to the Thermal Information Section.
400-mA LOW-DROPOUT REGULATOR WITH AUXILIARY POWER MANAGEMENT AND POK SLVS316 – NOVEMBER 2000
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electrical characteristics over recommended operating free-air temperature range, TA = 0°C to 70°C, CL = 4.7 mF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(5VCC)/ V(5VAUX) 5-V inputs 4.5 5 5.5 V I(Q) Quiescent supply current From 5VCC or 5VAUX terminals, IL = 0 mA to 400 mA 2.5 5 mA I(Q) Q uiescent supply current From 3.3VAUX terminal, IL = 0 A 250 500 mA IL Output load current 0.4 A I(LIMIT) Output current limit 3.3VOUT = 0 V 1 1.5 A T(TSD)† Thermal shutdown 3 3VOUT output shorted to 0 V 150 180 Thys† Thermal hysteresis 3.3VOUT output shorted to 0 V C L Load capacitance Minimal ESR to insure stability of regulated output 4.7 mF Ilkg(REV) Reverse leakage output current Tested for input that is grounded. 3.3VAUX, 5VAUX, or 5VCC = GND, 3.3VOUT = 3.3 V 50 mA † Design targets only. Not tested in production. 5-V detect PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(TO_LO) Threshold voltage, low 5VAUX or 5VCC↓ 3.85 4.05 4.25 V V(TO_HI) Threshold voltage, high 5VAUX or 5VCC↑ 4.1 4.3 4.5 V auxiliary switch PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R(SWITCH) Auxiliary switch resistance5VAUX = 5VCC = 0 V, 3.3VAUX = 3.3 V, IL = 150 mA 0.4 W DVO(DVI) Line regulation voltage 5VAUX or 5VCC = 4.5 V to 5.5 V 2 mV DVO(DIO) Load regulation voltage 20 mA < IL < 400 mA 40 mV VI – VO Dropout voltage IL < 400 mA 1 V Power OK (POK ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(TO_POK) POK threshold voltage 2.67 2.8 2.93 V VOL Output low voltage 3.3VOUT = 0 → 3.3 V and starts POK delay timer 0.4 V IOH Output high current 200 mA VOH Output high voltage 5K pullup to 3.3VOUT 3.3 V timing characteristics, TA = 0°C to 70°C, CL = 4.7 mF (unless otherwise noted)† PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Power OK delay 5VCC or 5VAUX or 3.3VAUX > VTO and POK ↑ 5 10 ms † Design targets only. Not tested in production. thermal characteristics‡ PARAMETER MIN TYP MAX UNIT R qJC Thermal impedance, junction-to-case 4.7 °C/W R qJA Thermal impedance, junction-to-ambient 59 °C/W ‡ Based on Texas Instrument recommended board for PowerPAD package.
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Figure 4. 5VCC Power Up (5VAUX = 5 V) Figure 5. 5VCC Power Up (3.3VAUX = 3.3 V) Figure 6. 5VAUX Power Up (3.3VAUX = 3.3 V) Figure 7. 5VCC Power Down (3.3VAUX = 3.3 V)
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A, and the junction power dissipation, PJ. qJA, of 59°C/W if implemented correctly. Using a multilayer board and utilizing the ground plane for heat spreading. NOTE: This curve is to be used for guideline purposes only. For a particular application, a more specific thermal characterization is required. Figure 12. Power Dissipation Derating Curve
400-mA LOW-DROPOUT REGULATOR WITH AUXILIARY POWER MANAGEMENT AND POK SLVS316 – NOVEMBER 2000
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APPLICATION INFORMATION
In a multilayer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors (die area, number of thermal vias, thickness of copper) Consult the PowerPAD Thermally Enhanced Package Technical Brief. single-layer PCB Package Outline Use as Much Copper Area as Possible for Heat Spread Package Thermal Pad Figure 15. Land Configuration for Single-layer PCB thermal impedance attachment method (solder paste or thermal conductive epoxy). mounted onto the circuit board. Figure 16. Typical Application Schematic
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPPM0302DGN Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 APF TPPM0302DGN.A Active Production HVSSOP (DGN) | 8 80 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 APF (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPPM0302DGN DGN HVSSOP 8 80 331.47 6.55 3000 2.88 TPPM0302DGN.A DGN HVSSOP 8 80 331.47 6.55 3000 2.88 Pack Materials-Page 1
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. PowerPAD HVSSOP - 1.1 mm max heightDGN 8 SMALL OUTLINE PACKAGE3 x 3, 0.65 mm pitch 4225482/B TM
www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05
4.75 TYP
0.15 0.05 0.25 GAGE PLANE 0 -8
1.1 MAX
0.23 0.13 1.57 1.28 1.89 1.63 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 PowerPAD VSSOP - 1.1 mm max heightDGN0008D SMALL OUTLINE PACKAGE 4225481/A 11/2019
0.13 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. TM A 20 DETAIL A TYPICAL SCALE 4.000 EXPOSED THERMAL PAD
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP (2) NOTE 9 (3) NOTE 9 (1.22) (0.55) ( 0.2) TYP VIA (1.57) (1.89) PowerPAD VSSOP - 1.1 mm max heightDGN0008D SMALL OUTLINE PACKAGE 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SOLDER MASK DEFINED PAD METAL COVERED BY SOLDER MASK SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP (1.57) BASED ON
0.125 THICK
(1.89) BASED ON PowerPAD VSSOP - 1.1 mm max heightDGN0008D SMALL OUTLINE PACKAGE 4225481/A 11/2019 1.33 X 1.600.175 1.43 X 1.730.15 1.57 X 1.89 (SHOWN)0.125 1.76 X 2.110.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X SYMM SYMM 4 5 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES
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