TPPM0115DG4

TPPM0115_08 TI1 | Alldatasheet

Document overview

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Technical content

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

/C0068DC-DC Synchronous Buck Controller /C0068Switching Frequency, 200 kHz (Typ) /C0068Programmable Output Voltage, 1 V to 2.5 V ±2% /C0068Power Good Function (PWRGD) /C0068Input Voltage, 12 V ±5% /C0068Drive High Load Current With External Components

applications

/C0068PC Motherboard, Voltage Regulation for System Power /C0068DDR Memory Supply (VDDQ or VTT) /C0068RDRAM Memory Supply (V DDQ ) /C0068General Purpose Synchronous Switch Mode Controller

description

The TPPM0115 is a synchronous buck controller capable of driving two external power FETs 180° out of phase. The device requires a minimum of external standard filter components and switching FETs to regulate the desired output voltage. This is achieved with an internal switching frequency of 200 kHz (typical). The TPPM0115 switch mode controller and associated circuitry provide efficient voltage regulation of greater than 85%. The output voltage is set by two external resistors. During power up, when the output voltage reaches 90% of the desired value, the power good (PWRGD) output is transitioned high after a short delay of 1 ms to 5 ms. During power down, when the output voltage falls below 90% of the set value, the PWRGD output is pulled low without any delay. In the event the set output is in an over-voltage condition due to a system fault, the drive to the lower FET turns on to correct the fault. There is a dead time between switching one FET ON while the other FET is switching OFF to prevent cross conduction. The TPPM0115 is capable of driving high static load currents with minimal ripple on the output (<2%). The phase sense input is used to sense the flow of current through the inductor during flyback to minimize ripple on the output. To optimize output filter capacitance, the voltage mode control is based on a fixed ON time during the start of the cycle and hysteretic control during load transients. This allows the device to respond and maintain the set regulation voltage. Copyright  2001, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NC − No internal connection VCC PWRGD NC PHASE GND SEN DRVL DRVH SO (D) PACKAGE (TOP VIEW)

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001

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+ 1-V Ref Logic Voltage Reference Power Good Control VCC GND PWRGD DRVH DRVL PHASE SEN PWRGD Ref Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION DRVH 5 O Output for upper FET gate drive DRVL 6 O Output for lower FET gate drive GND 8 O Ground NC/TEST 3 O No connection, used for test purpose only PHASE 4 I Phase sense input PWRGD 2 O Open-drain output for power good function SEN 7 I Sense input VCC 1 I Input voltage

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Absolute negative voltage values on these terminals should not be below −0.5 V. 3. Absolute negative voltage values on these terminals should not be below −1 V. 4. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal. recommended operating conditions MIN NOM MAX UNIT Unregulated input voltage, VCC 11.4 12.6 V Drive output current, I(DRVH) and I(DRVL) 500 mA Power good voltage, V(PWRGD) 5 V Feedback voltage, V(SEN) 1 V Phase sense voltage, V(PHASE) 0 V Continuous power dissipation, PD 100 mW Operating ambient temperature, TA 55 °C

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001

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dc electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT Output voltage VCC = 11.4 V to 12.6 V, IL = 5 A to 10 A, See Figure 8 for external components, R 1 = 0, R2 is not present 1 V η Efficiency IL = 10 A, See Figure 8 86% IQ Quiescent current V(SEN) = <1 V or >1.3 V, VOUT = 1 V to 1.3 V 2 mA ∆VO(∆IO) Load regulation ∆VO(∆VI) Line regulation See Figure 8 −1% 1% Temperature regulation See Figure 8 −1% 1% VOH(DRVH) Upper drive output voltage V(SEN) = 0.9 V, IOH = 200 mA VCC −3V VVOL(DRVH) Upper drive output voltage V(SEN) = 1.2 V, IOL = −200 mA 1 V VOH(DRVL) Lower drive output voltage V(SEN) = 1.2 V, V(PHASE) < 0 V IOH = 200 mA 5 V VOL(DRVL) Lower drive output voltage V(SEN) = 0.9 V, IOL = −200 mA 1 V IIH Phase input current V(SEN) = 0.9 V, V(PHASE) = 5 V 100 AIIL Phase input current V(SEN) = 1.2 V, V(PHASE) = −0.3 V −50 µA V(PWRGD) Sense output voltage for Ramp up sense input until PWRGD transition to high VOUT * 0.86 VOUT* 0.96 VV(PWRGD) Sense output voltage for PWRGD detection range Ramp down sense input until PWRGD transition to low VOUT* 0.63 VOUT* 0.71 V IBIAS Sense feedback bias current V(SEN) = 1.08 V 5 µA ac electrical characteristics, TA = 0°C to 55°C, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fsw Switching frequency Measured at DRVH terminal 200 kHz tr Output rise time for both DRVH and DRVL V(DRVH) → 0 V to 8 V, V(SEN) → 1.1 V to 0.9 V 50 nstr Output rise time for both DRVH and DRVLV(DRVL) → 0 V to 8 V, V(SEN) → 0.9 V to 1.1 V 50 ns tf Output fall time for both DRVH and DRVL V(DRVH) → 8 V to 0 V, V(SEN) → 0.9 V to 1.1 V 50 nstf Output fall time for both DRVH and DRVLV(DRVL) → 8 V to 0 V, V(SEN) → 1.1 V to 0.9 V 50 ns td Power good signal delay Delay time for V(SEN) >V(PWRGD) to PWRGD transitioning high 1 5 ms tdt Dead time between DRVH and DRVL V(SEN) → 1.1 V to 0.9 V, Delay between V(DRVL) at 0 V and V(DRVH) = 1.5 V 50 nstdt Dead time between DRVH and DRVL switch conduction V(SEN) → 0.9 V to 1.1 V, Delay between V(DRVH) at 0 V and V(DRVL) = 1.5 V 50 ns thermal characteristics MIN TYP MAX UNIT R θJC Thermal impedance, junction-to-case 50 °C/W R θJA Thermal impedance, junction-to-ambient 178 °C/W

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Figure 3. Output Voltage Ripple (Offset = 2.5 V) With NO Load Figure 4. Output Voltage Ripple (Offset = 2.5 V) With 6 A Load

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Figure 7. System Efficiency With Load Current (2.5-V Output)

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

20 kΩ VDD 1 µF 12 V Supply PWRGD TPPM0115 DRVH PHASE DRVL GND SEN 4 µH Optional 0.1 µF 4.7 µF 1 V to 2.5 V 0.1 µF 4.7 µF 5 V 1.7 µH NOTES: A. The heavy lines must be kept short and connected to the ground plane construction for efficient results. B. The feedback (sense) trace should be kept from the inductor flux. C. The 1500-µF capacitor should have a low ESR to minimize output voltage ripple. D. External FETs are MTD3302 or PHD55N03LT. E. Set the resistor values on the SEN terminal using the following formulas: F. Maximum efficiency is dependent on proper selection of external components. G. Line and load regulation is dependent on proper selection of external components. Optional: When resistor feedback network is not used, VOUT must be connected directly to SEN input to provide output regulation at VOUT = Vref. 4.7 µF 2200 µF 2200 µF 680 pF 1500 µF Low ESR 1500 µF Low ESR VOUT VOUT /C0043 V ref(R1/C0041R2) , where Vref/C00431V 2.2 Ω 4.7 nF Figure 8. Typical Application Schematic

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001

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1 µF VCC 1.7 µH 4 µH 2.2 Ω20 kΩ 250 Ω 1 kΩ 50 Ω 50 Ω DDQ VCC 1 µF 0.1 µF V1P25MEM V TT P-Channel0.1 µF 4.7 µF 220 µF Low ESR 220 µF Low ESR 0.1 µF 4.7 µF 4.7 µF 1000 µF 1000 µF 0.1 µF 4.7 µF 1500 µF Low ESR1500 µF Low ESR VCC NOTES: A. The heavy lines must be kept short and connected to the ground plane construction for efficient results. B. The performance of the regulator depends on the proper selection of the external components for the application. Figure 9. Application Schematic for DDR Memory VDDQ and VTT Supplies

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 µF VCC 1.7 µH 0.1 µF 4.7 µF 4.7 µF 1000 µF 1000 µF 4 µH 2.2 Ω20 kΩ 250 Ω 1 kΩ 0.1 µF 4.7 µF 1500 µF Low ESR1500 µF Low ESR DDQ VCC VCORE P-Channel0.1 µF 4.7 µF 220 µF Low ESR 300 Ω 450 Ω 175 Ω 0.1 µF 1 µF J1: 1 and 2 = 1.8 V VCORE J1: 2 and 3 = 1.5 V VCORE VCC NOTES: A. The heavy lines must be kept short and connected to the ground plane construction for efficient results. B. The performance of the regulator depends on the proper selection of the external components for the application. Figure 10. Application Schematic for RAMBUS Memory VDDQ and VCORE Supplies

/C0084/C0080/C0080/C0077/C0048/C0049/C0049/C0053 /C0083/C0087/C0073/C0084/C0067/C0072 /C0077/C0079/C0068/C0069 /C0083/C0089/C0078/C0067/C0072/C0082/C0079/C0078/C0079/C0085/C0083 /C0066/C0085/C0067/C0075 /C0067/C0079/C0078/C0084/C0082/C0079/C0076/C0076/C0069/C0082 SLVS371A− MARCH 2001 − REVISED JUNE 2001

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D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

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