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µC GPIO VDD GND TPL5110-Q1 VDD GND EN/ ONE_SHOT DRV DELAY/ M_DRV DONE REXT Battery - + Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL5110-Q1 SNAS681 – FEBRUARY 2017 TPL5110-Q1AEC-Q100Nano-PowerSystemTimerforPowerGating

1 Features

1• Qualified for Automotive Applications

AEC-Q100 Qualified with the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C5
Current Consumption of 35nA (typ) at 2.5V
Supply Voltage from 1.8V to 5.5V
Selectable Time Intervals 100ms to 7200s
Timer Accuracy 1% (typ)
Resistor Selectable Time Interval
Manual MOSFET Power On
One-Shot Feature
TPL5x10Q Family of AEC-Q100 Nano-Power System Timers: – TPL5010-Q1:Watchdog Function with Programmable Delay Range – TPL5110-Q1: MOS-Driver with Programmable Delay Range and One-Shot Feature

2 Applications

Electric Vehicles
Battery Powered Systems
Clutch Actuator Circuit
Car Door Handle Circuit
Smart Key
Remote Current Sensor
Intruder Detection

3 Description

The TPL5110-Q1 Nano Timer is a low power, AEC- Q100 qualified timer with an integrated MOSFET driver ideal for power gating in duty cycled or battery powered applications. Consuming only 35nA, the TPL5110-Q1 can enable the power supply line and drastically reduce the overall system stand by current during the sleep time. Such power savings enable the use of significantly smaller batteries making it well suited for energy harvesting or wireless sensor applications. The TPL5110-Q1 provides selectable timing intervals from 100ms to 7200s and is designed for power gating applications. In addition, the TPL5110-Q1 has a unique One-shot feature where the timer will only power the MOSFET for one cycle. The TPL5110-Q1 is available in a 6-pin SOT23 package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPL5110-Q1 SOT23 (6) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Schematic

12.1 Receiving Notification of Documentation Updates 20

13 Mechanical, Packaging, and Orderable

4 Revision History

February 2017 * Initial release.

5 Device Comparison Table

Table 1. TPL5x10Q Family of AEC-Q100 Nano- Power System Timers

ONE_SHOT DRV DELAY/ M_DRV DONE 3 4 TPL5110-Q1 SNAS681 – FEBRUARY 2017 www.ti.com Product Folder Links: TPL5110-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) G= Ground, P= Power, O= Output, I= Input.

6 Pin Configuration and Functions

TYPE(1) DESCRIPTION APPLICATION INFORMATION NO. NAME

1 VDD P Supply voltage

2 GND G Ground

3 DELAY/

M_DRV I Time interval set and manual MOSFET Power ON Resistance between this pin and GND is used to select the time interval. The manual MOSFET power ON switch is also connected to this pin.

4 DONE I Logic Input for watchdog

Digital signal driven by the µC to indicate successful processing.

5 DRV O Power Gating output signal

The Gate of the MOSFET is connected to this pin. When DRV = LOW, the MOSFET is ON.

6 EN/

ONE_SHOT I Selector of mode of operation When EN/ONE_SHOT = HIGH, the TPL5110-Q1 works as a TIMER. When EN/ONE_SHOT = LOW, the TPL5110-Q1 turns on the MOSFET one time for the programmed time interval. The next power on of the MOSFET is enabled by the manual power ON.

www.ti.com SNAS681 – FEBRUARY 2017 Product Folder Links: TPL5110-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) (3) The voltage between any two pins should not exceed 6V. (4) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Supply voltage (VDD-GND) -0.3 6.0 V Input voltage at any pin(3) -0.3 VDD + 0.3 V Input Current on any pin -5 +5 mA Storage temperature, Tstg -65 150 °C Junction temperature, TJ(4) 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JADEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human Body Model, per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±750

7.3 Recommended Operating Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply Voltage (VDD-GND) 1.8 5.5 V Temperature Range –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) TPL5110-Q1 UNITSOT-23

6 PINS

RθJA Junction-to-ambient thermal resistance 163 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26 °C/W RθJB Junction-to-board thermal resistance 57 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 57 °C/W

SNAS681 – FEBRUARY 2017 www.ti.com Product Folder Links: TPL5110-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Electrical Characteristics Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD. (5) This parameter is specified by design and/or characterization and is not tested in production. (6) The accuracy for time interval settings below 1second is ±100ms. (7) Operational life time test procedure equivalent to10 years.

7.5 Electrical Characteristics(1)

Specifications are for TA= 25°C, VDD-GND=2.5 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT POWER SUPPLY IDD Supply current(4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP Time interval Period(5) 1650 selectable Time intervals Min time interval 100 ms Max time interval 7200 s Time interval Setting Accuracy(6) Excluding the precision of Rext ±0.6% Time interval Setting Accuracy over supply voltage 1.8V ≤ VDD ≤ 5.5V ±25 ppm/V tOSC Oscillator Accuracy –0.5% 0.5% Oscillator Accuracy over temperature(5) –40°C ≤ TA≤ 125°C 150 ppm/°C Oscillator Accuracy over supply voltage(5) Oscillator Accuracy over life time(7) ±0.24% tDONE Minimum DONE Pulse width (5) 100 ns tDRV DRV Pulse width DONE signal not received tIP–50ms t_Rext Time to convert Rext (5) 100 ms DIGITAL LOGIC LEVELS VIH Minimum Logic High Threshold DONE pin 0.7xVDD V VIL Maximum Logic Low Threshold DONE pin 0.3xVDD V VOH Logic output High Level DRV pin Iout = 100 µA VDD–0.3 V Iout = 1 mA VDD–0.7 V VOL Logic output Low Level DRV pin Iout = –100 µA 0.3 V Iout = –1 mA 0.7 V VIHM_DRV Minimum Logic High Threshold DELAY/M_DRV pin (5) 1.5 V

correlations using statistical quality control (SQC) method. (3) This parameter is specified by design and/or characterization and is not tested in production.

7.6 Timing Requirements

Figure 1. TPL5110-Q1 Timing

7.7 Typical Characteristics

Figure 2. IDD vs. VDD Figure 3. IDD vs. Temperature Figure 4. Oscillator Accuracy vs. VDD Figure 5. Oscillator Accuracy vs. Temperature Figure 6. IDD vs. Time Figure 7. Time Interval Setting Accuracy

ONE_SHOT DRV VDD GND DELAY/ M_DRV DECODER MANUAL RESET DETECTOR LOGIC CONTROL DONE TPL5110-Q1 www.ti.com SNAS681 – FEBRUARY 2017 Product Folder Links: TPL5110-Q1 Submit Documentation FeedbackCopyright © 2017, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The TPL5110-Q1 is a timer with power gating feature. It is ideal for use in power-cycled applications and provides selectable timing from 100ms to 7200s. Once configured in timer mode (EN/ONE_SHOT= HIGH) the TPL5110-Q1 periodically sends out a DRV signal to a MOSFET to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the TPL5110-Q1 turns off the µC, otherwise the TPL5110-Q1 keeps the µC in the on state for a time equal to tDRV. The TPL5110-Q1 can work also in a one shot mode (EN/ONE_SHOT= LOW). In this mode the DRV signal is sent out just one time at the power on of the TPL5110-Q1 to turn on the µC. If the µC replies with a DONE signal within the programmed time interval (tDRV) the TPL5110-Q1 turns off the µC, otherwise the TPL5110-Q1 keeps the µC in the on state for a time equal to tDRV.

8.2 Functional Block Diagram

8.3 Feature Description

The TPL5110-Q1 implements a periodical power gating feature or one shot power gating according to the EN/ONE_SHOT voltage. A manual MOSFET Power ON function is realized by momentarily pulling the DELAY/M_DRV pin to VDD.

8.3.1 DRV

The gate of the MOSFET is connected to the DRV pin. When DRV= LOW, the MOSFET is turned ON. The pulse generated at DRV is equal to the selected time interval period, minus 50ms. It is shorter in the case of a DONE signal received from the µC. If the DONE signal is not received within the programmed time interval (minus 50ms), the DRV signal will be high for the last 50ms of the time interval in order to turn off the MOSFET before the next cycle starts. The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110-Q1 when the programmed time interval starts. When the DRV is LOW, the manual power ON signal is ignored.

8.3.2 DONE

The DONE pin is driven by a µC to signal that the µC is working properly. The TPL5110-Q1 recognizes a valid DONE signal as a low to high transition; if two or more DONE signals are received within the time interval, only the first DONE signal is processed. The minimum DONE signal pulse length is 100ns. When the TPL5110-Q1 receives the DONE signal it asserts DRV logic HIGH.

8.4 Device Functional Modes

8.4.1 Startup

DELAY/M_DRV pin in order to determine the desired time interval for DRV. This measurement interval is tR_EXT. During this measurement a constant current is temporarily flowing into REXT. according to the required mode of operation. Figure 8. Startup - Timer mode

8.4.2 Timer Mode

programmed time interval. The length of the DRV pulses is set by the receiving of a DONE pulse from the uC.

8.4.3 One Shot Mode

Q1 generates just one pulse at the DRV pin. The duration of the pulse is set by the programmed time interval. connected to the DRV pin is turned off. See Figure 9 and Figure 10. Figure 9. Startup One Shot Mode, (DONE Received Within tIP)

Figure 10. Startup One Shot Mode, (No DONE Received Within tIP)

8.5 Programming

8.5.1 Configuring the Time Interval with the DELAY/M_DRV Pin

External Resistance on how to set the time interval using REXT.

8.5.2 Manual MOSFET Power ON Applied to the DELAY/M_DRV Pin

may be implemented using a switch (momentary mechanical action). If the DRV is already LOW (MOSFET ON) the manual MOSFET Power ON is ignored. Figure 11. Manual MOSFET Power ON in Timer Mode

Figure 12. Manual MOSFET Power ON in One Shot Mode

8.5.2.1 DELAY/M_DRV

switched off and the DELAY/M_DRV is connected to a digital circuit. the TPL5110-Q1 insensitive to the glitches on the DELAY/M_DRV. programmed time interval (minus 50ms), or less if the DONE is received. is already LOW (MOSFET ON) the manual power ON is ignored.

8.5.2.2 Circuitry

offers 2 possible approaches according to the power consumption constraints of the application.

Figure 13. Manual MOSFET Power ON with SPST Switch offer a lower cost solution. The DELAY/M_DRV pin may be directly connected to VDD with REXT in the circuit. The current drawn from the supply voltage during the manual power ON is given by VDD/REXT. Figure 14. Manual MOSFET Power ON with SPDT Switch

8.5.3 Selection of the External Resistance

T is the desired time interval in seconds.
REXT is the resistance value to use in Ω.
a,b,c are coefficients depending on the range of the time interval.

Table 2. Coefficients for Equation 1 The resistance value is 10.18 kΩ. The following Look-Up-Tables contain example values of tIP and their corresponding value of REXT. Table 3. First 9 Time Intervals Table 4. Most Common Time Intervals Between 1s to 2h

Table 4. Most Common Time Intervals Between 1s to 2h (continued)

8.5.4 Quantization Error

discrete intervals, there is a quantization error associated with each value. REXT is the resistance calculated with Equation 1 and a,b,c are the coefficients of the equation listed in Table 2.

8.5.5 Error Due to Real External Resistance

are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.

Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial

resistance values and their tolerances.

Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with Equation 4.
Find the errors using Equation 3 with TADC_MIN, TADC_MAX.

The results of the formula indicate the accuracy of the time interval. The example below illustrates the procedure.

Desired time interval , T_desired = 600s,

Required REXT, from Equation 1, REXT= 57.44kΩ. From Table 4 REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1=107kΩ, R2=124kΩ. The uncertainty of the equivalent parallel resistance can be found using: (6) Where uRn (n=1,2) represent the uncertainty of a resistance, (7) The uncertainty of the parallel resistance is 0.82%, meaning the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. Using these value of REXT, the digitized timer intervals calculated with Equation 4 are respectively TADC_MIN = due to the quadratic transfer function of the resistance digitizer.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

is suitable in applications where there is a need to monitor environmental conditions at a fixed time interval. Often in these applications a watchdog or other internal timer in a µC is used to implement a wakeup function. periodical power gating of the µC or of the entire system the current consumption will be only tens of nA.

9.2 Typical Application

programmed time interval elapses or for debug purpose with the manual MOSFET Power ON switch. Figure 15. Sensor Node

9.2.1 Design Requirements

Q1 helps achieve this goal because it allows turning off the RF micro.

9.2.2 Detailed Design Procedure

appropriate time interval which respect the application constraint and maximize the life of the battery.

9.2.3 Application Curves

Figure 16. Effect of TPL5110-Q1 on Current Consumption

10 Power Supply Recommendations

0.1μF between VDD and GND pin is recommended.

11 Layout

11.1 Layout Guidelines

capacitance. The EN/ONE_SHOT needs to be tied to GND or VDD with short traces.

11.2 Layout Example

Figure 17. Layout

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 7-Feb-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPL5110QDDCRQ1 PREVIEW SOT DDC 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 13ZX TPL5110QDDCTQ1 PREVIEW SOT DDC 6 250 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 13ZX (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 7-Feb-2017 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPL5110-Q1 :

Catalog: TPL5110 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL5110QDDCRQ1 SOT DDC 6 3000 210.0 185.0 35.0 TPL5110QDDCTQ1 SOT DDC 6 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Feb-2017 Pack Materials-Page 2

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Product Information

TPL5110QDDCTQ1 specifications and overview.

Summary

AEC-Q100 Nano-Power System Timer for Power Gating

Description

AEC-Q100 Nano-Power System Timer for Power Gating

Source title TPL5110QDDCTQ1 Datasheet(PDF) - Texas Instruments

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