TPL5010-Q1 TI1 | Alldatasheet
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µC GPIO VDD GND Rp GPIO RSTn TPL5010-Q1 VDD GND RSTn WAKE DELAY/ M_RST DONE REXT Battery - + Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL5010-Q1 SNAS679 – SEPTEMBER 2016 TPL5010-Q1AEC-Q100Nano-PowerSystemTimerwithWatchdogFunction
1 Features
1• Qualified for Automotive Applications
- AEC-Q100 Qualified with the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C5
- Current Consumption of 35 nA (typ) at 2.5 V
- Supply Voltage from 1.8 V to 5.5 V
- Selectable Time Intervals 100 ms to 7200 s
- Timer Accuracy 1% (Typical)
- Resistor Selectable Time Interval
- Watchdog Functionality
- Manual Reset
- TPL5x10Q Family of AEC-Q100 Nano-Power System Timers
- TPL5010-Q1 - Supply Current 35 nA – Low Power Timer – Watchdog Function – Programmable Delay Range – Manual Reset
- TPL5110-Q1 - Supply Current 35 nA – Low Power Timer – MOS-Driver – Programmable Delay Range – Manual Reset – One-Shot Feature
2 Applications
- Electric Vehicles
- Always On Systems
- Battery powered systems
- Clutch Actuator circuit
- Car Door Handle circuit
- Smart Key
- Remote current sensor
- Intruder Detection
3 Description
The TPL5010-Q1 Nano Timer is a low power, AEC- Q100 qualified timer with a watchdog feature ideal for system wake up in duty cycled or battery powered applications. In such systems the microcontroller timer can be used for system wake-up, but if the timer sleep current is high, up to 60-80% of the total system current can be consumed by the microcontroller timer in this sleep mode. Consuming only 35 nA, the TPL5010-Q1 can replace the functionality of the integrated microcontroller timer and allow the microcontroller to be placed in a much lower power mode. Such power savings extend the operating life of batteries and enable the use of significantly smaller batteries making the TPL5010- Q1 ideal for power sensitive applications.. The TPL5010-Q1 provides selectable timing intervals from 100 ms to 7200 s and is designed for interrupt-driven applications. Some standards (such as EN50271) require implementation of a watchdog for safety and the TPL5010-Q1 realizes this watchdog function at almost no additional power consumption. The TPL5010-Q1 is available in a 6-pin SOT23 package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPL5010-Q1 SOT23 (6) 3.00 mm x 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application
SNAS679 – SEPTEMBER 2016 www.ti.com Product Folder Links: TPL5010-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table of Contents
12.1 Receiving Notification of Documentation Updates 18
13 Mechanical, Packaging, and Orderable
4 Revision History
September 2016 * Initial release.
5 Device Comparison Table
TPL5x10Q Family of AEC-Q100 Nano- Power System Timers PART NUMBER SUPPLY CURRENT (Typ) SPECIAL FEATURES TPL5010-Q1 35 nA Low Power Timer Watchdog Function Programmable Delay Range Manual Reset TPL5110-Q1 35 nA Low Power Timer MOS-Driver Programmable Delay Range Manual Reset One-Shot Feature
(1) G= Ground, P= Power, O= Output, I= Input.
6 Pin Configuration and Functions
Table 1. Pin Functions
1 VDD P Supply voltage
2 GND G Ground
3 DELAY/
4 DONE I Logic Input for watchdog functionality Digital signal driven by the µC to indicate successful
processing of the WAKE signal.
5 WAKE O Timer output signal generated every tIP
the programmed time interval.
6 RSTn O Reset Output (open drain output) Digital signal to RESET the µC, pull-up resistance is
SNAS679 – SEPTEMBER 2016 www.ti.com Product Folder Links: TPL5010-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage between any two pins should not exceed 6V. (3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage (VDD-GND) –0.3 6.0 V Input voltage at any pin(2) –0.3 VDD + 0.3 V Input current on any pin –5 5 mA Tstg Storage temperature –65 150 °C TJ Junction temperature(3) 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model, per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q10-011 ±750
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage (VDD-GND) 1.8 5.5 V Temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) TPL5010-Q1 UNITSOT23
6 PINS
RθJA Junction-to-ambient thermal resistance 163 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26 °C/W RθJB Junction-to-board thermal resistance 57 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 57 °C/W
www.ti.com SNAS679 – SEPTEMBER 2016 Product Folder Links: TPL5010-Q1 Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated (1) Values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pull-up resistor current. Input pins are at GND or VDD. (5) This parameter is specified by design and/or characterization and is not tested in production. (6) The accuracy for time interval settings below 1 second is ±100 ms. (7) Operational life time test procedure equivalent to 10 years.
7.5 Electrical Characteristics
TA= 25°C, VDD-GND=2.5 V (unless otherwise stated)(1) PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT POWER SUPPLY IDD Supply current(4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP Time interval period(5) 1650 selectable time Intervals Min time interval 100 ms Max time interval 7200 s Time interval setting accuracy(6) Excluding the precision of Rext ±0.6% Timer interval setting accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V tOSC Oscillator accuracy –0.5% 0.5% Oscillator accuracy over temperature(5) -40°C ≤ TA ≤ 125°C 150 ppm/°C Oscillator accuracy over supply voltage(5) Oscillator accuracy over life time(7) 0.24% tDONE Minimum DONE pulse width (5) 100 ns tRSTn RSTn pulse width 320 ms tWAKE WAKE pulse width 20 ms t_Rext Time to convert Rext(5) 100 ms DIGITAL LOGIC LEVELS VIH Minimum logic high threshold DONE pin 0.7 × VDD V VIL Maximum logic low threshold DONE pin 0.3 × VDD V VOH Logic output high-level WAKE pin Iout = 100 µA VDD – 0.3 V Iout = 1 mA VDD – 0.7 V VOL Logic output low-level WAKE pin Iout = –100 µA 0.3 V Iout = –1 mA 0.7 V VOLRSTn RSTn logic output low-level IOL= –1 mA 0.3 V IOHRSTn RSTn high-level output current VOHRSTn = VDD 1 nA VIHM_RST Minimum logic high threshold DELAY/M_RST pin(5) 1.5 V
correlations using statistical quality control (SQC) method. (3) This parameter is specified by design and/or characterization and is not tested in production. (4) In case of RSTn from its falling edge, in case of WAKE, from its rising edge.
7.6 Timing Requirements
Figure 1. TPL5010-Q1 Timing
7.7 Typical Characteristics
Figure 2. IDD vs VDD Figure 3. IDD vs Temperature Figure 4. Oscillator Accuracy vs VDD Figure 5. Oscillator Accuracy vs Temperature Figure 6. IDD vs Time Figure 7. Time Interval Setting Accuracy
8 Detailed Description
8.1 Overview
Q1 is ideal for use in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.
8.2 Functional Block Diagram
8.3 Feature Description
next WAKE pulse. If the DONE signal is not asserted, the TPL5010-Q1 asserts the RSTn signal to reset the µC. A manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD. Figure 8. Watchdog
8.3.1 WAKE
beginning of the first cycle or if in the previous interval the DONE has not been received). This signal is normally low.
8.3.2 DONE
time interval, only the first DONE signal is processed. high, the WAKE will go low as soon as the DONE is recognized.
8.3.3 RSTn
recommended, to minimize current. During the POR and the reading of the REXT the RSTn signal is LOW.
- 1. If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately 20 ms).
- 2. At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising edge (see Figure 8).
8.4 Device Functional Modes
8.4.1 Startup
tR_EXT. During this measurement a constant current is temporarily flowing into REXT. Figure 9. Startup
8.4.2 Normal Operating Mode
internal counters. See Figure 8 and Figure 10 .
8.5 Programming
8.5.1 Configuring the WAKE Interval with the DELAY/M_RST Pin
Timer Interval Selection Using External Resistance for how to set the WAKE pulse interval using REXT. (rising edge) is given by the sum of the programmed time interval and the tRSTn (reset pulse width).
8.5.2 Manual Reset
digital voltage at DELAY/M_RST is removed and the next tRSTn is elapsed. Figure 10. Manual Reset
8.5.2.1 DELAY/M_RST
DELAY/RST is connected to a digital circuit. of the RSTn signal maybe affected by an uncertainty of about ±5 ms.
- WAKE = LOW
- RSTn = asserted LOW
8.5.2.2 Circuitry
possible approaches according to the power consumption constraints of the application.
Figure 11. Manual Reset with SPST Switch offer a lower cost solution. The DELAY/M_RST pin may be directly connected to VDD with REXT in the circuit. The current drawn from the supply voltage during the reset is given by VDD/REXT. Figure 12. Manual Reset with SPDT Switch double throw switch, which will provide a lower power solution for the manual reset, because no current flows.
8.5.3 Timer Interval Selection Using External Resistance
- T is the desired time interval in seconds
- REXT is the resistance value to use in Ω
- a, b, c are coefficients depending on the range of the time interval (1)
Table 2. Coefficients for Equation 1 The resistance value is 10.18 kΩ. Table 3 and Table 4 contain example values of tIP and their corresponding value of REXT. Table 3. First 9 Time Intervals Table 4. Most Common Time Intervals Between 1 s to 2 h
Table 4. Most Common Time Intervals Between 1 s to 2 h (continued)
8.5.4 Quantization Error
they are discrete intervals, there is a quantization error associated with each value.
- REXT is the resistance calculated with Equation 1
- a, b, c are the coefficients of the equation listed in Table 2 (5)
8.5.5 Error Due to Real External Resistance
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
- Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial
resistance values and their tolerances.
- Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with Equation 4.
- Find the errors using Equation 3 with TADC_MIN, TADC_MAX.
The results of the formula indicate the accuracy of the time interval.
//// 21 ¸ § R u R uRuR RR TPL5010-Q1 SNAS679 – SEPTEMBER 2016 www.ti.com Product Folder Links: TPL5010-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated The example below illustrates the procedure.
- Desired time interval , T_desired = 600 s
- Required REXT, from Equation 1, REXT= 57.44 kΩ From Table 4, REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1=107 kΩ, R2=124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 6. (6) Where uRn (n=1,2) represent the uncertainty of a resistance, (7) The uncertainty of the parallel resistance is 0.82%, meaning the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. Using these value of REXT, the digitized timer intervals calculated with Equation 4 are respectively TADC_MIN = due to the quadratic transfer function of the resistance digitizer.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
power consumption of the system.
9.2 Typical Application
sensor based on the LMP91000. Figure 13. Data-Logger
9.2.1 Design Requirements
care of the watchdog and the timing.
9.2.2 Detailed Design Procedure
application constraints and maximize the life of the battery.
9.2.3 Application Curves
Figure 14. Effect of TPL5010-Q1 on Current Consumption
10 Power Supply Recommendations
0.1 μF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
11.2 Layout Example
Figure 15. Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 16-Sep-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPL5010QDDCRQ1 ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 13VX TPL5010QDDCTQ1 ACTIVE SOT DDC 6 250 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 13VX (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 16-Sep-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPL5010-Q1 :
- Catalog: TPL5010 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
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