TPL5010 TI | Alldatasheet
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Technical content
µC GPIO VDD GND Rp GPIO RSTn TPL5010 VDD GND RSTn WAKE DELAY/ M_RST DONE REXT Battery - + Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL5010 SNAS651A – JANUARY 2015–REVISED SEPTEMBER 2018 TPL5010Nano-PowerSystemTimerWithWatchdogFunction
1 Features
1• Supply Voltage From 1.8 V to 5.5 V
- Current Consumption at 2.5 V and 35 nA (Typical)
- Selectable Time Intervals: 100 ms to 7200 s
- Timer Accuracy: 1% (Typical)
- Resistor Selectable Time Interval
- Watchdog Functionality
- Manual Reset
2 Applications
- Battery-Powered Systems
- Internet of Things (IoT)
- Intruder Detection
- Tamper Detection
- Home Automation Sensors
- Thermostats
- Consumer Electronics
- Remote Sensors
- White Goods
3 Description
The TPL5010 Nano Timer is an ultra-low power timer with a watchdog feature designed for system wake up in duty-cycled, battery-powered applications such as those in IoT. Many of these applications require the use of a μC, so it is desirable to keep the μC in a low power mode to maximize current savings, waking up only during certain time intervals to collect data or service an interrupt. Although the internal timer of the μC can be used for system wake-up, it can single- handedly consume microamps of total system current. Consuming only 35 nA, the TPL5010 can replace the functionality of the integrated μC timer. This allows the μC to be placed in a much lower power mode, with the internal timer off, returning only to active mode upon an interrupt by the TPL5010. By offering power savings of almost two orders of magnitude, the TPL5010 enables the use of significantly smaller batteries for energy harvesting or wireless sensor applications. The TPL5010 provides selectable timing intervals from 100 ms to 7200 s and is designed for interrupt-driven applications. Some standards (such as EN50271) require implementation of a watchdog for safety and the TPL5010 realizes this watchdog function at almost no additional power consumption. The TPL5010 is available in a 6-pin SOT23 package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPL5010 SOT23 (6) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Schematic
SNAS651A –JANUARY 2015– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TPL5010 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated Table of Contents
12.1 Receiving Notification of Documentation Updates 19
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (January 2015) to Revision A Page
www.ti.com SNAS651A – JANUARY 2015– REVISED SEPTEMBER 2018 Product Folder Links: TPL5010 Submit Documentation FeedbackCopyright © 2015–2018, Texas Instruments Incorporated
5 Device Comparison Table
TPL5x1x Family of Nano Timers PART NUMBER Special Features Output Rating TPL5010 Low Power Timer, Watchdog Functionality Active High Catalog TPL5010Q Low Power Timer, Watchdog Functionality Active High Automotive TPL5111 Low Power Timer, Power Gating MOS-Driver Active High Catalog TPL5110 Low Power Timer, Power Gating MOS-Driver Active Low Catalog
M_RST DONE 3 4 TPL5010 SNAS651A –JANUARY 2015– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TPL5010 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated (1) G= Ground, P= Power, O= Output, I= Input.
6 Pin Configuration and Functions
TYPE(1) DESCRIPTION APPLICATION INFORMATION NO. NAME
1 VDD P Supply voltage
2 GND G Ground
3 DELAY/
M_RST I Time Interval set and Manual Reset Resistance between this pin and GND is used to select the time interval. The reset switch is also connected to this pin.
4 DONE I Logic Input for watchdog
Digital signal driven by the µC to indicate successful processing of the WAKE signal.
5 WAKE O Timer output signal generated every
tIP period. Digital pulsed signal to wake up the µC at the end of the programmed time interval.
6 RSTn O Reset Output (open drain output) Digital signal to RESET the µC, pullup resistance is
www.ti.com SNAS651A – JANUARY 2015– REVISED SEPTEMBER 2018 Product Folder Links: TPL5010 Submit Documentation FeedbackCopyright © 2015–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The voltage between any two pins should not exceed 6V. (3) The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a printed-circuit board (PCB).
7 Specifications
7.1 Absolute Maximum Ratings(1)
Supply Voltage (VDD-GND) –0.3 6 V Input Voltage at any pin(2) –0.3 VDD + 0.3 V Input Current on any pin –5 +5 mA Junction Temperature, TJ(3) 150 °C Storage Temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human Body Model, per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-101(2) ±250
7.3 Recommended Operating Ratings
Supply Voltage (VDD-GND) 1.8 5.5 V Temperature –40 105 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
7.4 Thermal Information
THERMAL METRIC(1) TPL5010 UNITDDC (SOT-23)
6 PINS
RθJA Junction-to-ambient thermal resistance 163 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26 °C/W RθJB Junction-to-board thermal resistance 57 °C/W ψJT Junction-to-top characterization parameter 7.5 °C/W ψJB Junction-to-board characterization parameter 57 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
SNAS651A –JANUARY 2015– REVISED SEPTEMBER 2018 www.ti.com Product Folder Links: TPL5010 Submit Documentation Feedback Copyright © 2015–2018, Texas Instruments Incorporated (1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. (2) Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through correlations using statistical quality control (SQC) method. (3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (4) The supply current excludes load and pullup resistor current. Input pins are at GND or VDD. (5) The accuracy for time interval settings below 1 second is ±100 ms. (6) This parameter is specified by design and/or characterization and is not tested in production. (7) Operational life time test procedure equivalent to 10 years.
7.5 Electrical Characteristics(1)
Specifications are for TA= 25°C, VDD-GND = 2.5 V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT POWER SUPPLY IDD Supply current(4) Operation mode 35 50 nA Digital conversion of external resistance (Rext) 200 400 µA TIMER tIP Time Interval Period 1650 selectable Time Intervals Minimum time interval 100 ms Maximum time interval 7200 s Time Interval Setting Accuracy(5) Excluding the precision of Rext ±0.6% Timer Interval Setting Accuracy over supply voltage 1.8 V ≤ VDD ≤ 5.5 V ±25 ppm/V tOSC Oscillator Accuracy –0.5% 0.5% Oscillator Accuracy over temperature(6) Oscillator Accuracy over supply voltage Oscillator Accuracy over life time(7) 0.24% tDONE DONE Pulse width (6) 100 ns tRSTn RSTn Pulse width 320 ms tWAKE WAKE Pulse width 20 ms t_Rext Time to convert Rext 100 120 ms DIGITAL LOGIC LEVELS VIH Logic High Threshold DONE pin 0.7 × VDD V VIL Logic Low Threshold DONE pin 0.3 × VDD V VOH Logic output High Level WAKE pin Iout = 100 µA VDD – 0.3 V Iout = 1 mA VDD – 0.7 V VOL Logic output Low Level WAKE pin Iout = -100 µA 0.3 V Iout = –1 mA 0.7 V VOLRSTn RSTn Logic output Low Level IOL = –1 mA 0.3 V IOHRSTn RSTn High Level output current VOHRSTn = VDD 1 nA VIHM_RST Logic High Threshold DELAY/M_RST pin 1.5 V
correlations using statistical quality control (SQC) method. (3) This parameter is specified by design and/or characterization and is not tested in production. (4) In case of RSTn from its falling edge, or in case of WAKE from its rising edge.
7.6 Timing Requirements
Figure 1. TPL5010 Timing
7.7 Typical Characteristics
Figure 2. IDD vs. VDD Figure 3. IDD vs. Temperature Figure 4. Oscillator Accuracy vs. VDD Figure 5. Oscillator Accuracy vs. Temperature Figure 6. IDD vs. Time Figure 7. Time Interval Setting Accuracy
8 Detailed Description
8.1 Overview
TPL5010 can be used in interrupt-driven applications and provides selectable timing from 100 ms to 7200 s.
8.2 Functional Block Diagram
8.3 Feature Description
manual reset function is realized by momentarily pulling the DELAY/M_RST pin to VDD. Figure 8. Watchdog
8.3.1 WAKE
beginning of the first cycle or if in the previous interval the DONE has not been received). This signal is normally low.
8.3.2 DONE
only the first DONE signal is processed. high, the WAKE will go low as soon as the DONE is recognized.
8.3.3 RSTn
recommended to minimize current. During the POR and the reading of the REXT, the RSTn signal is LOW.
- If the DELAY/M_RST pin is high for at least two consecutive cycles of the internal oscillator (approximately
- At the beginning of a new time interval if DONE is not received at least 20 ms before the next WAKE rising
8.4 Device Functional Modes
8.4.1 Start-Up
this measurement, a constant current is temporarily flowing into REXT. Figure 9. Start-Up
8.4.2 Normal Operating Mode
counters. See Figure 8 and Figure 10 .
8.5 Programming
8.5.1 Configuring the WAKE Interval With the DELAY/M_RST Pin
section Timer Interval Selection Using External Resistance on how to set the WAKE pulse interval using REXT. (rising edge), is given by the sum of the programmed time interval and the tRSTn (reset pulse width).
8.5.2 Manual Reset
voltage at DELAY/M_RST is removed and the next tRSTn is elapsed. Figure 10. Manual Reset
8.5.2.1 DELAY/M_RST
the RSTn signal maybe affected by an uncertainty of about ±5 ms.
- WAKE = LOW
- RSTn = asserted LOW
8.5.2.2 Circuitry
possible approaches according to the power consumption constraints of the application.
Figure 11. Manual Reset With SPST Switch offer a lower-cost solution. The DELAY/M_RST pin may be directly connected to VDD with REXT in the circuit. The current drawn from the supply voltage during the reset is given by VDD/REXT. Figure 12. Manual Reset With SPDT Switch double-throw switch, which will provide a lower power solution for the manual reset, because no current flows.
8.5.3 Timer Interval Selection Using External Resistance
- T is the desired time interval in seconds.
- REXT is the resistance value to use in Ω.
- a, b, and c are coefficients depending on the range of the time interval. (1)
Table 1. Coefficients for Equation 1 The coefficient set to be selected is the number 2. The formula becomes Equation 2. The resistance value is 10.18 kΩ. Table 2 and Table 3 contain example values of tIP and their corresponding value of REXT. Table 2. First 9 Time Intervals Table 3. Most Common Time Intervals Between 1s to 2h
Table 3. Most Common Time Intervals Between 1s to 2h (continued)
8.5.4 Quantization Error
discrete intervals, there is a quantization error associated with each value.
- (3) REXT is the resistance calculated with Equation 1 and a, b, c are the coefficients of the equation listed in Table 1.
8.5.5 Error Due to Real External Resistance
are characterized by a certain tolerance. This tolerance will affect the accuracy of the time interval.
- Evaluate the min and max values of REXT (REXT_MIN, REXT_MAX with Equation 1 using the selected commercial
resistance values and their tolerances.
- Evaluate the time intervals (TADC_MIN[REXT_MIN], TADC_MAX[REXT_MAX]) with the TADC equation mentioned in
- Find the errors using Equation 3 with TADC_MIN, TADC_MAX.
The results of the formula indicate the accuracy of the time interval.
//// 21 ¸ § R u R uRuR RR TPL5010 www.ti.com SNAS651A – JANUARY 2015– REVISED SEPTEMBER 2018 Product Folder Links: TPL5010 Submit Documentation FeedbackCopyright © 2015–2018, Texas Instruments Incorporated The example below illustrates the procedure.
- Desired time interval, T_desired = 600 s,
- Required REXT from Equation 1, REXT= 57.44 kΩ. From Table 3 REXT can be built with a parallel combination of two commercial values with 1% tolerance: R1 = 107 kΩ, R2 = 124 kΩ. The uncertainty of the equivalent parallel resistance can be found using Equation 4: where
- uRn (n=1,2) represent the uncertainty of a resistance (see Equation 5) (4) SPACER (5) The uncertainty of the parallel resistance is 0.82%, which means the value of REXT may range between REXT_MIN = 56.96 kΩ and REXT_MAX = 57.90 kΩ. Using these value of REXT, the digitized timer intervals calculated by TADC equation mentioned in Equation 3 are asymmetry of the error range is due to the quadratic transfer function of the resistance digitizer.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
sensor based on the LMP91000. Figure 13. Data-Logger
9.2.1 Design Requirements
9.2.2 Detailed Design Procedure
and wake-up timing functions. application constraints and maximize the life of the battery.
9.2.3 Application Curve
Figure 14. Effect of TPL5010 on Current Consumption
10 Power Supply Recommendations
μF between VDD and GND pin is recommended.
11 Layout
11.1 Layout Guidelines
11.2 Layout Example
Figure 15. Layout
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPL5010DDCR Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCR.A Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCR.B Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCT Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCT.A Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCT.B Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCTG4.A Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX TPL5010DDCTG4.B Active Production SOT-23- THIN (DDC) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 105 ZAKX (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1
www.ti.com 23-May-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPL5010 :
- Automotive : TPL5010-Q1 NOTE: Qualified Version Definitions:
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant TPL5010DDCR SOT-23- THIN TPL5010DDCT SOT-23- THIN Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL5010DDCR SOT-23-THIN DDC 6 3000 208.0 191.0 35.0 TPL5010DDCT SOT-23-THIN DDC 6 250 208.0 191.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.20
0.12 TYP
0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1
0.0 TYP
6X 0.5 0.3 0.6
0.3 TYP
1.9 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/E 08/2024 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4
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