TPL0501-100DCNRG4.A

TPL0501-100 TI | Alldatasheet

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Copyright © 2016, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPL0501-100 SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 TPL0501256-Taps,Single-Channel,DigitalPotentiometerWithSPIInterface

1 Features

1• Single-channel, 256-position resolution

• 100-kΩ end-to-end resistance options
• Low temperature coefficient: 35 ppm/°C
• SPI-compatible serial interface
• 2.7-V to 5.5-V single-supply operation
• ±20% resistance tolerance
• Operating temperature: –40°C to +125°C
• ESD performance tested per JESD 22 – 2000-V human-body model (A114-B, Class II)

2 Applications

• Pulse oximeter
• Water meter
• Camera
• Medical sensor patches
• Building security gateway

3 Description

The TPL0501 device is a single-channel, linear-taper, digital potentiometer with 256 wiper positions. This device can be used as a three-terminal potentiometer or as a two-terminal rheostat. The TPL0501 is currently offered with end-to-end resistance of 100 kΩ. The internal registers of the TPL0501 can be accessed using a SPI-compatible interface. The TPL0501 has a nominal temperature coefficient of 35 ppm/°C. The TPL0501 is available in 8-pin SOT-23 and 8-pin UQFN packages, with a specified temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPL0501 UQFN (8) 1.50 mm × 1.50 mm SOT-23 (8) 1.63 mm × 2.90 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Schematic

SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TPL0501-100 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Table of Contents 6.5 Electrical Characteristics: Operating Specifications.. 5

11.1 Receiving Notification of Documentation Updates 21

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2016) to Revision C Page Changes from Revision A (September 2011) to Revision B Page

• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
• Changed ratio to correct form in Ideal Resistance Values section and in Table 2; registers names for RWL and

H W VDD L W L CS H GND VDD 3 6 DINSCLK 4 5 TPL0501-100 www.ti.com SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 Product Folder Links: TPL0501-100 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated

5 Pin Configuration and Functions

(1) G = Ground, I = Input, O = Output, P = Power Pin Functions PIN TYPE(1) DESCRIPTION NAME SOT-23 UQFN CS 6 3 I SPI chip select (active low) DIN 5 2 I SPI input GND 3 4 G Ground H 8 1 I/O High terminal L 7 8 I/O Low terminal SCLK 4 5 I SPI clock VDD 2 7 P Positive supply voltage W 1 6 I/O Wiper terminal (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum (3) All voltages are with respect to ground, unless otherwise specified.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) MIN MAX UNIT Supply voltage VDD to GND –0.3 7 V VH, VL, VW –0.3 VDD + 0.3 Pulse current, IH, IL, IW ±20 mA Continuous current, IH, IL, IW (TPL0501-100) ±5 mA Digital input voltage, VI –0.3 7 V Operating temperature, Tj 125 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TPL0501-100 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The package thermal impedance is calculated in accordance with JESD 51-7.

6.3 Thermal Information

THERMAL METRIC(1) TPL0501 UNITDCN (SOT-23) RSE (UQFN)

8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance(2) 205.6 118.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 122.3 62.4 °C/W RθJB Junction-to-board thermal resistance 98.9 26.8 °C/W ψJT Junction-to-top characterization parameter 38.7 2.3 °C/W ψJB Junction-to-board characterization parameter 97.8 26.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) VH = VDD, VL = GND, VW = not loaded (2) Measurements between Wi and Li with Hi not connected, or between Wi and Hi with Li not connected.

6.4 Electrical Characteristics: Analog Specifications

typical values are specified at VDD = 5 V and operating temperature is 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTOTAL End-to-end resistance Between Hi and Li terminals 80 100 120 kΩ VH, VL Terminal voltage 0 VDD V RH, RL Terminal resistance 50 150 Ω RW Wiper resistance H terminal floating, VL = GND, Force IW = (VDD/2) / RTOTAL, input code = 0x80h 25 100 Ω CH, CL Terminal capacitance f = 1 MHz, measured to GND, input code = 0x80h 15 pF CW Wiper capacitance f = 1 MHz, measured to GND, input code = 0x80h 12 pF ILKG Terminal leakage current VH = GND to VDD, VL = floating or VL = GND to VDD, VH = floating 0.1 1 µA TCR Resistance temperature coefficient 35 ppm/°C VOLTAGE DIVIDER MODE(1) INL Integral non-linearity –1 1 LSB DNL Differential non-linearity –0.5 0.5 LSB ZSERROR Zero-scale error 0 0.5 2 LSB FSERROR Full-scale error –2 –0.5 0 LSB TCV Ratiometric temperature coefficient Wiper set at mid-scale 4 ppm/°C BW Bandwidth Wiper set at mid-scale (TPL0501-100), CLOAD= 10 pF 265 kHz TSW Wiper settling time TPL0501-100 3 µS THD Total harmonic distortion VH = 1 VRMS at 1 kHz, VL = VDD/2, measurement at W 0.005% RHEOSTAT MODE(2) RINL Integral non-linearity –1 1 LSB RDNL Differential non-linearity –0.5 0.5 LSB ROFFSET Offset 0 0.5 2 LSB RBW Bandwidth Code = 0x00h, L floating, input applied to W, 10 pF on H 60 kHz

www.ti.com SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 Product Folder Links: TPL0501-100 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated (1) SCLK, DIN, CS Inputs

6.5 Electrical Characteristics: Operating Specifications

typical values are specified at VDD = 5 V and operating temperature is 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDD(STBY) VDD standby current 0.3 8 µA IIN-DIG Digital pins leakage current SCLK, DIN, CS inputs –1 1 µA IDD(SUPPLY) VDD supply current Digital input = 1.8 V, VDD = 2.7 V 5 µA Digital input = 1.8 V, VDD = 5 V 500 SERIAL INTERFACE(1) VIH Input high voltage VDD = 2.7 V to 5.5 V 1.8 5.5 V VIL Input low voltage SCLK, DIN, CS inputs 0 0.6 V CIN Pin capacitance SCLK, DIN, CS inputs 7 10 pF

6.6 Timing Requirements

fSCLK SCLK frequency 25 MHz tSCP SCLK period 40 ns tSCH SCLK high time 20 ns tSCL SCLK low time 20 ns tDS DIN to SCLK set-up time 5 ns tDH DIN hold after SCLK 5 ns tCSS CS fall to SCLK rise setup time 15 ns tCSW CS pulse width high 40 ns

6.7 Typical Characteristics

Figure 1. INL vs Tap Position (Potentiometer Mode) Figure 2. DNL vs Tap Position (Potentiometer Mode) Figure 3. INL vs Tap Position (Rheostat Mode) Figure 4. DNL vs Tap Position (Rheostat Mode) Figure 5. End-to-End Resistance Change vs Temperature Figure 6. Zero Scale Error vs Temperature

Copyright © 2016, Texas Instruments Incorporated TPL0501-100 SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: TPL0501-100 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPL0501 has a single linear-taper digital potentiometer with 256 wiper positions and an end-to-end resistance of 100 kΩ. The potentiometer can be used as a three-terminal potentiometer or as a two-terminal rheostat. The potentiometer can be used in either voltage divider mode or rheostat mode. The high (H) and low (L) terminals of the TPL0501 are equivalent to the fixed terminals of a mechanical potentiometer. The H and L terminals do not have any polarity restrictions (H can be at a higher voltage than L, or L can be at a higher voltage than H). The position of the wiper (W) terminal is controlled by the value in the 8-bit Wiper Resistance (WR) register. When the WR register contains all zeroes (zero-scale), the wiper terminal is closest to its L terminal. As the value of the WR register increases from all zeroes to all ones (full-scale), the wiper moves from the position closest to the L terminal, to the position closest to the H terminal. At the same time, the resistance between W and L increases, whereas the resistance between W and H decreases.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Single-Channel, 256-Position Resolution

The TPL0501 features a single independent DPOT. The DPOT is capable of being used and controlled independently.

7.4 Device Functional Modes

7.4.1 Voltage Divider Mode

wiper-to-H and wiper-to-L is proportional to the input voltage at H to L (see Figure 12). Figure 12. Equivalent Circuit for Voltage Divider Mode from 0 V to 5 V (see Equation 1). The voltage difference between terminal H and terminal W can also be calculated in Equation 2.

• D is the decimal value of the wiper code. (2)

7.4.2 Rheostat Mode

used to determine one of the 256 possible wiper positions. in two possible ways (see Figure 13). Figure 13. Equivalent Circuit for Rheostat Mode With Terminal H to Terminal W Resistance

• RTOT is the end-to-end resistance between terminal H and terminal L.
• D is the decimal value of the wiper code (3) Similarly, to set the resistance between terminal L and terminal W, the potentiometer can be configured in two possible ways.

Figure 14. Equivalent Circuit for Rheostat Mode With Terminal L to Terminal W Resistance

• RTOT is the end-to-end resistance between terminal H and terminal L
• D is the decimal value of the wiper code. (4)

7.5 Programming

7.5.1 SPI Digital Interface

low during the entire serial data stream to avoid corruption of the data. Table 1. Register Map - Default Value 0x80 Figure 15. SPI Write Sequence Figure 16. Digital Interface Timing Diagram

7.5.2 Ideal Resistance Values

Figure 17. Digital Potentiometer Measurements resistance can vary significantly but the Ratio (RWL/RHW) is extremely accurate. Table 2. DPOT Ideal Values

Table 2. DPOT Ideal Values (continued)

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

digital-to-analog converter (DAC).

8.2 Typical Application

Figure 18. DAC Schematic

8.2.1 Design Requirements

Table 3 lists the design parameters for this application. Table 3. Example Parameters

8.2.2 Detailed Design Procedure

on the output of the voltage divider affects the output voltage.

8.2.3 Application Curve

H voltage. In this example, VIN at terminal H is 5 V and 2.7 V. Figure 19. TPL0501 Digital Input vs OPA320 Analog Output (DAC)

0603 Cap

9 Power Supply Recommendations

9.1 Power Sequence

VW. The order of powering digital inputs, VH, VL, and VW does not matter as long as they are powered after VDD.

9.2 Wiper Position Upon Power Up

the device will return to 0x80h code because this device does not contain non-volatile memory.

10 Layout

10.1 Layout Guidelines

To maintain reliability of the device, follow common printed-circuit board (PCB) layout guidelines.

• Leads to the input must be as direct as possible with a minimum conductor length.
• The ground path must have low resistance and low inductance.
• Use short trace-lengths to avoid excessive loading.
• It is common to have a dedicated ground plane on an inner layer of the board.
• Terminals that are connected to ground must have a low-impedance path to the ground plane in the form of wide polygon pours and multiple vias.
• Use bypass capacitors on power supplies and placed them as close as possible to the VDD pin.
• Apply low equivalent series resistance (0.1-μF to 10-μF tantalum or electrolytic capacitors) at the supplies to minimize transient disturbances and to filter low frequency ripple.

10.2 Layout Example

Figure 20. Example Layout for DCN Package

www.ti.com SLIS136C –SEPTEMBER 2011–REVISED SEPTEMBER 2019 Product Folder Links: TPL0501-100 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPL0501-100DCNR Active Production SOT-23 (DCN) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (NF5J, NF5T) TPL0501-100DCNR.A Active Production SOT-23 (DCN) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 (NF5J, NF5T) TPL0501-100DCNRG4 Active Production SOT-23 (DCN) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 NF5T TPL0501-100DCNRG4.A Active Production SOT-23 (DCN) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 NF5T TPL0501-100RSER Active Production UQFN (RSE) | 8 5000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 7M TPL0501-100RSER.A Active Production UQFN (RSE) | 8 5000 | LARGE T&R Yes NIPDAUAG Level-1-260C-UNLIM -40 to 125 7M (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 10-Nov-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL0501-100DCNR SOT-23 DCN 8 3000 202.0 201.0 28.0 TPL0501-100DCNRG4 SOT-23 DCN 8 3000 202.0 201.0 28.0 TPL0501-100RSER UQFN RSE 8 5000 202.0 201.0 28.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C0.6 0.5 0.05 0.00 4X 0.5 6X 0.4 0.3 4X 0.3 0.2 2X 0.45 0.35 2X 0.25 0.15 2X 0.35 0.25 B 1.55 1.45 A 1.55 1.45 (0.12) TYP UQFN - 0.6 mm max heightRSE0008A PLASTIC QUAD FLATPACK - NO LEAD 4220323/B 03/2018 PIN 1 INDEX AREA SEATING PLANE 0.05 C

0.1 C A B

0.05 C SYMM SYMM 0.05 C PIN 1 ID (45 X 0.1) NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 0.05 C SCALE 7.000

www.ti.com EXAMPLE BOARD LAYOUT 2X (0.6) 2X (0.3) (0.2)

0.07 MIN

0.07 MAX

6X (0.55) 4X (0.25) 4X (0.5) (1.35) (1.3) (R0.05) TYP UQFN - 0.6 mm max heightRSE0008A PLASTIC QUAD FLATPACK - NO LEAD 4220323/B 03/2018 SYMM 3 5 SYMM LAND PATTERN EXAMPLE SCALE:30X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). METAL SOLDER MASK OPENING SOLDER MASK DETAILS NOT TO SCALE NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 6X (0.55) 4X (0.25) 2X (0.6) (0.3) (1.35) (1.3) 2X (0.2)4X (0.5) (R0.05) TYP UQFN - 0.6 mm max heightRSE0008A PLASTIC QUAD FLATPACK - NO LEAD 4220323/B 03/2018 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICKNESS SCALE: 30X

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