TPL0401B

TPL0401A_12 TI1 | Alldatasheet

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W H GND VDD 1 SDASCL 4 TPL0401A/B L W L GND VDD 1 SDASCL 4 TPL0401C H TPL0401A TPL0401B TPL0401C www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 128TAPSSingleChannelDigitalPotentiometerwithI2C Interface Check forSamples: TPL0401A ,TPL0401B ,TPL0401C 1FEATURES DESCRIPTION• SingleChannel,128-PositionResolution The TPL0401 isa singlechannel,linear-taperdigital• 10 kΩ End-to-EndResistanceOptions potentiometerwith 128 wiper positions.The

• Low Temperature Coefficient:35 ppm/ °C TPL0401A/B have the low terminalinternaland connectedtoGND. The positionofthewipercan be• I2C SerialInterface adjustedusing an I2C interface.The TPL0401 is• 2.7V to5.5V Single-SupplyOperation availableina 6-pinSC-70 package witha specified• ±20% ResistanceTolerance temperaturerangeof–40°C to125°C. The parthas a 10k end-to-endresistanceand can operatewitha• 'A'and 'B'VersionsHave DifferentI2C supplyvoltagerange of 2.7V to 5.5V.This kindofAddresses productiswidelyused insettingthevoltagereference• 'L'Terminalof'A'and 'B'versionisinternal forlowpower DDR3 memory.and connected To GND The TPL0401A/B have theLow Terminalinternaland• ‘H ’Terminalof ‘C ’VersionisInternaland connected to GND. The TPL0401C has the HighFloating Terminalinternaland floating.• OperatingTemperature –40°C to125°C SC-70 DCK PACKAGE• AvailableinIndustryStandard SC70 Packages (TOP VIEW)• ESD Performance Tested per JESD 22 – 2000 V Human Body Model (A114-B,Class II)

APPLICATIONS

• Low Power DDR3 VoltageReference
• AdjustablePower Supplies
• AdjustableGain Amplifiersand Offset Trimming
• PrecisionCalibrationofSet PointThresholds
• Sensor Trimming and Calibration
• MechanicalPotentiometerReplacement

ORDERING INFORMATION

ORDERABLE PART END-TO-END TOP-SIDETA PACKAGE (1) I2C ADDRESSNUMBER RESISTANCE MARKING TPL0401A-10DCKR 10-kΩ 0101110 7TV Tape and–40°C to125°C SC70 – DCK TPL0401B-10DCKR 10-kΩ 0111110 7UVReel TPL0401C-50DCKR 50-kΩ 0101110 TBD (1) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011–2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

H W TPL0401A/B WIPER REGISTERI C INTERFACE2SCL SDA VDD GND L W TPL0401C H TPL0401A TPL0401B TPL0401C SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. PIN FUNCTIONS PIN NUMBER PIN NAME TYPE DESCRIPTION

1 VDD Power PositiveSupplyVoltage

2 GND Ground Ground

3 SCL Input I2C Clock

4 SDA I/O I2C Data

5 W I/O Wiperterminal

6 H I/O Highterminal

– L I/O Low terminal FUNCTIONAL BLOCK DIAGRAM

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H L W RHW RWL RTOT H L WRTOT RWL = RTOT x D/128 RHW = RTOT x (1 – (D/128)) VOLTAGE DIVIDER MODE RHEOSTAT MODE A RHEOSTAT MODE B Where D = Decimal Value of Wiper Code Where D = Decimal Value of Wiper Code Where D = Decimal Value of Wiper Code H (Floating) L W RWL RTOT RHW H L (Floating) WRTOT OR OR VH W VHW VWL VH - VL VL VWL = (VH – V L) x D/128 VHW = (VH – V L) x (1 – (D/128)) TPL0401A TPL0401B TPL0401C www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 DIGITAL POTENTIOMETER CONFIGURATIONS Figure1. DPOT Configurations Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1)(2)(3) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VDD toGND –0.3 7 V SupplyvoltagerangeAllotherpinsto –0.3 VDD +0.3 VGND Pulsecurrent ±20 mAIH IL TPL0401A/B-10 ±5 mA ContinuouscurrentIW TPL0401C-50 ±1.3 mA VI Digitalinputvoltagerange –0.3 VDD + 0.3 V θJA Package thermalimpedance(4) DCK package 259 °C/W Tstg Storagetemperaturerange –65 150 °C (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotimplied. (2) The algebraicconvention,whereby themost negativevalueisa minimum and themost positivevalueisa maximum (3) Allvoltagesarewithrespecttoground,unlessotherwisespecified. (4) The package thermalimpedance iscalculatedinaccordancewithJESD 51-7. RECOMMENDED OPERATING CONDITIONS DESCRIPTION MIN MAX Unit VDD SupplyVoltage 2.7 5.5 V VW ,VH TerminalVoltage 0 VDD V VIH VoltageInputHigh(SCLK, SDA ) 0.7VDD V VIL VoltageInputLow (SCLK, SDA) 0.3VDD V IW WiperCurrent ±2 mA TA AmbientOperatingtemperature -40 128 °C

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www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 ANALOG SPECIFICATIONS Typicalvaluesarespecifiedat25oC and Vdd=3.3V PARAMETER CONDITIONS MIN TYP MAX UNIT TPL0401A/B-10 8 10 12 kΩEnd-to-endresistance(betweenHR TOTAL and L terminals) TPL0401C-50 40 50 60 kΩ VH Terminalvoltagerange 0 VDD V R H Terminalresistance 35 100 Ω R W Wiperresistance 35 100 Ω C H Terminalcapacitance 10 pF C W Wipercapacitance 11 pF ILKG Terminalleakagecurrent 0.1 1 µA TPL0401A/B-10 22 ppm/°C TC R Resistancetemperaturecoefficient TPL0401C-50 TBD ppm/°C VOLTAGE DIVIDER MODE (TPL0401A, TPL0401B, VH = VDD ,VW = Not Loaded) INL Integralnon-linearity –0.5 0.5 LSB DNL Differentialnon-linearity –0.25 0.25 LSB ZS ERROR Zero-scaleerror 0 0.75 1.5 LSB FS ERROR Full-scaleerror –1.5 -0.75 0 LSB RatiometrictemperatureTCV Wipersetatmid-scale 4 ppm/°Ccoefficient Wipersetatmid-scale,BW Bandwidth 2862 kHz,C LOAD = 10 pF TSW Wipersettlingtime 0.152 µS VH = 1 VRMS at1 kHz,THD Totalharmonicdistortion 0.03 %VL = VDD /2,Measurement atW RHEOSTAT MODE (TPL0401C) RINL Integralnon-linearity TBD LSB RDNL Differentialnon-linearity TBD LSB R OFFSET Offset TBD LSB Code=0x00h, L Floating,InputappliedtoW, 10pFRBW Bandwidth TBD kHzon H Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com OPERATING SPECIFICATIONS Typicalvaluesarespecifiedat25oC and Vdd=3.3V(1) CONDITIONPARAMETER MIN TYP MAX UNITS -40to85oC 0.5 uA IDD(STBY) VDD Standbycurrent -40to125oC 1.5 uA IIN-DIG DigitalPinsLeakage Current(SCL,SDA Inputs) -1 1 uA SERIAL INTERFACE SPECS (SDA, SCL) VIH Inputhighvoltage 0.7x VDD 5.5 V VIL Inputlowvoltage 0 0.3x VDD V SDA Pin,VOL Outputlowvoltage 0.4 VIOL = 4 mA SCL,C IN Pincapacitance 7 pFSDA Inputs I2C INTERFACE TIMING REQUIREMENTS STANDARD MODE I2C FAST MODE I2C BUS UNITSBUS MIN MAX MIN MAX fSCL I2C Clockfrequency 0 100 0 400 kHz tSCH I2C Clockhightime 4 0.6 µs tSCL I2C Clocklowtime 4.7 1.3 µs tsp I2C Spiketime 0 50 0 50 ns tSDS I2C Serialdatasetuptime 250 100 ns tSDH I2C Serialdataholdtime 0 0 ns tICR I2C Inputrisetime 1000 20 + 0.1Cb 300 ns tICF I2C Inputfalltime 300 20 + 0.1Cb 300 ns tICF I2C Outputfalltime,10 pF to400 pF bus 300 20 + 0.1Cb 300 ns tBUF I2C Bus freetimebetween stopand start 4.7 1.3 µs tSTS I2C Startorrepeaterstartconditionsetuptime 4.7 1.3 µs tSTH I2C Startorrepeaterstartconditionholdtime 4 0.6 µs tSPS I2C Stopconditionsetuptime 4 0.6 µs tVD(DATA) Validdatatime,SCL lowtoSDA outputvalid 1 1 µs ValiddatatimeofACK condition,ACK signalfromSCL lowtVD(DATA) 1 1 µstoSDA (out)low (1) ParameterswithMin and Max limitsare100% testedat+25C, unlessotherwisespecified.Temperaturelimitsestablishedby characterizationand arenotproductiontested

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-0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0 18 36 54 72 90 108 126 Digital Code INL Error (LSB) 5.5V 3.3V 2.7V -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0 18 36 54 72 90 108 126 Digital Code DNL Error (LSB) 5.5V 3.3V 2.7V -1.00 -0.50 0.00 0.50 1.00 0 16 32 48 64 80 96 112 128 Digital Code RINL Error (LSB) 5.5V 3.3V 2.7V -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0 16 32 48 64 80 96 112 128 Digital Code RDNL Error (LSB) 5.5V 3.3V 2.7V 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 -40 -20 0 20 40 60 80 100 120 T emperature (C) ZS Error (LSB) 5.5V 3.3V 2.7V -1.00 -0.90 -0.80 -0.70 -0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 -40 -20 0 20 40 60 80 100 120 T emperature (C) FS Error (LSB) 5.5V 3.3V 2.7V TPL0401A TPL0401B TPL0401C www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 TYPICAL CHARACTERISTICS INL vs DNL vs TAP POSITION (PotentiometerMode) TAP POSITION (PotentiometerMode) Figure2. Figure3. INL vs DNL vs TAP POSITION (RheostatMode) TAP POSITION (RheostatMode) Figure4. Figure5. ZERO SCALE ERROR vs FULL SCALE ERROR vs TEMPERATURE TEMPERATURE Figure6. Figure7. Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

-1.00 -0.50 0.00 0.50 1.00 -40 -10 20 50 80 110 T emperature (C) Resistance Change (%) 5.5V 3.3V 2.7V 0.00 30.00 60.00 90.00 120.00 150.00 180.00 210.00 240.00 270.00 300.00 0 16 32 48 64 80 96 112 128 Digital Code TC (ppm/C) 5.5V 3.3V 2.7V 0.00 30.00 60.00 90.00 120.00 150.00 180.00 210.00 240.00 270.00 300.00 0 16 32 48 64 80 96 112 128 Digital Code TC (ppm/C) 5.5V 3.3V 2.7V -60.00 -54.00 -48.00 -42.00 -36.00 -30.00 -24.00 -18.00 -12.00 -6.00 0.00 Frequency (Hz) Magnitude (dB) Code 40 Code 20 Code 10 Code 08 TPL0401A TPL0401B TPL0401C SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) END-TO-END RTOTAL% CHANGE vs TEMPERATURE COEFFICIENT vs TEMPERATURE TAP POSITION (PotentiometerMode) Figure8. Figure9. TEMPERATURE COEFFICIENT vs TAP POSITION (RheostatMode) FREQUENCY RESPONSE Figure10. Figure11.

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Start Address (01_1110) 0 Ack Command (00000000) Ack Start Address (01_1110) 0 Ack Command (00000000) Ack reStart Address (01_1110) 1 Ack Data Byte I2C Write to A Register I2C Read From A Register Data Stop noAck Stop Ack From Processor to DPOT From toDPOT Processor SDA SCL Start Condition Stop Condition S P TPL0401A TPL0401B TPL0401C www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 SLAVE ADDRESS TPL0401A, TPL0401C BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (MSB) (LSB) 0 1 0 1 1 1 0 R/W TPL0401B BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (MSB) (LSB) 0 1 1 1 1 1 0 R/W WRITE AND READ PROTOCOL Standard I2C InterfaceDetails The bidirectionalI2C bus consistsof the serialclock(SCL) and serialdata (SDA) lines.Both linesmust be connectedto a positivesupplyviaa pullupresistorwhen connectedto the outputstagesof a device.Data transfermay be initiatedonlywhen thebus isnotbusy. I2C communicationwiththisdeviceisinitiatedby themastersendinga startcondition,a high-to-lowtransitionon theSDA input/outputwhiletheSCL inputishigh(seeFigure13).Afterthestartcondition,thedeviceaddress byteissent,MSB first,includingthedatadirectionbit(R/W).Thisdevicedoes notrespondtothegeneralcall address.Afterreceivingthevalidaddressbyte,thisdevicerespondswithan ACK, a low on theSDA input/output duringthehighoftheACK-relatedclockpulse. Figure12. DefinitionofStartand Stop Conditions Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

S 1 2 8 9 TPL0401A TPL0401B TPL0401C SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com The databytefollowstheaddressACK. The R/W bitiskeptlow fortransferfrom themastertotheslave.The databyteisfollowedby an ACK sentfromthisdevice.Data areoutputonlyifcompletebytesarereceivedand acknowledged.The outputdataisvalidattime(tpv)afterthelow-to-hightransitionofSCL, duringtheclockcycle fortheACK. On theI2C bus,onlyone databitistransferredduringeach clockpulse.The dataon theSDA linemust remain stableduringthehighpulseoftheclockperiod,as changes inthedatalineatthistimeareinterpretedas control commands (startorstop)(seeFigure13). Figure13. BitTransfer A stopcondition,a low-to-hightransitionon the SDA input/outputwhilethe SCL inputishigh,issentby the master(seeFigure13). The number ofdatabytestransferredbetween thestartand thestopconditionsfromtransmittertoreceiverisnot limited.Each byteofeightbitsisfollowedby one ACK bit.The transmittermust releasetheSDA linebeforethe receivercan send an ACK bit. A slavereceiverthatisaddressedmust generatean ACK afterthe receptionof each byte.The devicethat acknowledgeshas topulldown theSDA lineduringtheACK clockpulseso thattheSDA lineisstablelowduring thehighpulseoftheACK-relatedclockperiod(seeFigure14).Setupand holdtimesmust be takenintoaccount. Figure14. Acknowledgement on theI2C Bus

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1.5 V VREF1 + 1 k/c87 DPOT TPL0401A/B OP-AMP LMV321 1 k/c87 TPL0401A TPL0401B TPL0401C www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 TYPICAL APPLICATION Figure15. DDR3 VoltageReferenceAdjustment Below tableshows Idealvaluesofresistancefora 10kΩ DPOT. The absolutevaluescan varysignificantly,but theratio(Rhw/Rwl)isextremelyaccurate. Table1.ResistanceValues Table Step Binary Rwl (kΩ) Rhw (kΩ) Rhw/Rwl 0 0 0.00 10.00 0.00 1 1 0.08 9.92 0.01 2 10 0.16 9.84 0.02 3 11 0.23 9.77 0.02 4 100 0.31 9.69 0.03 5 101 0.39 9.61 0.04 6 110 0.47 9.53 0.05 7 111 0.55 9.45 0.06 8 1000 0.63 9.38 0.07 9 1001 0.70 9.30 0.08 10 1010 0.78 9.22 0.08 11 1011 0.86 9.14 0.09 12 1100 0.94 9.06 0.10 13 1101 1.02 8.98 0.11 14 1110 1.09 8.91 0.12 15 1111 1.17 8.83 0.13 16 10000 1.25 8.75 0.14 17 10001 1.33 8.67 0.15 18 10010 1.41 8.59 0.16 19 10011 1.48 8.52 0.17 20 10100 1.56 8.44 0.19 21 10101 1.64 8.36 0.20 22 10110 1.72 8.28 0.21 23 10111 1.80 8.20 0.22 24 11000 1.88 8.13 0.23 25 11001 1.95 8.05 0.24 26 11010 2.03 7.97 0.25 27 11011 2.11 7.89 0.27 28 11100 2.19 7.81 0.28 29 11101 2.27 7.73 0.29 30 11110 2.34 7.66 0.31 31 11111 2.42 7.58 0.32 Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com Table1.ResistanceValues Table(continued) Step Binary Rwl (kΩ) Rhw (kΩ) Rhw/Rwl 32 100000 2.50 7.50 0.33 33 100001 2.58 7.42 0.35 34 100010 2.66 7.34 0.36 35 100011 2.73 7.27 0.38 36 100100 2.81 7.19 0.39 37 100101 2.89 7.11 0.41 38 100110 2.97 7.03 0.42 39 100111 3.05 6.95 0.44 40 101000 3.13 6.88 0.45 41 101001 3.20 6.80 0.47 42 101010 3.28 6.72 0.49 43 101011 3.36 6.64 0.51 44 101100 3.44 6.56 0.52 45 101101 3.52 6.48 0.54 46 101110 3.59 6.41 0.56 47 101111 3.67 6.33 0.58 48 110000 3.75 6.25 0.60 49 110001 3.83 6.17 0.62 50 110010 3.91 6.09 0.64 51 110011 3.98 6.02 0.66 52 110100 4.06 5.94 0.68 53 110101 4.14 5.86 0.71 54 110110 4.22 5.78 0.73 55 110111 4.30 5.70 0.75 56 111000 4.38 5.63 0.78 57 111001 4.45 5.55 0.80 58 111010 4.53 5.47 0.83 59 111011 4.61 5.39 0.86 60 111100 4.69 5.31 0.88 61 111101 4.77 5.23 0.91 62 111110 4.84 5.16 0.94 63 111111 4.92 5.08 0.97 64 1000000 5.00 5.00 1.00 65 1000001 5.08 4.92 1.03 66 1000010 5.16 4.84 1.06 67 1000011 5.23 4.77 1.10 68 1000100 5.31 4.69 1.13 69 1000101 5.39 4.61 1.17 70 1000110 5.47 4.53 1.21 71 1000111 5.55 4.45 1.25 72 1001000 5.63 4.38 1.29 73 1001001 5.70 4.30 1.33 74 1001010 5.78 4.22 1.37 75 1001011 5.86 4.14 1.42 76 1001100 5.94 4.06 1.46 77 1001101 6.02 3.98 1.51 78 1001110 6.09 3.91 1.56

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www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 Table1.ResistanceValues Table(continued) Step Binary Rwl (kΩ) Rhw (kΩ) Rhw/Rwl 79 1001111 6.17 3.83 1.61 80 1010000 6.25 3.75 1.67 81 1010001 6.33 3.67 1.72 82 1010010 6.41 3.59 1.78 83 1010011 6.48 3.52 1.84 84 1010100 6.56 3.44 1.91 85 1010101 6.64 3.36 1.98 86 1010110 6.72 3.28 2.05 87 1010111 6.80 3.20 2.12 88 1011000 6.88 3.13 2.20 89 1011001 6.95 3.05 2.28 90 1011010 7.03 2.97 2.37 91 1011011 7.11 2.89 2.46 92 1011100 7.19 2.81 2.56 93 1011101 7.27 2.73 2.66 94 1011110 7.34 2.66 2.76 95 1011111 7.42 2.58 2.88 96 1100000 7.50 2.50 3.00 97 1100001 7.58 2.42 3.13 98 1100010 7.66 2.34 3.27 99 1100011 7.73 2.27 3.41 100 1100100 7.81 2.19 3.57 101 1100101 7.89 2.11 3.74 102 1100110 7.97 2.03 3.92 103 1100111 8.05 1.95 4.12 104 1101000 8.13 1.88 4.33 105 1101001 8.20 1.80 4.57 106 1101010 8.28 1.72 4.82 107 1101011 8.36 1.64 5.10 108 1101100 8.44 1.56 5.40 109 1101101 8.52 1.48 5.74 110 1101110 8.59 1.41 6.11 111 1101111 8.67 1.33 6.53 112 1110000 8.75 1.25 7.00 113 1110001 8.83 1.17 7.53 114 1110010 8.91 1.09 8.14 115 1110011 8.98 1.02 8.85 116 1110100 9.06 0.94 9.67 117 1110101 9.14 0.86 10.64 118 1110110 9.22 0.78 11.80 119 1110111 9.30 0.70 13.22 120 1111000 9.38 0.63 15.00 121 1111001 9.45 0.55 17.29 122 1111010 9.53 0.47 20.33 123 1111011 9.61 0.39 24.60 124 1111100 9.69 0.31 31.00 125 1111101 9.77 0.23 41.67 Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 www.ti.com Table1.ResistanceValues Table(continued) Step Binary Rwl (kΩ) Rhw (kΩ) Rhw/Rwl 126 1111110 9.84 0.16 63.00 127 1111111 9.92 0.08 127.00

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www.ti.com SLIS144A –SEPTEMBER 2011–REVISED MARCH 2012 Changes from Original(September 2011)toRevisionA Page Copyright© 2011–2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):TPL0401A TPL0401B TPL0401C

www.ti.com 11-Jan-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPL0401A-10DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPL0401B-10DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPL0401C-50DCKR PREVIEW SC70 DCK 6 3000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 29-Feb-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPL0401A-10DCKR SC70 DCK 6 3000 202.0 201.0 28.0 TPL0401A-10DCKR SC70 DCK 6 3000 180.0 180.0 18.0 TPL0401B-10DCKR SC70 DCK 6 3000 202.0 201.0 28.0 TPL0401B-10DCKR SC70 DCK 6 3000 180.0 180.0 18.0 PACKAGE MATERIALS INFORMATION www.ti.com 29-Feb-2012 Pack Materials-Page 2

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