TPIC44L02 TI | Alldatasheet
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/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00684-Channel Serial-In Parallel-In Low-Side Pre-FET Driver /C0068Devices Are Cascadable /C0068Internal 55-V Inductive Load Clamp and V GS Protection Clamp for External Power FETs /C0068Independent Shorted-Load/Short-to- Battery Fault Detection on All Drain Terminals /C0068Independent OFF-State Open-Load Fault Sense /C0068Over-Battery-Voltage Lockout Protection and Fault Reporting /C0068Under-Battery Voltage Lockout Protection for the TPIC44L01 and TPIC44L02 /C0068Asynchronous Open-Drain Fault Flag /C0068Device Output Can Be Wire-ORed With Multiple Devices /C0068Fault Status Returned Through Serial Output Terminal /C0068Internal Global Power-On Reset of Device and External RESET Terminal /C0068High-Impedance CMOS-Compatible Inputs With Hysteresis /C0068TPIC44L01 and TPIC44L03 Disables the Gate Output When a Shorted-Load Fault Occurs /C0068TPIC44L02 Transitions the Gate Output to a Low-Duty Cycle PWM Mode When a Shorted-Load Fault Occurs
description
The TPIC44L01, TPIC44L02, and TPIC44L03 are low-side predrivers that provide serial and parallel input interfaces to control four external FET power switches such as offered in the TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown is provided on the TPIC44L01/L02. On the TPIC44L03 driver, only over-battery voltage shutdown is provided. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver must be minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated FLT VCOMPEN VCOMP IN0 IN1 IN2 IN3 CS SDO SDI SCLK VCC VBAT N/C RESET DRAIN0 GATE0 DRAIN1 GATE1 GATE2 DRAIN2 GATE3 DRAIN3 GND DB PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
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description (continued) Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted-load and open-load flags (bits 0–3) for each of the four output channels. A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS transfers the last four bits of serial data to the output buffer puts SDO in a high-impedance state and clears and reenables the fault register. The TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0 –3) output asynchronously. SCLK or CS is not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC . The drain voltage is compared to the fault reference when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t (STBDG) , to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this data sheet. These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of V CC and turnon voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from exceeding their rated voltages. An external active low RESET is provided to clear all registers and flags in the device. GATE(0–3) outputs are disabled after RESET has been pulled low. These devices provide pulldown resistors on all inputs except CS and RESET. A pullup resistor is used on CS and RESET .
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic diagram Parallel Register PREZ D QGND Serial Register Fault Logic SDO FLT STB and Open-Load Fault Protection OSC BIAS Vbg S B A Gate Drive Block DRAIN 0 DRAIN 1 DRAIN 2 DRAIN 3 GATE 0 GATE 1 GATE 2 GATE 3 OVLO † UVLO VCOMPEN VCOMP SDI SCLK CS IN 0 IN 1 IN 2 IN 3 VBAT VCC RST RST RST RST VCC RSTRESET † OVLO not on TPIC44L03
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NAME NO. I/O CS 8 I Chip select. A high-to-low transition on CS enables SDO, latches fault data into the serial interface, and refreshes FLT. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault data is latched into the serial output register and transferred using SDO and SCLK. On a low-to-high transition of CS, serial data is latched in to the output control register. DRAIN0 21 I FET drain inputs. DRAIN0 through DRAIN3 are used for both open-load and short-circuit fault detection at the DRAIN1 19 g drain of the external FETs. They are also used for inductive transient protection. DRAIN2 16 DRAIN3 14 FLT 1 I Fault flag. FLT is a logic level open-drain output that provides a real-time fault flag for shorted-load/ open-load/over-battery voltage/under-battery voltage faults. The device can be ORed with FLT terminals on other devices for interrupt handling. FLT requires an external pullup resistor. GATE0 20 O Gate drive output. GATE0 through GATE3 outputs are derived from the VBAT supply voltage. Internal clamps GATE1 18 g BAT yg prevent voltages on these nodes from exceeding the VGS rating on most FETs. GATE2 17 GATE3 15 GND 13 I Ground and substrate IN0 4 I Parallel gate driver. IN0 through IN3 are real-time controls for the gate predrive circuitry. They are CMOS IN1 5 gg g y y compatible with hysteresis. IN2 6 IN3 7 RESET 22 I Reset. A high-to-low transition of RESET clears all registers and flags. Gate outputs turn off and the FLT flag is cleared. SCLK 11 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of SDO on the falling edge of the serial clock. SDI 10 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a particular gate output on and a 0 turns it off. SDO 9 O Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high state. VBAT 24 I Battery supply voltage VCC 12 I Logic supply voltage VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an external fault reference (1) to be used in the shorted- and open-load fault detection circuitry. VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and open-load fault detection circuitry.
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions MIN NOM MAX UNIT Logic supply voltage, VCC 4.5 5 5.5 V Battery supply voltage, VBAT 8 24 V High-level input voltage, VIH 0.85 VCC VCC V Low-level input voltage, VIL 0 0.15 VCC V Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns Case temperature, TC –40 125 °C
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IBAT Supply current, VBAT All outputs off, VBAT = 12 V 300 500 700 µA ICC Supply current, VCC All outputs off, VBAT = 5.5 V 1 2.6 4.2 mA V(turnon) Turnon voltage, logic operational, VCC VBAT = 5.5 V, Check output functionality 2.6 3.5 4.4 V V(ovsd) Over-battery-voltage shutdown Gate disabled See Fig re 16 32 34 36 V Vhys(ov) Over-battery-voltage reset hysteresis Gate disabled, See Figure 16 0.5 1 1.5 V V(uvsd) Under-battery-voltage shutdown, (TPIC44L01/L02 only) Gate disabled See Fig re 17 4.1 4.8 5.4 V Vhys(uv) Under-battery-voltage reset hysteresis, (TPIC44L01/L02 only) Gate disabled, See Figure 17 100 200 300 mV V Gate dri e oltage 8 V < VBAT < 24 V, IO = 100 µA 7 13.5 V VG Gate drive voltage 5.5 V < VBAT < 8 V,IO = 100 µA 5 7 V IO(H) Maximum current output for drive terminals, pullup VO = GND 0.5 1.2 2.5 mA IO(L) Maximum current output for drive terminals, pulldown VO = 7 V 0.5 1.2 2.5 mA V(stb) Short-to-battery/shorted-load/open-load detection voltage VCOMPEN = L 1.1 1.25 1.4 V Vhys(stb) Short-to-battery hysteresis 40 100 150 mV VD(open) Open-load off-state detection voltage thresholdVCOMPEN = L 1.1 1.25 1.4 V Vhys(open) Open-load hysteresis 40 100 150 mV II(open) Open-load off-state detection current 30 60 80 µA II(PU) Input pullup current (CS) VCC = 5 V, VIN = 0 V 10 µA II(PD) Input pulldown current VCC = 5 V, VIN = 5 V 10 µA Vhys Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V VO(SH) High-level serial output voltage IO = 1 mA 0.8 VCC V VO(SL) Low-level serial output voltage IO = 1 mA 0.1 0.4 V IOZ(SD) 3-state current serial-data output VCC = 0 V to 5.5 V -10 1 10 µA VO(CFLT) Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V VI(COMP) Fault-external reference voltage, (TPIC44L01/L02 only) VCOMPEN = H 0.25 3 V VI(COMP) Fault-external reference voltage, (TPIC44L03 only) VCOMPEN = H 1 3 V VC Output clamp voltage, (TPIC44L01/L02 only)dc < 1%, tw = 100 µs 47 55 63 V VC Output clamp voltage, (TPIC44L03 only) dc < 1%, tw = 100 µs 47 53.5 60 V
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tsu(1) SCLK CS SDI th tsu Figure 6 tpd(2) SCLK CS tpd(1) 3-StateSDO Figure 7 tpd(3) CS SDO 50% 3-State Figure 8 3-STATE 90% 10% tr(2) SDO Figure 9 3-STATE 90% 10% tf(2) SDO Figure 10 FLT tr(3) 90% 10% 90% 10% tf(3) Figure 11 FLT
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION serial data operation The TPIC44L01, TPIC44L02, and TPIC44L03 offer serial input interface to the microcontroller to transfer control data to the predriver and fault data back to the controller. The serial input interface consists of: /C0068SCLK – Serial clock /C0068CS – Chip select /C0068SDI – Serial data input /C0068SDO – Serial data output Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK after CS has transitioned from 1 to 0. Four clock cycles are required to shift the first bit from the LSB to the most significant bit (MSB) of the shift register. Four clock cycles must occur before CS transitions high for proper control of the outputs. Less than four clock cycles result in fault data being latched into the output control buffer. Eight bits of data can be shifted into the device, but the first 4 bits shifted out are always the fault data and the last 4 bits shifted in are always the output control data. A low-to-high transition on CS latches the contents of the serial shift register into the output control register. A logic 0 input to SDI turns the corresponding parallel output off and a logic 1 input turns the output on (see Figure 12). GATE3 ON GATE2 ON GATE1 OFF GATE0 OFF 12 34 Present Output Data New Data 3-State FLT3 FLT2 FLT1 FLT0 IN3 3-State SCLK CS SDI New Data Output Control Register Data SDO (a) 4-Bit Serial Word Example Figure 12
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Present Output Data New Data FLT0 NA NA NA NA IN3 3-State SCLK CS Output Control Register Data SDO 56 78 Don ’t Care 3-State FLT3 FLT2 FLT1 New Data SDI (b) 8-Bit Serial Word Example (Single Predriver) 12 34 FLT4 FLT3 FLT2 FLT1 FLT0 IN7 3-State SCLK CS SDO 56 78 3-State FLT7 FLT6 FLT5 New Data (c) 8-Bit Serial Word Example (Cascade: Two Predrivers) IN 4 IN 3 IN 2 IN 1 IN 0 NASDI IN 7 IN 6 IN 5 GATE7 –GATE4 (2nd stage) GATE3 –GATE0 (1st stage) Figure 12 (continued)
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION serial data operation (continued) Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available after CS is transitioned low. The remaining 3 bits of fault data are shifted out in the following three clock cycles. Fault data is latched into the serial register when CS is transitioned low. A fault must be present on the high to low transition of CS to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data has been clocked into the device. The rising edge of CS inhibits SDI, puts SDO into a high-impedance state, latches the 4 bits of serial data into the output control register, and clears and reenable the serial fault registers (see Figure 13). When a shorted-load condition occurs with the TPIC44L01 or TPIC44L03, then the controller must disable and reenable the channel to clear the fault register and FLT . The TPIC44L02 automatically retries the output and the fault clears after the fault condition has been corrected. 12 34 3-State FLT3 FLT2 FLT1 FLT0 IN3 3-State SCLK CS SDO Figure 13 parallel input data operation In addition to the serial interface, the TPIC44L01, TPIC44L02, and TPIC44L03 also provides a parallel interface to the microcontroller. The output turns on when either the parallel or the serial interface commands it to turn on. The parallel data terminals are real-time control inputs for the output drivers. SCLK and CS are not required to transfer parallel input data to the output buffer. Fault data must be read over the serial data bus as described in the serial data operation section of this data sheet. The parallel input must be transitioned low and then high to clear and reenable a gate output after it has been disabled due to a shorted-load fault condition.
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
chipset performance under fault conditions The TPIC44L01, TPIC44L02, TPIC44L03, and power FET arrays are designed for normal operation over a battery-voltage range of 8 V to 24 V with load-fault detection from 4.8 V to 34 V. The TPIC44L01, TPIC44L02, and TPIC44L03 offer onboard fault detection to handle a variety of faults that may occur within a system. The circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs. Note that unused DRAIN0-DRAIN3 inputs must be connected to V BAT through a pullup resistor to prevent false reporting of open-load fault conditions. The circuitry detects the fault, shuts off the output to the FET, and reports the fault to the microcontroller. The primary faults under consideration are: 1. Shorted load 2. Open load 3. Over-battery voltage shutdown 4. Under-battery voltage shutdown (TPIC44L01 and TPIC44L02 only) NOTE: An undervoltage fault may be detected when VCC and VBAT are applied to the device. The controller should initialize the fault register after power up to clear any false fault reports. shorted-load fault condition The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain voltage of each channel to detect shorted-load conditions. The onboard deglitch timer starts running when the gate output to the power FET transitions from the off state to the on state. The timer provides a 60-µs deglitch time, t (STBFM) , to allow the drain voltage to stabilize after the power FET has been turned on. The deglitch time is only enabled for the first 60 µs after the FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than the fault reference voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch time, t (STBDG) , FLT flags the microcontroller that a fault condition exists and the gate output is automatically shut off (TPIC44L01 and TPIC44L03) until the error condition has been corrected. An overheating condition on the FET occurs when the controller continually tries to reenable the output under shorted-load fault conditions. When a shorted-load fault is detected using the TPIC44L02, the gate output is transitioned into a low-duty cycle, PWM signal to to protect the FET from overheating. The PWM rate is defined as t (SB) and the pulse width is defined as tw. The gate output remains in this state until the fault has been corrected or until the controller disables the gate output. The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition. Fault bits 0-3 distinguish faults for each of the output channels. When a shorted-load condition occurs with the TPIC44L01 or TPIC44L03, the controller must disable and reenable the channel to clear the fault register and FLT . The TPIC44L02 automatically retries the output and the fault clears after the fault condition has been corrected. Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET is turned on and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates below the reference point set at U1. The output of U1 is low and a fault condition is not flagged.
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION t(STBFM) t(STBFM) Glitches Glitches tw t(SB) GATE0 – GATE3 Input DRAIN0 – DRAIN3 FLT NORMAL SHORTED-LOAD TPIC44L02 N-Channel Load VBAT External TPIC44L01/L02 1.25 V Deglitch FLT Input From TPIC44L01/L02 GATE0 – GATE3 Glitches t(STBDG) Input DRAIN0 – DRAIN3 FLT GATE0 – GATE3 Input DRAIN0 – DRAIN3 FLT GATE0 – GATE3 SHORTED-LOAD TPIC44L01 and TPIC44L03 t(STBDG) t(STBFM) Figure 14
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain of each power FET for open circuit conditions that may exist. The 60-µA current source is provided to monitor open load fault conditions. Open-load faults are only detected when the power FET is turned off. When load impedance is open or substantially high, the 60-µA current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection circuit. Unused DRAIN0–DRAIN3 inputs must be connected to V BAT through a pullup resistor to prevent false reporting of open-load fault conditions. The onboard deglitch timer starts running when the TPIC44L01, TPIC44L02, and TPIC44L03 gate output to the power FET transitions to the off state. The timer provides a 60-µs deglitch time, t (STBFM) to allow the drain voltage to stabilize after the power FET has been turned off. The deglitch time is only enabled for the first 60 µs after the FET has been turned off. After the deglitch delay time, the drain is checked to verify that it is greater than the fault reference voltage. When it is less than the reference voltage, a fault is flagged to the microcontroller through FLT that an open-load fault condition exists. The microcontroller can then read the serial port on the TPIC44L01, TPIC44L02, and TPIC44L03 to isolate which channel reported the fault condition. Fault bits 0–3 distinguish faults for each of the output channels. Figure 15 illustrates the operation of the open-load detection circuit. This feature provides useful information to the microcontroller to isolate system failures and warn the operator that a problem exists. Examples of such applications would be a warning that a light bulb filament may be open, solenoid coils may be open, etc. NORMAL N-Channel Load VBAT External TPIC44L01/L02/L03 1.25 V Deglitch FLT Input From TPIC44L01/L02/L03 60 µA t(STBFM) Glitches Input DRAIN0 – DRAIN3 FLT OPEN-LOAD NORMAL GATE0 – GATE3 Input DRAIN0 – DRAIN3 FLT GATE0 – GATE3 t(STBFM) Figure 15
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION over-battery-voltage shutdown The TPIC44L01,TPIC44L02, and TPIC44L03 monitor the battery voltage to prevent the power FETs turning on in the event that the battery voltage is too high. This condition may occur due to voltage transients resulting from a loose battery connection. The TPIC44L01, TPIC44L02, and TPIC44L03 turns the power FET off when the battery voltage is above 34 V to prevent possible damage to the load and the FET. GATE(0–3) output goes back to normal operation after the overvoltage condition has been corrected. An over-battery voltage fault is flagged to the controller through FLT . The over-battery voltage fault is not reported in the serial fault word. When an overvoltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are reenabled after the battery fault condition has been corrected. When the fault condition is removed before the CS signal transitions low, the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of CS provided no other faults are present in the device. Figure 16 illustrates the operation of the over-battery voltage detection circuit. VBAT 34 V 34 V
33 V12 VVBAT
GATE0 –GATE3 Output Disable Figure 16
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
under-battery-voltage shutdown (TPIC44L01 and TPIC44L02 only) The TPIC44L01 and TPIC44L02 monitor the battery voltage to prevent the power FETs from being turned on in the event that the battery voltage is too low. When the battery voltage is below 4.8 V, then GATE0–GATE3 may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result in a thermal stress on the FET. The output goes back to normal operation after the undervoltage condition has been corrected. An under-battery voltage fault is flagged to the controller through FLT . The under-battery voltage fault is not reported in the serial fault word. When an under-battery voltage condition occurs, the device reports the battery fault but disables fault reporting for open- and shorted-load conditions. When the fault condition is removed before the CS signal transitions low, the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of CS provided no other faults are present in the device. Figure 17 illustrates the operation of the under-battery voltage detection circuit. VBAT 4.8 V 4.8 V 5 V 12 V VBAT GATE0 –GATE3 Output Disable Figure 17
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION inductive voltage transients A typical application for the predriver/power FET circuit is to switch inductive loads. When an inductive load is switched off, a large voltage spike can occur. These spikes can exceed the maximum VDS rating for the external FET and damage the device when the proper protection is not in place. The FET can be protected from these transients through a variety of methods using external components. The TPIC44L01, TPIC44L02, and TPIC44L03 offer that protection in the form of a Zener diode stack connected between the DRAIN input and GATE output (see Figure 18). Zener diode Z1 turns the FET on to dissipate the transient energy. GATE diode Z2 is provided to prevent the gate voltage from exceeding 13 V during normal operation and transient protection. DRAIN GATE LOAD
55 VZ1
TPIC44L01/L02/L03 External Figure 18
/C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0049/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0050/C0044 /C0084/C0080/C0073/C0067/C0052/C0052/C0076/C0048/C0051 /C0052/C0262/C0067/C0072/C0065/C0078/C0078/C0069/C0076 /C0083/C0069/C0082/C0073/C0065/C0076 /C0065/C0078/C0068 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0076/C0079/C0087/C0262/C0083/C0073/C0068/C0069 /C0080/C0082/C0069/C0262/C0070/C0069/C0084 /C0068/C0082/C0073/C0086/C0069/C0082 SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
external fault reference input The TPIC44L01, TPIC44L02, and TPIC44L03 compare each channel drain voltage to a fault reference to detect shorted-load and open-load conditions. The user has the option of using the internally generated 1.25-V fault reference or providing an external reference voltage through VCOMP. The internal reference is selected by connecting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to V CC (see Figure 19). Proper layout techniques should be used in the grounding network for the VCOMP circuit on the TPIC44L01, TPIC44L02, and TPIC44L03. The ground for the predriver and VCOMP network should be connected to a Kelvin ground if available; otherwise, they should make single-point contact back to the power ground of the FET array. Improper grounding techniques can result in inaccuracies in detecting faults. A M U X 1.25 V DRAIN3 DRAIN0 VCOMP VCOMPEN Deglitch FLT External TPIC44L01/L02/L03 VCOMPEN 1.25 V VCOMP Figure 19
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPIC44L01DB Obsolete Production SSOP (DB) | 24 - - Call TI Call TI - TPIC44L01 TPIC44L01DBR Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC44L01 TPIC44L01DBR.A Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC44L01 TPIC44L02DB Obsolete Production SSOP (DB) | 24 - - Call TI Call TI -40 to 125 TPIC44L02 TPIC44L02DBR Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - TPIC44L02 TPIC44L02DBR.A Active Production SSOP (DB) | 24 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC44L02 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 23-May-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC44L01DBR SSOP DB 24 2000 356.0 356.0 35.0 TPIC44L02DBR SSOP DB 24 2000 356.0 356.0 35.0 Pack Materials-Page 2
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01
28 PINS SHOWN
8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated