TPIC2810DR.A

TPIC2810 TI | Alldatasheet

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Technical content

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Low rDS(on) ...5 Ω Typical /C0068Eight Power DMOS Transistor Outputs of 100-mA Continuous Current /C0068210-mA Current Limit Capability /C0068Drain Output ESD Protection. . . 3000 V /C0068Output Clamp Voltage...4 0 V

description

The TPIC2810 device is a monolithic, medium- voltage, low-current, 8-bit shift register design to drive low-side switched resistive loads such as LEDs. The device is not recommended for switching inductive loads. This device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through the shift register via an I 2C bus interface. Data is transferred into the data shift register only after the group ID and device address have been verified. The subaddress directs the I2C bus interface to read or write data to the device or transfer data to the output. When output enable (G) is held high, all drain outputs are off. When G is held low, data from the output storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The TPIC2810 device has an internal power-up clear to initialize all registers to an off state when power is applied to the device. It also has a thermal sensor to monitor the die temperature and shut the drain outputs off, if an over current condition occurs. Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 100 mA continuous sink-current capability. Each output provides a 210-mA maximum current limit at T C = 25°C. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 3000 V of ESD protection on output terminals and 2000 V of ESD protection on input terminals when tested using the human-body model. The TPIC2810 device is characterized for operation over the operating case temperature range of −40°C to 125°C. Copyright  2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VCC SDA DRAIN0 DRAIN1 DRAIN2 DRAIN3 G GND SCL DRAIN7 DRAIN6 DRAIN5 DRAIN4 D PACKAGE (TOP VIEW) /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

See the TPIC2810 subaddress and I2C protocol definition section of this data sheet for definition of the 11H, 22H, and 44H control signals.

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION A0 9 I Address input 0 A1 10 I Address input 1 A2 7 I Address input 2 DRAIN0 3 DRAIN1 4 DRAIN2 5 DRAIN3 6 O FET drain outputs. The DRAIN terminals are low-side switches for resistive loads.DRAIN4 11 O FET drain outputs. The DRAIN terminals are low-side switches for resistive loads. DRAIN5 12 DRAIN6 13 DRAIN7 14 G 8 I Output enable. Active low input enables output FETs when low and disables output FETs when high. GND 16 O Ground SCL 15 I Serial clock SDA 2 I/O Open drain, bidirectional serial data terminal VCC 1 I Supply voltage input schematic of inputs and outputs Equivalent of Each Input VCC GND Input 7 V RC Filter is Not Present On A0, A1, and A2 Inputs Typical of All Drain Outputs Drain GND 6.5 V 42 V

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. DISSIPATION RATING TABLE PACKAGE TC = 25°C POWER RATING DERATING FACTOR ABOVE T C = 25°C TC = 125°C POWER RATING D 1087 mW 8.7 mW/°C 217 mW recommended operating conditions MIN MAX UNIT Logic supply voltage, VCC 3.0 5.5 V High-level input voltage, VIH 0.7VCC V Low-level input voltage, VIL 0.3VCC V Pulse drain output current, TC = 25°C, VCC = 5 V, all outputs on (see Notes 3 and 4 and Figure 8) 210 mA Operating case temperature, TC −40 125 °C NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%. 4. Technique must limit TJ − TC to 10°C maximum.

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Logic supply voltage 3 5.5 V V(BR)DSX Drain-to-source breakdown voltageID = 1 mA 40 V VSD Source-to-drain diode forward voltage IF = 100 mA 0.85 1.2 V VPUC Power-up clear voltage VCC rising no load, See Note 5 2.84 V IIH High-level input current VCC = 5.5 V, VI = VCC 1 µA IIL Low-level input current VCC = 5.5 V, VI = 0 −1 µA VHYS Digital input hysteresis 1.1 V ICC Logic supply current VCC = 5.5 V All outputs off 0.62 1 mAICC Logic supply current V CC = 5.5 V All outputs on 0.7 1 mA ICC(FRQ) Logic supply current at frequencyfSCL = 100 kHz, All outputs off, C L = 30 pF, See Figure 3 0.74 1 mA IOL Low level output current; SDA VOL = 0.4 V 13 mA IL Leakage current; SDA VI = VCC −1 1 µA IN Nominal current VDS(on) = 0.5 V, TC = 85°C, IN = ID , See Notes 4, 6, 7 75 mA IDSX Off-state drain current VDS = 30 V VCC = 5.5 V 0.3 0.6 AIDSX Off-state drain current VDS = 30 V, TC = 125°C VCC = 5.5 V 0.3 0.6 µA TTSD Thermal shutdown set points 160 °C THYS Thermal shutdown hysteresis 10 20 30 °C ID = 100 mA, VCC = 3 V 8.0 10.8 ID = 100 mA, VCC = 4.5 V 5.1 6.9 rDS(on) Static drain-source on-state resistance ID = 100 mA, VCC = 3.0 V, TC = 125°C See Notes 4 and 6 and Figures 4 and 5 13.0 18.2 Ωresistance ID = 100 mA, VCC = 4.5 V, TC = 125°C and Figures 4 and 5 8.0 11.2 NOTES: 4. Technique must limit TJ − TC to 10°C maximum 5. The power-up clear resets the I2C interface and clears all outputs. 6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage of 0.5 V at TC = 85°C.

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, TC = 25°C, CL = 100 pF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output from GC L = 30 pF, 1.15 tPHL Propagation delay time, high-to-low-level output from G C L = 30 pF, ID = 75 mA, See Figures 1, 2, and 6 0.64 µs tr(OUT) Rise time, drain output ID = 75 mA, See Figures 1, 2, and 6 1.05 µs tf(OUT) Fall time, drain output 0.89 µs 100 kHz f(SCL) Serial clock frequency 400 kHz f(SCL) Serial clock frequency

2 MHz

t(BUF) Bus free time between stop and start condition SCL = 100 kHz 4.7 st(BUF) Bus free time between stop and start condition SCL = 400 kHz 1.3 µs t(SP) Tolerable spike width on bus 50 ns tpd(ACK) SCL low to data out valid (acknowledge) 120 ns SCL = 100 kHz 4.7 s tLOW SCL low time SCL = 400 kHz 1.3 µs tLOW SCL low time SCL = 2 MHz 250 ns SCL = 100 kHz 4.0 µs tHIGH SCL high time SCL = 400 kHz 600 ns tHIGH SCL high time SCL = 2 MHz 200 ns SCL = 100 kHz 250 tsu(DAT) SDA → SCL setup time SCL = 400 kHz 100 nstsu(DAT) SDA → SCL setup time SCL = 2 MHz 10 ns SCL = 100 kHz 4.7 µs tsu(STA) Start condition setup time SCL = 400 kHz 600 ns tsu(STA) Start condition setup time SCL = 2 MHz 300 ns SCL = 100 kHz 4 µs tsu(STO) Stop condition setup time SCL = 400 kHz 600 ns tsu(STO) Stop condition setup time SCL = 2 MHz 140 ns th(DAT) SDA → SCL hold time 50 ns SCL = 100 kHz 4 µs th(STA) Start condition hold time SCL = 400 kHz 600 ns SCL = 2 MHz 160 ns SCL = 100 kHz 1000 tr(SCL) Rise time of SCL signal SCL = 400 kHz 300 nstr(SCL) Rise time of SCL signal SCL = 2 MHz 70 ns SCL = 100 kHz 300 tf(SCL) Fall time of SCL signal SCL = 400 kHz 300 nstf(SCL) Fall time of SCL signal SCL = 2 MHz 70 ns SCL = 100 kHz 1000 tr(SDA) Rise time of SDA signal SCL = 400 kHz 300 nstr(SDA) Rise time of SDA signal SCL = 2 MHz 70 ns SCL = 100 kHz 300 tf(SDA) Fall time of SDA signal SCL = 400 kHz 300 nstf(SDA) Fall time of SDA signal SCL = 2 MHz 140 ns

NOTES: A. The word generator has the following characteristics: tr ≤ 30 ns, tf ≤ 30 ns, pulsed repetition rate (PRR) = 400 kHz, ZO = 50 Ω. B. C L includes probe and jig capacitance.

15 V5 V

Figure 1. Resistive-Load Test Circuit and Voltage Waveforms

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NOTES: A. The word generator has the following characteristics: tr ≤ 30 ns, tf ≤ 30 ns, pulsed repetition rate (PRR) = 400 kHz, ZO = 50 Ω. B. C L includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times and Voltage Waveforms

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Figure 5. Static Drain-Source On-State Resistance vs Figure 6. Switching Time vs Case Temperature

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Figure 9. Normalized Junction-to-Ambient Thermal Resistance vs Pulse Duration

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION TPIC2810 subaddress and I2C protocol definition subaddress definition: Summary: HEX Value R/W Bit Function 11H 1 Read data from the input register 11H 0 Write data to the data shift register, do not transfer to output register 22H 0 Command to transfer data from the data shift register to the output storage register 44H 0 Write data to the data shift register and transfer it to the output storage register immediately (extra load 22H command not needed) Other x No action on undefined subaddresses All other undefined subaddress values are not acknowledged. register definition: /C0068The data shift register receives serial data from the I2C interface. /C0068The data shift register receives data from the input interface and holds it until it is transferred to the output storage register. /C0068The output storage register controls whether the FET is on or off. TPIC2810 I2C input interface protocol definition S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 AS0 Slave Address and R/W Subaddress D7 D6 D5 D4 D3 D2 D1 AD0 Data P S G A(0:2) RW A Subaddress Data P Start Condition Group ID: Defined as 1100 Device Address Selectable Via Input Terminals Read/Write Select Bit Acknowledge Defined Per Subaddress Table Data to Be Loaded Into the Shift and Output Registers Stop Condition

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Case 1: Read/Write serial data, but do not load output register This case loads the data shift register with data via the I2C interface. Data is not transferred to the output storage register. write operation: S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 AS0 Slave Address and R/W = 0 Subaddress 11H D7 D6 D5 D4 D3 D2 D1 AD0 Data to Slave P G[3:0]: A[2:0]: RW: Subaddress: Data: Acknowledge: Fixed at 1100 Selectable Via Input Terminals 0 = Write Shift Register 11H (0001 0001) Output Data to the TPIC2810 Device Occurs After Valid Address Byte, After the Subaddress Byte, and After the Data Byte read operation: G3 G2 G1 G0 A2 A1 A0 RW A Slave Address and R/W = 1 D7 D6 D5 D4 D3 D2 D1 D0 Data From Slave P G[3:0]: A[2:0]: RW: Subaddress: Data: Acknowledge: Fixed at 1100 Selectable Via Input Terminals 1 = Read Shift Register (Note the Slave Address RW Bit = 0) 11H (0001 0001) Input Data From the TPIC2810 Device Occurs After Valid Address Byte and After the Subaddress Byte S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 AS0 Slave Address and R/W = 0 Subaddress 11H NAS

/C0084/C0080/C0073/C0067/C0050/C0056/C0049/C0048 /C0056/C0262/C0066/C0073/C0084 /C0076/C0069/C0068 /C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0073/C0050/C0067 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 SLIS109A − DECEMBER 2001 − REVISED SEPTEMBER 2002 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION Case 2: Transfer serial data to output storage register This case transfers data from the data shift register to the output storage register. The transfer must occur during the subaddress acknowledge bit and the data byte is ignored. S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 AS0 Slave Address and R/W = 0 Subaddress 22H P G[3:0]: A[2:0]: RW: Subaddress: Data: Acknowledge: Fixed at 1100 Selectable Via Input Terminals 0 = Write Shift Register 22H (0010 0010) Output Data to the TPIC2810 Device Occurs After Valid Address Byte and After the Subaddress Byte Case 3: Read serial data and load output storage register This case loads the data shift register with data via the I2C interface and transfers the data to output storage register, if R/W = 0. The transfer occurs during the acknowledge bit following the data byte. Data byte and transfer to the output register is ignored if R/W = 1. S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 AS0 Slave Address and R/W = 0 Subaddress 44H D7 D6 D5 D4 D3 D2 D1 AD0 Data to Slave P G[3:0]: A[2:0]: RW: Subaddress: Data: Acknowledge: Fixed at 1100 Selectable Via Input Terminals 0 = Write Shift Register 44H (0100 0100) Output Data to the TPIC2810 Device Occurs After Valid Address Byte, After the Subaddress Byte and After the Data Byte Case 4: Undefined subaddress values S G3 G2 G1 G0 A2 A1 A0 RW A S7 S6 S5 S4 S3 S2 S1 S0 Slave Address and R/W = x Subaddress Undefined Don’t Care P G[3:0]: A[2:0]: RW: Subaddress: Data: Acknowledge: Fixed at 1100 Selectable Via Input Terminals Don’t Care All Bit Combinations Except 11H, 22H, and 44H Don’t Care; Data Is Ignored Occurs After Valid Address Byte, But Is Not Issued After an Undefined Subaddress Byte or After the Data Byte Following an Undefined Subaddress Byte NA

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

portion of the data transmission. of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. Figure 10. The device acknowledges each byte of data that it receives from the controller. Figure 10. Start/Stop/Acknowledge Protocol

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPIC2810D Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC2810 TPIC2810D.A Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC2810 TPIC2810DG4 Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM - TPIC2810 TPIC2810DG4.A Active Production SOIC (D) | 16 40 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC2810 TPIC2810DR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC2810 TPIC2810DR.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC2810 TPIC2810DRG4 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - IC2810 TPIC2810DRG4.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 IC2810 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC2810DR SOIC D 16 2500 350.0 350.0 43.0 TPIC2810DRG4 SOIC D 16 2500 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) TPIC2810D D SOIC 16 40 505.46 6.76 3810 4 TPIC2810D.A D SOIC 16 40 505.46 6.76 3810 4 TPIC2810DG4 D SOIC 16 40 505.46 6.76 3810 4 TPIC2810DG4.A D SOIC 16 40 505.46 6.76 3810 4 Pack Materials-Page 3

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