TPIC2701MJ

TPIC2701 TI | Alldatasheet

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7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Seven 0.5-A Independent Output Channels /C0068Integrated Clamp Diode With Each Output /C0068Low rDS(on) . . . 0.5 Ω Typical /C0068Output Voltage. . . 60 V /C0068Pulsed Current...3 A Per Channel /C0068Avalanche Energy...2 2 m J

description

The TPIC2701 is a monolithic power DMOS transistor array that consists of seven indepen- dent N-channel enhancement-mode DMOS transistors connected in a common-source configuration with open drains. The TPIC2701 is pin-for-pin functionally compatible with the Texas Instruments ULN2001A through ULN2004A. The TPIC2701 is characterized for operation over a temperature range of 0°C to 125 °C.The TPIC2701M is characterized for operation over the full military temperature range of –55°C to 125°C. logic diagram CLAMP DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 GATE1 GATE2 GATE3 GATE4 GATE5 GATE6 GATE7 SOURCE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. GATE1 GATE2 GATE3 GATE4 GATE5 GATE6 GATE7 SOURCE DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 DRAIN7 CLAMP GATE1 GATE2 GATE3 NC NC GATE4 GATE5 NC GATE6 GATE7 SOURCE SOURCE DRAIN1 DRAIN2 DRAIN3 NC NC DRAIN4 DRAIN5 NC DRAIN6 DRAIN7 CLAMP SOURCE TPIC2701M J PACKAGE † (TOP VIEW) NC – No internal connection TPIC2701 N PACKAGE (TOP VIEW) † Refer to the mechanical data for the JW package.

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996

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absolute maximum ratings over operating case temperature range (unless otherwise noted) NOTE 1: Pulse duration = 10 ms, duty cycle = 6%. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING J 2660 mW 21.3 mW/°C 1701 mW 1382 mW 530 mW N 1400 mW 11.0 mW/°C 905 mW 740 mW 300 mW electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TPIC2701 UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(BR)DS Drain-source breakdown voltage ID = 1 µA, V GS = 0 60 V VTGS Gate-source threshold voltage ID = 1 mA, V DS = VGS 1.2 1.75 2.4 V VDS(on) Drain-source on-state voltage ID = 0.5 A, V GS = 15 V, See Notes 2 and 3 0.25 0.4 V IDSS Zero gate voltage drain current VDS =4 8V VGS =0 TC = 25°C 0.05 1 µAIDSS Zero-gate-voltage drain current VDS = 48 V, VGS = 0 TC = 125°C 0.5 10 µA IGSSF Forward gate current, drain short circuited to source VGS = 20 V, VDS = 0 10 100 nA IGSSR Reverse gate current, drain short circuited to source VGS = –20 V, VDS = 0 10 100 nA rDS( ) Forward drain source on state resistance VGS = 15 V, ID = 0.5 A, See Notes 2 and 3 and TC = 25°C 0.5 0.8 ΩrDS(on) Forw ard drain-source on-state resistance See N otes 2 and 3 and Figures 5 and 6 TC = 125°C 0.8 1.3 Ω gfs Forward transconductance VDS = 15 V, ID = 0.5 A, See Notes 2 and 3 0.5 0.8 S C iss Short-circuit input capacitance, common source 105 C oss Short-circuit output capacitance, common sourceVDS =2 5V V GS =0 f = 300 kHz 65 pF C rss Short-circuit reverse transfer capacitance, common source VDS = 25 V, VGS = 0, f = 300 kHz F NOTES: 2. Technique should limit TJ – TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts with a single output transistor conducting.

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over case temperature operating range (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS TC † TPIC2701M UNITPARAMETER TEST CONDITIONS TC † MIN TYP MAX UNIT V(BR)DS Drain to source breakdown voltage ID = 1 µA, VGS = 0 25°C

60 VV(BR)DS Drain-to-source breakdow n voltage

ID = 1 mA, VGS = 0 Full range 60 V VTGS Gate-to-source input threshold voltage ID = 1 mA, VDS = VGS Full range 1.2 1.75 2.4 V VDS( ) Drain to source on state voltage ID =05A VGS =1 5V 25°C 0.25 0.45 VVDS(on) Drain-to-source on-state voltage ID = 0.5 A, VGS = 15 V Full range 0.65 V IDSS Zero gate voltage drain current VDS =4 8V VGS =0 25°C 0.05 1 µAIDSS Zero-gate-voltage drain current VDS = 48 V, VGS = 0 Full range 10 µA IGSSF Forward gate current, drain short-circuited toVGS =2 0V V DS =0 25°C 10 100 nA IGSSF source VGS = 20 V, VDS = 0 Full range 10 µA IGSSR Reverse gate current, drain short-circuited toVGS =2 0 V V DS =0 25°C 10 100 nA IGSSR source VGS = –20 V, VDS = 0 Full range 10 µA rDS( ) Forward drain source on state resistance VGS =1 5V I D =05A 25°C 0.5 0.9 ΩrDS(on) Forw ard drain-source on-state resistance VGS = 15 V, ID = 0.5 A Full range 1.3 Ω gfs Forward transconductance VDS = 15 V, ID = 0.5 A 25°C 0.8 S C iss Short-circuit input capacitance, common source 105 C oss Short-circuit output capacitance, common sourceVDS = 25 V, VGS = 0, Full range 65 pF C rss Short-circuit reverse transfer capacitance, common source f = 300 kHz Full range F † Full range is –55°C to 125°C. NOTE 4: Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. source-drain diode characteristics, TC = 25°C PARAMETER TEST CONDITIONS TPIC2701 UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSD Forward On voltage IS = 0.5 A, VGS = 0 0.9 1.4 V trr(SD) Reverse-recovery time IS = 0.5 A, VGS = 0, VDS = 48 V, 165 ns Q RR Total source-drain diode charge SG S di/dt = 25 A/µs, DS See Figure 1 250 nC source-to-drain diode characteristics over operating case temperature range (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS TPIC2701M UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSD Forward On voltage IS = 0.5 A, V GS = 0 0.9 1.4 V trr Reverse recovery time IS = 0.5 A, V GS = 0, VDS = 48 V, 165 ns Q RR Total source-to-drain diode charge SG S di/dt = 25 A/µs, T C = 25°C, DS See Figure 1 250 nC NOTE 4: Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately.

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996

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clamp diode characteristics, TC = 25°C PARAMETER TEST CONDITIONS TPIC2701 UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VF Forward on-voltage IF = 0.5 A 1 1.5 V VBR Breakdown voltage IR = 1 µA 60 V IR Reverse leakage current VR = 48 V 0.05 1 µA trr(CD) Reverse-recovery time IF = 0.1 A, di/dt = 25 A/µs, 90 ns Q RR Total source-drain diode charge F VCD = 48 V, µ See Figure 1 100 nC clamp diode characteristics over operating case temperature range (unless otherwise noted) (see Note 4) PARAMETER TEST CONDITIONS TPIC2701M UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT VF Forward voltage IF = 0.5 A 1 1.5 V V(BR) Breakdown voltage IR = 1 µA, TC = 25°C

60 VV(BR) Breakdow n voltage

IR = 1 mA 60 V IR Reverse leakage current VR =4 8V TC = 25°C 0.05 1 µAIR Re verse leakage current VR = 48 V µA trr(SD) Reverse recovery time, source-to-drain IF = 0.1 A, di/dt = 25 A/µs, T C = 25°C 90 ns Q RR Total source-to-drain diode charge F VCD = 48 V, µ C See Figure 1 100 nC NOTE 4: Pulse testing techniques are used to maintain the virtual junction temperature as close to the case temperature as possible. Thermal effects must be taken into account separately. resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS TPIC2701 UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 10 td(off) Turn-off delay time VDD = 25 V, R L = 100 Ω ,t en = 10 ns, 30 ns tr Rise time DD , tdis = 10 ns, L , See Figure 2 en , ns tf Fall time 5 Q g Total gate charge V4 8 V I 0 25 A V1 0 V 2.8 3.6 Q gs Gate-source charge VDS = 48 V, See Figure 3 ID = 0.25 A, VGS = 10 V, 1.6 2 nC Q gd Gate-drain charge See Figure 3 1.2 1.6

effects must be taken into account separately. Figure 1. Reverse-Recovery-Current Waveforms of Source-Drain and Clamp Diodes

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Figure 2. Resistive Switching Figure 3. Gate Charge Test Circuit and Waveform

NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω . B. Input pulse duration (tw ) is increased until peak current IAS = 2.5 A. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996

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0.3 0.2 0.1 0.4 0.5 0.6 0.7 0.8 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs FREE-AIR TEMPERATURE TA – Free-Air Temperature – °C ΩOn-State Resistance – rDS(on) – Static Drain-Source 0.9 VGS = 15 V VGS = 10 V 0 125 50– 50 – 25 25 100 75 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT ID – Drain Current – A ΩOn-State Resistance – rDS(on) – Static Drain-Source 0.5 0.4 0.2 0.1 0.9 0.3 0 0.5 1 1.5 0.7 0.6 0.8 2 2.5 VGS = 6 V VGS = 15 V VGS = 20 V ID = 0.5 A TA = 25°C Figure 5 Figure 6 0.76 0.775 0.79 0.805 0.82 DISTRIBUTION OF FORWARD TRANSCONDUCTANCE gfs – Forward Transconductance – S Percentage of Units – % 2.5 0.5 4.5 1.5 0 2 10 14 3.5 DRAIN-TO-SOURCE CURRENT vs DRAIN-TO-SOURCE VOLTAGE I – Drain-to-Source Current – AD VDS – Drain-to-Source Voltage – V 12 18 1646 8 VGS = 5 V VGS = 4.5 V VGS = 4 V VGS = 3.5 V VGS = 3 V TA = 25°C ID = 0.5 A VDS = 15 V TA = 25°C VGS = 2.5 V Figure 7 Figure 8

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996

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Clamp-Diode Voltage – V 2.5 0.5 1.5 0 0.2 1 1.4 Clamp-Diode Current – A CLAMP-DIODE REVERSE RECOVERY TIME vs REVERSE di/dt Reverse di/dt – A/µs 120 10 20 60 80 100 110 130 1007030 40 50 – Clamp-Diode Reverse Recovery Time – ns 140 trr IF = 0.1 A VR = 48 V TA = 25°C TA = 25°C Figure 13 Figure 14 REVERSE di/dt vs FORWARD CURRENT IF – Forward Current – A 0.01 100 200 1010.1 600 1000Reverse di/dt – A/ VCD = 40 V VCD = 20 V TA = 25°C µ s 400 NOTE A: V CD = Vclamp – Vdrain Figure 15

Figure 16. Resistive Switching Waveforms

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996

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Duty Cycle – % 1.4 1.2 0.8 0.6 0.4 01 0 5 0 7 0 1.8 1.6 10060 90 8020 30 40 2.2 2.4 ID – Maximum Drain Current – A N = 1 2.6 2.8 N = 2 N = 3 N = 4 N = 5 N = 7 TA = 25°C N = Number of Outputs Conducting Simultaneously See Note A 1.4 1.2 0.8 0.6 0.4 01 0 5 0 7 0 1.8 1.6 10060 90 8020 30 40 2.2 2.4 ICL – Maximum Clamp-Diode Current – A 2.6 2.8 MAXIMUM CLAMP-DIODE CURRENT vs DUTY CYCLE Duty Cycle – % N = 1 N = 2 N = 3 N = 4 N = 5 N = 7 TA = 25°C N = Number of Outputs Conducting Simultaneously See Note A 0.2 Figure 17 Figure 18 NOTE A: For Figures 17 and 18, d = tw /tc = 10 ms / tc, where tw and tc are defined by the following: tc tw 0.001 0.1 PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 0.01 1 IAS – Peak Avalanche Current – A tav – Time Duration of Avalanche – ms TA = 25°C MAXIMUM DRAIN CURRENT vs DRAIN-SOURCE VOLTAGE VDS – Drain-To-Source Voltage – V 0.4 0.2 0.04 0.02 0.01 0.1 0.1 0.6 100101 – Maximum Drain-Diode DCurrent – A0.06 ID rDS(on) Limit DC Thermal Limit 1 ms TA = 25°C TA = 125°C Figure 19 Figure 20

7-CHANNEL COMMON-SOURCE POWER DMOS ARRAY SLIS019A – SEPTEMBER 1992 – REVISED SEPTEMBER 1996 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL INFORMATION JW (R-GDIP-T24) CERAMIC DUAL-IN-LINE PACKAGE 4040111/B 04/95 0.515 (13,10) 0.560 (14,20) 0.225 (5,70) 0.150 (3,80) 0.610 (15,50) 0.590 (14,99) 0.008 (0,20) 0.012 (0,30) 0.125 (3,17) 0.160 (4,06) Seating Plane 0.020 (0,51) 0.070 (1,78) 0.060 (1,52) 0.100 (2,54) 1.235 (31,30) 0.070 (1,78) MAX 1.290 (32,80) 0.020 (0,51) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only E. Falls within MIL-STD-1835 GDIP5-T24

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N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE 0.975 (24,77) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS 0.310 (7,87) 0.290 (7,37) (23.37) (21.59) Seating Plane 0.010 (0,25) NOM 14/18 PIN ONLY 4040049/C 08/95 0.070 (1,78) MAX A 0.035 (0,89) MAX 0.020 (0,51) MIN 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25)

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

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