TPIC2101

TPIC2101_12 TI1 | Alldatasheet

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SLIS060 – OCTOBER 1995 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 /C00680 V to16 V, 50 mA Max PWM Gate Drive Output /C0068Dual Speed Command Input Capability /C0068Effective Motor Voltage Adjustment /C0068100% Duty Cycle Capability /C0068Low Current (<200 µA) Sleep State /C0068Built-in Soft Start /C0068Over/Under Voltage Protection /C0068Over Current Protection of External FET/IGBT

description

The TPIC2101 is a monolithic integrated control circuit designed for direct current (dc) brush motor control that generates a user-adjustable, fixed-frequency, variable duty cycle, pulse width modulated (PWM) signal primarily to control rotor speed of a permanent magnet dc motor. The TPIC2101 can also be used to control power to other loads such as solenoids and incandescent bulbs. This device drives the gate of an external, low side NMOS power transistor to provide PWM controlled power to a motor or other loads. Inductive current from motor or solenoid loads during PWM off-time is recirculated through an external diode. The TPIC2101 accepts a 0% to 100% PWM signal (auto mode) or a 0 V to 2.2 V differential voltage (manual mode), and internally engages the correct operating mode to accept the input type. The device operates in a sleep state, a run state, or a fault state. In the sleep state the gate-drive (GD) terminal is held low and the overall current draw is less than 200 µA. The normal operating mode of the device is in the run state and is initiated by any speed command. When the device detects an overvoltage or current fault, it enters the fault state. The TPIC2101 is offered in a 14-terminal plastic DIP (N) package, and a SOIC (D) package, and is characterized for operation over the operating free-air temperature range of –40°C to 105°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. V5P5 MAN AUTO SPEED ROSC COSC INT CCS AREF V bat GD GND ILS ILR D or N PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1995, Texas Instruments Incorporated

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional block diagram Sleep AUTO and MAN Logic V5P5V5P5 Vbat Vbat 20 kHz UVSD Sleep Source Select AREF AREF MDET ADET V5P5 AUTO and MAN Input Config CCS Buffer AREF ICCS Bandgap Buffer Vbat Sleep Bandgap and IBIAS Vbat 20 kHz Oscillator and Voltage Ramp Waveform Generator Sleep AREF 20 kHz AREF GD Logic V5P5 ILimit Logic 20 kHz Switched Vbat Vbat OVSD Vbat/8 AREF Sleep OVSD Gate Drive V5P5 UVSD UVSD IFLT 13 5 6 ILR ILS Vbat GD GND MAN AUTO CCS V5P5 AREF ROSC COSC SPEED INT AREF IDET GDDIS V5P5 PWMout Vtrip Vramp Vbat/4 NOTE A: For correct operation, no terminal may be taken below GND.

SLIS060 – OCTOBER 1995 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION V5P5 1 O 5.5 V supply voltage. V5P5 is a regulated voltage supply from Vbat, internally switched to AREF during the run state. This requires a 4.7 µF tantalum capacitor from V5P5 to GND for stability. MAN 2 I Manual control input. MAN is an active high (greater than 5.5 V asserts the manual mode) input that serves as a positive differential input (0-2.3 V full range) for the manual mode. In man mode, Iman is approx. 20×Iccs. AUTO 3 I PWM control input. AUTO is an active low input that remains active if pulsed every 2048 counts of the oscillator frequency. It also serves as a negative differential input for the manual mode. In auto mode, Iauto is approx. 13×Iccs pullup, Iauto is approx. 20×Iccs pulldown in man mode. SPEED 4 O Integrator output. SPEED is an integrator output with a required minimum resistance between SPEED and INT terminals of 20 kΩ (typically 1 second RC time constant, or as required for soft start). ROSC 5 O Oscillator resistor output. ROSC has an external resistor connected to ground which determines the constant charging current of COSC. The IC forces a voltage of Vbat/4 in run state. COSC 6 O Oscillator capacitor output. COSC has an external capacitor connected to ground which determines (with ROSC) switching frequency. f(osc) = 2/(ROSC×COSC) INT 7 I Integrator input. INT is an input from an integrator that requires a 4.7 µF capacitor and a 20 k minimum resistance between the SPEED and INT terminals. ILR 8 I Current limit reference. ILR is an input from a resistor divider off AREF. ILS 9 I Current limit sense. ILS senses drain voltage of external FET. ILS trips within ±10 mV of ILR. GND 10 Ground terminal GD 11 O Gate drive output. GD, PWM output, 0-Vbat voltage, provides a 0-Vbat PWM output pre-drive for an external FET. Vbat 12 I Positive power input. AREF 13 O 5.5 V reference voltage. AREF is a 5.5 V reference voltage switched from V5P5 during the run state. AREF is used as a reference for ILR in current limit detection and is capable of sourcing 2 mA of current. CCS 14 Constant current sink. ICCS equals AREF/(2×R ccs). Requires an external resistor. recommended external components for auto and manual modes (see Figures 2 and 4) TERMINAL NAME NO. V5P5 1 Capacitor – 4.7 µF tantalum MAN 2 Capacitor – 0.1 µF MAN 2 Resistor – 499 Ω , 1%, 100 ppm AUTO 3 Capacitor – 0.47 µF AUTO 3 Resistor – 499 Ω , 1%, 100 ppm SPEED 4 Resistor – 100 kΩ , 1%, 100 ppm to INT terminal, (minimum 20 kΩ) ROSC 5 Resistor – 45.3 kΩ COSC 6 Capacitor – 2200 pF INT 7 Capacitor – 4.7 µF CCS 14 Resistor – 27.4 kΩ , 1%, 100 ppm

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the rotor speed of a permanent-magnet dc motor. This section provides a functional description of the device. state) or by resetting a current fault by entering the sleep state. battery voltages. PWMin is described as the duty cycle of the PWM signal at the AUTO terminal. Figure 1. Motor Voltage vs. Incoming PWM for Various Battery Voltages that the device will not toggle into and out of sleep state or fault condition.

Current through the motor is limited by lowering the GD terminal PWM when a high current situation occurs. This section explains the normal circuit operation for the automatic and manual states. Nominal oscillator frequency is 20-kHz based on the recommended components. Figure 2. Automatic Mode Connections

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Figure 3 illustrates this transfer curve with various battery voltages. Figure 3. Output PWM vs. Incoming PWM for Various Battery Voltages In manual mode, a high input (>5.5V) on the MAN terminal changes the state of the device from sleep to run. a 2 mA current sink to each terminal. The MAN and AUTO current sinks are multiplied 20 X from the CCS current.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 over/under voltage operating The TPIC2101 detects an over or under voltage condition (on the Vbat terminal) and turns off the gate drive circuit. The device remains in this condition until the supply voltage returns to normal operating voltage. Hysteresis assures that the over/under voltage condition does not toggle off and on near the threshold. The INT terminal pulls toward GND through an internal impedance of less than 500 Ω during the over-voltage condition or during sleep state. This ensures a slow ramp up of the GD terminal PWM when the V bat voltage returns to the operating range. current limit operation An over-current condition is detected if the ILS terminal is higher than the ILR terminal while the gate drive (GD terminal) is high. This condition activates a closed-loop control, causing the INT terminal to be pulled low (through an internal resistance less than 500 Ω ) lowering the commanded duty cycle to close the loop. current fault operation During a window of 8192 clock cycles, a latch is set if at least once during the window, a current limit condition is detected. If a current limit condition is set for eight consecutive 8192 clock cycle windows, the gate drive (GD terminal) will be shut off for a disable period of 65536 clock cycles. During the disable period, the INT terminal is pulled to GND through an internal resistance of less than 500 Ω . After the disable period is completed, an internal restart is attempted. If the current limit is present again, as described above, for 8 consecutive windows, the GD and INT terminals are again pulled to GND and the device remains in this current fault state until the device is cycled through a sleep state to run state. However, if the current limit condition is not present during any of the eight 8192 clock cycle windows, the latches for the 8 count window timer and the two cycle shutdown/restart are reset. See timing diagrams, Figures 6, 7, and 8. absolute maximum ratings over the operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Under load dump conditions, the voltage on Vbat can reach 40 V within 1 ms.

SLIS060 – OCTOBER 1995 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 recommended operating conditions MIN NOM MAX UNIT Supply voltage, Vbat 8 12 16 V AREF Input current I(AREF) 0 2 mA Input voltage, VI(MAN), VI(AUTO) (manual mode) 6 16 V Differential voltage, VI(MAN) – VI(AUTO) 0 2.2 V Input voltage, VI(AUTO) (auto mode) 0 5.5 V VI, ILR, ILS 0.5 2.75 V Output resistance, input resistance, R(CCS) 27.2 27.5 27.8 kΩ Output Resistance, ROSC, ro 20 100 kΩ Output Capacitance, COSC, CO 1 5 nF Gate drive frequency f = 2/(ROSC × COSC), f(GD) 20 kHz Gate drive output capacitance, CO(GD) 3300 pF Operating free-air temperature, TA –40 105 °C

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics, Vbat = 8 V to 16 V, TA = 25°C PARAMETER TEST CONDITION MIN TYP MAX UNIT Vbat = 16 V, GD open, f(osc) = 20 kHz, MAN = AUTO =V bat 4 10 mA Ibat Supply current (average), Vbat V bat = 16 V, GD open, f(osc) = 20 kHz, MAN open, Auto mode, AUTO – 99% PWM in 2 10 mA Ib t(Q) Quiescent current (sleep state) Vbt Vbat = 13 V, AUTO and MAN open 150 200 µA Ibat(Q) Q uiescent current (sleep state), Vbat Vbat = 13 V, AUTO shorted to MAN, floating 165 200 µA V(AREF) Voltage supply regulation, AREF I(AREF) = 0 – 2 mA, MAN = AUTO = Vbat 5.225 5.5 5.775 V VIO Input offset voltage, current limit comparator, ILS, ILR AUTO or MAN mode, ILS, ILR common mode, Voltage range 0.5 – 2.75 V, Vint = 4.5 V, Detect I(int) > 100 µA 10 mV IIB Input bias current, current limit comparator, ILS, ILR†, ILS, ILR common mode, Voltage range 0.5 – 2.75 V 250 nA IIO Input offset current, current limit comparator, ILS, ILR† ILS, ILR common mode, Voltage range 0.5 – 2.75 V 100 nA IOL(CLS) Pulldown current, ILS terminal blanking, ILS ILS = 100 mV, GD commanded low 250 360 µA VIL(AUTO) Automatic mode low level input voltage, AUTO MAN open, AUTO mode, Lower VI(AUTO) until VI(SPEED) >2.4V 2.7 3 3.3 V VIH(AUTO) Automatic mode high level input voltage, AUTO MAN open, AUTO mode, Raise VI(AUTO) until VI(SPEED) < 2.4 V 3.6 4 4.4 V II(AUTO) Input current, automatic mode, AUTO MAN open, Auto mode, VI(AUTO) = 0 V –1 –10 mA II(AUTOQ) Input current, auto sleep mode, AUTO MAN open, Sleep state, VI(AUTO) = 0 V –40 –80 µA VIH(MAN) High level input voltage, manual mode, MAN Vbat = 9 V to 16 V, VIH(MAN) = VIH(AUTO), Raise V(MAN) until VI(AREF) > 2.5 V 5 5.5 6 V VIL(MAN) Low level input voltage, manual mode, MANVI(MAN) =VI( AUTO) , Lower VI(MAN) until VI(AREF) < 2.5 V 2.3 2.5 2.7 V VID(MAN) Input voltage, manual mode high differential (high speed command), MAN-AUTO Vbat = 16 V, Vbat –3.5 V < MAN < Vbat 1.7 2.3 V † Indicates electrical parameter not tested in production.

SLIS060 – OCTOBER 1995 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 electrical characteristics, Vbat = 8 V to 16 V, TA = 25°C (continued) PARAMETER TEST CONDITION MIN TYP MAX UNIT VID(low) Input voltage, manual mode low differential (low speed command), MAN–AUTO Vbat –3.5 V < MAN < Vbat+ΔV where “Δ” is the lesser of 2 V and 16 V –Vbat, PWM out @ V(diff) = 0.2 V ≥ PWM out @ VI(DIFF)= 0 V 0.2 V II(MAN) II(AUTO) Input currents, auto and manual mode, MAN, AUTO Vbat –3.5 V < MAN < Vbat +ΔV where “Δ” is the lesser of 2 V and 16 V –Vbat, MAN – AUTO = 0 V to 2 V, R (css) = 27.5 kΩ to GND 1.70 2 2.30 mA II(MANRATIO) Input current, manual mode matching ratio, MAN, AUTO Vbat –3.5 V < MAN < Vbat +ΔV where “Δ” is the lesser of 2 V and 16 V –Vbat, MAN – AUTO = 0 V to 2 V, R css = 27.5 kΩ to GND –7 7 % II(MAN(a)) Input current, man terminal auto mode, MAN Auto mode, MAN = 2.2 V 5 10 15 µA II(MANQ) Input current, man terminal sleep mode, MAN Sleep state, MAN = 2.2 V 5 10 15 µA V(CCS) Constant current sink voltage regulation, CCS Auto or Man mode, I (CCS) = –100 µA 2.58 2.78 2.92 V V(OV) Over voltage shutdown, Vbat Vbat rising from 16 V, INT = 1 V, Detect I(INT) > 100 µA 17 18.5 20 V Vhys(OV) Hysteresis, over voltage, Vbat Vbat rising from 20.1 V, INT = 1 V, Detect I(INT) < 100 µA 0.5 0.8 0.99 V VIT-(UVLO) Under voltage shutdown negative going threshold voltage, Vbat MAN = Vbat, V bat falling from 9 V, Detect AREF < 2.5 V 7 7.5 8 V VIT+(UVHI) Under voltage shutdown positive going threshold voltage, Vbat MAN = Vbat,V bat rising from 6.9 V, Detect AREF > 2.5 V 8 8.5 9 V Vhys(UV) Hysteresis, under voltage, Vbat V(UVHI) – V(UVLO) 0.5 1 V VOH(GD) High level output voltage, gate IGD = –50 mA, INT = 4.5 V, Run state Vbat –3 Vbat V VOH(GD) gg , g drive, GD IGD = –2 mA, INT = 4.5 V, Run state Vbat –0.2 Vbat V VOL(GD) Low level output voltage, gate Run state, I GR = 50 mA, VI(INT) = 0 V, V COSC = 1 V 3.5 V VOL(GD) g, g drive, GD Run state, I GD = 2 mA, INT = 0 V, V COSC = 1 V 0.75 V VGD(SL) Gate voltage, sleep-state, GDSleep state, I GD = 2 mA 0.03 0.75 V I(GDP) Pulldown current, gate drive passive, GD Vbat open, V GD = 0.75 V 7.5 20 µA I(INT) Pulldown current, INT Run state, V ILS > VILR, VI(INT) = 1 V 2 3 mA

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No Current Limit Condition Present in Time Block 4. Condition Not Present For Eight Consecutive 8192 Cycles.

8192 Cycles 8192 Cycles 8192 Cycles 8192 Cycles 8192 CyclesInternal

Figure 6. Current Fault Timing Diagram, Normal State

Current Limit for Eight Consecutive Time Blocks. Disable Output for 65536 Clock Cycles. No Current Limit Condition in Time Block 19. Internal Latch or Counter Reset to Zero. Figure 7. Current Fault Timing Diagram, Over-Current Limit Condition

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Current Limit For Eight Consecutive Time Blocks. Disable Output For 65536 Clock Cycles. Figure 8. Over-Current Fault State Timing Diagram 3

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TYPICAL CHARACTERISTICS 0.5 0.4 0.2 0.1 0.9 0.3 0 5 10 15 20 25 30 – Gate Drive Low Side – V 0.7 0.6 0.8 GATE DRIVE LOW SIDE vs GATE DRIVE CURRENT 35 40 45 50 105°C 25°C –40°C 6.4 3.2 1.6 14.4 4.8 – Gate Drive High Side – V 11.2 9.6 12.8 GATE DRIVE HIGH SIDE vs GATE DRIVE CURRENT 05 0 45403530252015105 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 105°C 25°C –40°C VOL IGD – Gate Drive Current – mA VOH IGD – Gate Drive Current – mA V (bat)– VGD – V Figure 13 Figure 14 1000 500 0 1 02 03 04 05 06 0 Motor RPM – RPM 1500 2000 MOTOR RPM vs INCOMING PULSE WIDTH MODULATION 2500 70 80 90 100 Vbat = 16 V Vbat = 14 V Vbat = 12 V Vbat = 10 V Vbat = 8 V 0 1 02 03 04 05 0 6 0 – Effective Motor Voltage – V EFFECTIVE MOTOR VOLTAGE vs INCOMING PULSE WIDTH MODULATION 70 80 90 100 Vmotor Vbat = 16 V Vbat = 14 V Vbat = 12 V Vbat = 10 V Vbat = 8 V PWM in – Incoming Pulse Width Modulation – % PWM in – Incoming Pulse Width Modulation – % Figure 15 Figure 16

www.ti.com 2-Apr-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPIC2101D OBSOLETE SOIC D 14 TBD Call TI Call TI TPIC2101DG4 OBSOLETE SOIC D 14 TBD Call TI Call TI TPIC2101DR OBSOLETE SOIC D 14 TBD Call TI Call TI TPIC2101N OBSOLETE PDIP N 14 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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