TPIC2030 TI | Alldatasheet
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Technical content
U SLED1 SPM Driver V W MCOM SLED1+ SLED1- SLED2 SLED2- SLED2+ TLT TLT+ TLT- FCS FCS- FCS+ TRK TRK+ TRK- LOAD LOAD- LOAD+ 5 V 5 V 5 V 5 V 5 V 5 V 5 V SPI 5 V TPIC2030 1PX V output DCDC V3P3 10 mF REGOUT REGFB 1.x/3.3 V output 3.3 V Controller Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPIC2030 SLIS171 – DECEMBER 2015 TPIC2030SerialI/FControlled7-ChannelMotor-DriverWith1-ChannelStepDown Regulator
1 Features
1• Serial Peripheral Interface – Maximum Read/Write 35 MHz – 3.3-V Digital I/O
- Actuator and Motor Driver – PWM Control With H-Bridge Output – Focus / Tracking / Tilt Actuator Driver With 12- Bit DAC Control – Sled Motor Drivers With Current Mode, 10-Bit DAC Control – Load Driver With 12-Bit DAC Control – End Position Sensing for Sled Without Position Sensor
- Spindle Motor Driver – Integrated Spindle Current Sense Resistor – Sensor-Less: Rotor Position Sense by Motor BEMF – 12-Bit Spindle DAC – Quick Stop by Automatic Controlled Brake (Auto Short Brake) – LS Mode: Restricted to 25% of Normal Speed
- On-Chip Thermometer (15°C to 165°C/1.2°C)
- Software Controlled Switch for LED Driver With 0.1-A OCP
- Switch – CSW: Low RDS(ON) Current Switch With Selectable OCP Limit (Supposing Use <0.2 A) – LED: Software Control Current Output Port With 0.1-A OCP
- DC-DC Converter – Pin Selectable Conversion Voltage 1.0 V/ 1.2 V/ 1.5 V/ 3.3 V (or Disable) – Improved Efficiency at Low Current With Discontinuous Regulation Mode
- Protection – Individual Thermal Protect Circuit on LED/CSW, Switch, DCDC Converter, SPM, and Actuator – Overcurrent Protection – Undervoltage Lockout (UVLO) and Overvoltage Protection (OVP)
2 Applications
- DVD Player
- CD Player
- Optical Disk Drive
3 Description
TPIC2030 is very-low noise type motor driver IC suitable for slim or ultra-slim DVD reader/writer. The integrated current sense resistance for the spindle motor reduces cost and board area in designs. The TPIC2030 is an integrated solution for driving the spindle motor, sled motor, load motor, and Focus / Tracking / Tilt actuators in an optical disk drive. It also integrates a synchronous DC-DC converter to supply 1.0 or 3.3 V. The discontinuous mode regulation feature on the DC-DC converter improves efficiency at low power consumption. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPIC2030DBT TSSOP (44) 11.10 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram
SLIS171 – DECEMBER 2015 www.ti.com Product Folder Links: TPIC2030 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Table of Contents
7.8 Electrical Characteristics – Spindle Motor Driver
7.9 Electrical Characteristics – Sled Motor Driver Part... 9
7.10 Electrical Characteristics – Focus/
7.16 Electrical Characteristics – Serial Port Voltage
13 Mechanical, Packaging, and Orderable
4 Revision History
December 2015 * Initial release.
2 LOAD+
LOAD– SLED1+ SLED1– SLED2+ SLED2– CP2 CP1 CP3 W SSZ SCLK U SIMO SOMI V SIOV
15 XRESET
PGND_1 PGND_2 PGND_SPM XMUTE TRK- TRK+ SWR_VSEL2 SWR_VSEL1 FCS– FCS+
21 CV3P3A
TLT– AGND P5V_SPM P5V_1 GPOUT LEDO REGOUT REGFB P5V_SW P5V_2 CSWO PGND_SW TPIC2030 www.ti.com SLIS171 – DECEMBER 2015 Product Folder Links: TPIC2030 Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated
5 Description (continued)
Sensorless control using BEMF allows for self-starting and low-noise operation of the spindle motor without requiring external sensors. In addition, the TPIC2030 has many built-in protection features including: spindle driver output current limiting, thermal shutdown, sled-end detection, and power-reset circuit. It also integrates a thermometer to measure IC temperature.
6 Pin Configuration and Functions
SLIS171 – DECEMBER 2015 www.ti.com Product Folder Links: TPIC2030 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) I: Input; O: Output; PS: Power; MISC: Miscellaneous Pin Functions PIN I/O (1) DESCRIPTION NO. NAME
1 PGND_1 PS GND terminal
2 PGND_SW PS GND terminal for DC-DC converters
3 REGOUT O DC-DC converter switching output. Possible GPOUT pin in disable DC-DC
4 P5V_SW PS Power supply terminal for DC-DC converters
5 REGFB I Feedback input terminal for DC-DC converter
6 SIOV PS Power supply terminal for serial port typical 3.3 V
7 SWR_VSEL1 I Setting DC-DC converter output voltage
8 SWR_VSEL2 I Setting DC-DC converter output voltage setting
9 SSZ I SIO slave select low active input terminal
10 SCLK I SIO serial clock input terminal
11 SIMO I SIO slave input master output terminal
12 SOMI O SIO slave output master input terminal
13 XMUTE I XMUTE input terminal to disable driver output
14 XFG O Motor speed signal output
15 XRESET O Power on reset output. Internally pulled up to SIOV
16 GPOUT O General-purpose output (test monitor)
17 CP1 MISC Capacitance connection for charge pump
18 CP2 MISC Capacitance connection for charge pump
19 CP3 MISC Capacitance connection for charge pump
20 AGND PS Ground terminal for internal logic
21 CV3P3A MISC Capacitance terminal for internal 3.3-V regulator
22 P5V_2 PS Power supply terminal
23 PGND_2 PS GND terminal
24 TLT+ O Tilt positive output terminal
25 TLT– O Tilt negative output terminal
26 FCS+ O Focus positive output terminal
27 FCS– O Focus negative output terminal
28 TRK+ O Tracking positive output terminal
29 TRK– O Tracking negative output terminal
30 PGND_SPM PS GND terminal for spindle driver
31 V O V phase output terminal for spindle motor
32 U O U phase output terminal for spindle motor
33 W O W phase output terminal for spindle motor
34 P5V_SPM PS Power supply terminal for Spindle driver
35 P5V_1 PS Power supply terminal
36 MCOM I Motor center tap connection
37 CSWO O Power switch output for 5V OEIC in OPU
38 LEDO O LED output terminal
39 SLED1+ O Sled1 positive output terminal
40 SLED1– O Sled1 negative output terminal
41 SLED2+ O Sled2 positive output terminal
42 SLED2– O Sled2 negative output terminal
43 LOAD+ O Load positive output terminal
44 LOAD– O Load negative output terminal
www.ti.com SLIS171 – DECEMBER 2015 Product Folder Links: TPIC2030 Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT + 5 V supply voltage P5V, P5V_SW, P5V_SPM 6 V Voltage 7 V Spindle output current 1.0 A Spindle output peak current (PW ≦ 2 ms, Duty ≦ 30%) 2.5 A Current 0.8 A Focus/tilt/tracking driver output peak current 1.5 A Current 0.8 A Input/output voltage –0.3 VCC + 0.3 V V Power dissipation 1438 mW Operating temperature –20 75 °C Tstg Storage temperature –50 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±500
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT P5V Operating supply voltage(Apply for P5V) 4.5 5.0 5.5 V VSIOV SIOV voltage 3.0 3.3 3.6 V VSIFH XMUTE, SIMO, SSZ, SCLK pin H level input voltage range 2.2 SIOV + 0.2 V VSIFL XMUTE, SIMO, SSZ, SCLK pin L level input voltage range –0.2 0.8 V VIHB SWR_VSEL1, SWR_VSEL2 pin H level input voltage 2.2 P5V + 0.1 V VILB SWR_VSEL1, SWR_VSEL2 pin L level input voltage range –0.1 0.8 V V disRFB REGFB input level for DC-DC converter disable P5V – 0.1 P5V P5V + 0.1 V ISPMOA Spindle output average current (U, V, W total) 700 mA ISPMO Spindle output current 700 mA ISLDOA Sled output average current 400 mA ILd1Px DC-DC converter load current 1.x V 700 mA ILd3P3 DC-DC converter load current 3.3 V 500 mA IACTOA Focus / tracking / tilt / loading output average current 400 mA ILEDOA LED output average current 50 mA ICSWOA CSWO output average current 200 mA Fck SCLK frequency 30 33.8688 35 MHz TO Operating –20 25 75 ℃
SLIS171 – DECEMBER 2015 www.ti.com Product Folder Links: TPIC2030 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) The JEDEC specification low K (1 s) board design used to derive this data
7.4 Thermal Information
THERMAL METRIC(1) TPIC2030 UNITDBT (TSSOP) TBD PINS RθJA Junction-to-ambient thermal resistance (2) 71.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 19.1 °C/W RθJB Junction-to-board thermal resistance 34.3 °C/W ψJT Junction-to-top characterization parameter 0.5 °C/W ψJB Junction-to-board characterization parameter 33.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
www.ti.com SLIS171 – DECEMBER 2015 Product Folder Links: TPIC2030 Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated (1) Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause permanent damage to the device.
7.5 Electrical Characteristics – Common Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISTBY Standby supply current REGFB = P5V, XSLEEP = L 0.2 mA VCV3 CV3P3 output voltage Iload = 25 mA, REGFB < 3.7 V 2.97 3.3 3.63 V RXM XMUTE pulldown resistor 80 200 320 kΩ RSW1 SWR_VSEL1 pulldown resistor 80 200 320 kΩ RSW2 SWR_VSEL2 pulldown resistor 80 200 320 kΩ RXRST XRESET pullup resistor 13.2 33 52.8 kΩ VXRSTL XRESET low level output voltage SIOV = 3.3 V, IOL = –100 µA 0.3 V TPOR Power on reset delay 15 20 25 ms RXFG XFG output resistor 100 200 300 Ω VXFGH XFG high level output voltage SIOV = 3.3 V, XSLEEP = 1, IOH = 100 µA SIOV – 0.3 V VXFGL XFG low level output voltage SIOV = 3.3 V, XSLEEP = 1, IOL = –100 µA 0.3 V RGPO GPOUT output resistor 100 200 300 Ω VGPOH GPOUT high level output voltage SIOV = 3.3 V, XSLEEP = 1, GPOUT_ENA = 1, GPOUT_HL = 1, IOH = 100 µA SIOV – 0.3 V VGPOL GPOUT low level output voltage SIOV = 3.3 V, XSLEEP = 1, GPOUT_ENA = 1,GPOUT_HL = 0, IOH = 100 µA 0.3 V tTSD Thermal protect on temperature Design specified value 135 150 165 ºC hytTSD Thermal protect hys temperature 5 15 25 ºC Vonvcc P5V Reset on voltage 3.4 3.65 3.9 V Voffvcc P5V Reset off voltage 3.6 3.85 4.1 V VonCV3 CV3P3 reset on voltage 2.4 2.6 2.8 V VoffCV3 CV3P3 reset off voltage 2.5 2.7 2.9 V VonSIO SIOV reset on voltage 2.3 2.5 2.7 V VoffSIO SIOV reset off voltage 2.4 2.6 2.8 V VovpspmOn OVP detection voltage (spindle) (1) 6.0 6.2 6.5 V VovpspmOff OVP release voltage (spindle) (1) 5.8 6.0 6.3 V VovpSpmHys OVP voltage hysteresis (spindle) (1) 110 230 350 mV VovpOn OVP detection voltage (except spindle) (1) 6.3 6.5 6.8 V VovpOff OVP release voltage (except spindle) (1) 6.1 6.3 6.6 V VovpHys OVP voltage hysteresis (except Spindle) (1) 120 240 360 mV
7.6 Electrical Characteristics – Charge Pump Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FCHGP Frequency XSLEEP = 1 132.6 156 179.4 kHz VCHGP Output Voltage Ccp1 = Ccp3 = 0.1 µF IO = –1 mA 7.76 9.7 11.64 V
SLIS171 – DECEMBER 2015 www.ti.com Product Folder Links: TPIC2030 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated (1) Those are value as protection functions only, and stress beyond those listed under Recommended Operating Conditions may cause permanent damage to the device. (2) These value may fall in low temperature at selecting auto discontinuous mode (SWR_BSTAUTON = 1)
7.7 Electrical Characteristics – DC-DC Converter
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rds1pxH High Side FET RDSON REGFB = 0 V REGOUT + 100 mA, +300 mA 0.42 0.62 Ω Rds1pxL Low Side FET RDSON REGFB = 1.2 V REGOUT – 100 mA, –300 mA 0.2 0.4 Ω VO1p0 Output Voltage(1p0V) [SWR_VSEL2, SWR_VSEL1] = 10 0.95 1.0 1.05 V VO1p2 Output Voltage(1p2V) [SWR_VSEL2, SWR_VSEL1] = 01 1.14 1.2 1.26 V VO1p5 Output Voltage(1p5V) [SWR_VSEL2, SWR_VSEL1] = 11 1.425 1.5 1.575 V VO3p3 Output Voltage(3p3V) [SWR_VSEL2, SWR_VSEL1] = 00 3.13 3.3 3.47 V Tdly1p2 Soft start time [SWR_VSEL2, SWR_VSEL1] = 01 From P5V reset off to target 90% 0.66 0.82 0.98 ms RdsO1p2 Output Pull down transistor Rdson REGFB = 1 V (at DC-DC enable) 616 880 1144 Ω Fsw1px Switching frequency 2.125 2.5 2.875 MHz Vrston1px Reset on voltage threshold level 75% 80% 85% Vrstoff1px Reset off voltage threshold level 85% 90% 95% VrstHys Reset off voltage threshold Hys 5% 10% 15% PSRRDCDC PSRR ratio P5V_SW = 5 V + 200 mVpp, IO = 200 mA, F ≈ 100 kHz 26 – – dB IovcDCDC Overcurrent protective level (1)(2) [SWR_VSEL2, SWR_VSEL1] ≠ 00 SWR_BSTAUTON = 0 1.3 1.85 2.4 A [SWR_VSEL2, SWR_VSEL1] = 00 SWR_BSTAUTON = 0 0.65 1.15 1.65 A TMskovctpic mask time of over current protection (1) 0.7 1.0 1.3 ms
7.8 Electrical Characteristics – Spindle Motor Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RttlSPM Total output resistance High side + low side (IncldRcs) IOUT = 0.5 A 0.37 0.7 Ω ResSPM Resolution 12 bit GnSPM Gain Magnification to 1.0 input 5.2 6.0 6.8 times WidDZSPM Spindle dead band Forward 12h 52h 92h Reverse –92h –52h –12h WidDZSPMLS Spindle dead band (LS mode) –40h 0h 40h SPMClim Current limit SPM_RCOM_SEL = 00 801 890 979 mA SPM_RCOM_SEL = 01 882 980 1078 mA SPM_RCOM_SEL = 10 652 725 798 mA SPM_RCOM_SEL = 11 705 784 863 mA
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7.9 Electrical Characteristics – Sled Motor Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RttlSLD Total output resistance High side + low side IO = 0.5 A 0.8 1.2 Ω ResSLD Resolution 10 bit WidDZSLD input Dead band Forward 2h 1Fh 60h Reverse –60h –1Fh –2h GnSLD Sled current gain P5V = 5 V RL = 10 Ω, 2.2 mH VSLED = 7FFh 380 440 500 mA VthEdetSLD END_DET BEMF threshold voltage SLEDENDTH<1:0> = 00 26 46 66 mV SLEDENDTH<1:0> = 01 42 82 122 mV SLEDENDTH<1:0> = 11 9 22 35 mV
7.10 Electrical Characteristics – Focus/ Tilt/Tracking/Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RttlAct Total output resistance High side + low side IO = 0.5 A 0.7 1.1 Ω ResACT Resolution 12 bit VOfstACT Each channel output offset voltage DAC_code = 000h –30 0 30 mV VOfstDACT Output offset voltage focus and tilt DIFF_TLT = 1 –50 0 50 mV GnDAct Difference gain focus and tilt DIFF_TLT = 1 –1 0 1 db GnAct Gain magnification to 1.0 input 5.2 6 6.8 times
7.11 Electrical Characteristics – Load Driver Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RttlLOD Total output resistance High side + low side IO = 0.5 A 0.7 1.1 Ω ResLOD Resolution 12 bit GnLOD Gain Magnification to 1.0 input 5.2 6 6.8 times WidDZLOD Dead band Forward 20h Reverse –21h TocpLOD Output 100% limit time LOAD_05CH = 0 0.64 0.8 0.96 s IocpLOD Overcurrent protective Level LOAD_05CH = 1 at Load_OCP_IUP = 0 120 240 360 mA LOAD_05CH = 1 at Load_OCP_IUP = 1 215 430 645 mA DlyocpLOD Overcurrent protection delay time LOAD_05CH = 1 0.64 0.8 0.96 s
7.12 Electrical Characteristics – Current Switch Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RdsCSW Rds(on) IO = 0.2 A 200 500 mΩ IlmtCSW Current limit threshold level 0.25 0.5 0.75 A ThlCSW Protection hold time 1.47 1.6 2.0 ms
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7.13 Electrical Characteristics – LED Switch Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RdsLED Rds(on) IO = 10 mA 4.4 10 Ω IlmtLED Current limit threshold level P5V = 5 V 0.055 0.1 0.145 A ThlLED Protection hold time 0.35 0.4 0.66 ms
7.14 Electrical Characteristics – Thermometer Part
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ResTEMP Resolution 7 bit TEMPrng Temperature range CHIPTEMP[6:0] = 00 8 15 22 CHIPTEMP[6:0] = 7Fh 155 165 175 FTEMP Update cycle 8 10 12 KHz
7.15 Electrical Characteristics – Actuator Protection
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TintACTTEMP Update cycle 21 26 31 ms (1) Specified by design
7.16 Electrical Characteristics – Serial Port Voltage Levels
over recommended operating free-air temperature range; (P5V ≈ 4.5 to 5.5 V, TA ≈ –20℃ to 75℃, unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SOMI High-level output voltage, VOH IOH = 1 mA 80 % SIOV V SOMI Low-level output voltage, VOL IOL = 1 mA 20% SIOV V SIMO High-level input voltage, VIH 70% SIOV V SIMO Low level input voltage, VIL 20% SIOV V SIMO Input rise/fall time 10% → 90% SIOV 3.5 ns SOMI Output rise/fall time(1) Cload = 30 pF,10% 90% SIOV 10 ns SCLK Internal pulldown resistance 80 200 320 kΩ SSZ Internal pullup resistance 80 200 320 kΩ
7.17 Serial Port I/F Write Timing Requirements
7.18 Serial I/F Read Timing Requirements
Figure 1. Serial Port Write Timing Figure 2. Serial Port Read Timings
7.19 Typical Characteristics
Figure 3. DAC Code vs Duty Cycle for FCS Outputs Figure 4. DAC Code vs Duty Cycle for TLT Outputs
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8 Detailed Description
8.1 Overview
TPIC2030 is low noise type motor driver IC suitable for 5V optical disk drives. The 7-channel driver IC controlled by serial I/F is optimum for driving a spindle motor, a sled motor (stepping motor applicable), a load motor, and Focus / Tracking / Tilt actuators. The integrated current sense resistance for spindle motor current measurement reduces drive system cost. The spindle motor driver part uses integrated sensorless logic to attain very low-noise operation during startup and runtime. By using BEMF feedback, external sensors, such as a Hall device, are not needed to carry out self-starting by the starting circuit or perform position detection. By using the efficient PWM drivers, low-power operation can be achieved by controlling the PWM outputs. Dead zone less control is possible for a Focus / Tracking / Tilt actuator driver. In addition, the spindle part output current limiting circuit, the thermal shut down circuit, and the sled end-detection circuit offer protection for all actuators and motors.
V U MCOM AGND CP1 CP2 CP3 TRK+ TRK– FCS+ TLT+ SOM I SIM O P5V_ 2 XFG SCLK LOAD+ P5V_ SPM PGND_ SW XRESET LEDO CV3P3V SIOV XM UTE GPOUT 5 V CSWO LED O XFG 3.3 V 3.3 V InterLock XRESET GPOUT 0.1 µ SWR_ VSEL2 SWR_ VSEL1
5 V5 V
P5V_ 1 SLED2+ LOAD– BEM F SPM REGFB REGOUT 5 V P5V_ SW 5 V 1.x/3.3V 10 µ10 µ 0.1 µ 2.2 µH Digital Core SLED END Detection CSW LED int 3.3 V Regulator P5V P5V P5V ENDDET_ ENA SLD_ ENA FCS_ ENA TRK_ ENA CSW _ ON LED_ ON Pow er Monitor SIOV SIOV 200 k 200 k 200 k 200 k 200 k 33 k
10 V(P5Vx2)
LOAD_ ENA 10 µ p w r FET XSLEEP 3.3 V p w r FET p w r FET p w r FET p w r FET p w r FET p w r FET CSWO 5 V 0.1 µ 0.1 µ 0.1 µ10 µ 0.1 µ10 µ10 µ PGND_SPM Pre-driver SPM_RCOM SPM_ENA Charge Pump SPM Logic DAC PWM Analog TPIC2030 I-F/B F/B F/B F/B F/B I-F/B Current Limit Pre-driver Detector SSZ SCLK Pre-driver Pre-driver Pre-driver Pre-driver Pre-driver ACTTEMPTH>0 On Chip Thermometer PGND_1-2 SPI I/F ACTTEMP DC-DC Control SLED1+ 200 k SLD_ ENA TLT_ENA FCS– SLED1– SLED2– TLT– DAC PWM DAC PWM DAC PWM DAC PWM DAC PWM SIMO SOMI TPIC2030 SLIS171 – DECEMBER 2015 www.ti.com Product Folder Links: TPIC2030 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Protection Functions
protect target equipment. A protect behavior differ by generated events.
8.3.1.1 Undervoltage Lockout (UVLO)
clear all UVLOMon bits. The power device faults and actions are summarized in Table 1. Table 1. Power Fault Monitor
8.3.1.2 Overvoltage Protection (OVP)
Over voltage protect function is aimed to protect the unit from the supplying hi-voltage. 80% then XRESET signal goes low. supposing a voltage rising by motor BEMF of the high velocity revolution. Figure 5 shows the behavior of over voltage protection.
Figure 5. Overvoltage Protection
8.3.1.3 Overcurrent Protection (OCP)
provided for four circuit blocks, and each threshold are on Table 2. Table 2. OCP Threshold When the large current is detected on each block, device put the output FET to Hi-Z. The amounts of currents and time have specified the detection threshold for every circuit block. ON/OFF actuation in order to make it release. OCPERR (REG7F) and OCP flag (REG7B) are set at OCP detection.
8.3.1.3.1 OCP for DC-DC Converter
Figure 6. Overcurrent Protection DC-DC Converter
8.3.1.3.2 OCP for Load Driver
Figure 7. Overcurrent Protection Load 1-Channel Figure 8. Overcurrent Protection Load 0.5-Channel
8.3.1.3.3 OCP for LED Driver
Figure 9. Overcurrent Protection LED Driver
8.3.1.3.4 OCP for CSW
Figure 10. Overcurrent Protection Current Switch Table 3. SCP Condition Figure 11. Example of SCP (Driver Short to GND)
8.3.1.4 Thermal Protection (TSD)
Table 4. Thermal Sensor Assignment (1) The ACTTEMP data is updated on Register in ACTPROT_OFF = 0 and ACTTEMPTH > 0.
8.3.1.5 Actuator Temperature Protection (ACTTIMER)
too. And spindle channel will be forced Auto short brake and disc motor will stop. level, and reading the value of ACTTEMP. Because of the present value can be read from ACTTEMP (REG78).
Figure 12. Actuator Temperature Protections
8.4 Device Functional Modes
8.4.1 Power-On Reset (POR)
8.4.1.1 Power-Up Sequences
converter output. DC-DC converters stabilize the power up sequence finishes and the part starts to function. rush current and voltage over shoot. Each soft-start sequence takes about 0.8 ms. Figure 13. POR (Enable DCDC) Figure 14. POR (Disable DCDC)
changed Hi-Z and output falling <80%.
8.4.1.2 XRESET
XRESET is shown in Figure 16. Figure 15. POR Block Diagram Figure 16. XRESET Behavior
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8.4.2 XMUTE
If XMUTE signal is inputted during operation, all the outputs will be suspended and the danger will be avoided. TPIC2030 will turn off all enable bits, actuator (TLT_ENA/FCS_ENA/TRK_ENA), SPM_ENA, SLD_ENA, LOAD_ENA and CSW_ON when XMUTE input change to L. LOAD_ENA bit will be disabled only when LOAD_05CH =1. Also log this event to error latch flag XMUTE_DETECT (REG79) and PWRERR (REG7F). If XMUTE_NORST (REG7F) = 1, change of XMUTE will not influence to enable bits.
8.5 Programming
8.5.1 Serial Port Functional Description
All 16-bit transmission data is effective in SSZ=L period. access, and the other processed as a packet for a DAC data setting. There are the following four kinds of serial-data communication packets.
- Write 12 bits DAC data (MSB two bit ≠ 11)
- Write 8 bits control register (MSB two bit = 11)
- Read 8 bits control register (MSB two bit = 11)
- Write 12 bits Focus DAC data＋Read 8 bits status register at the same time (MSB two bit ≠ 11)
8.5.2 Write Operation
For write operation, DSP transmits 16 bit (command + address + data) data a bit every in an order from MSB. 17 or less than 15 SCLK pulses are received during the time that SSZ is low, the whole packet will be ignored. Figure 17. Write 12-Bits DAC Data Figure 18. Write 8-Bits Control Register
8.5.3 Read Operation
clock cycle of SCLK. This mode becomes effective by setting ADVANCE_RD (REG74) = H. Figure 19. Read 8-Bits Control Register
8.5.4 Write and Read Operation
by setting bit RDSTAT_ON_VFCS (REG74) = H. Figure 20. Write 12-Bits Focus DAC Data + Read 8-Bits Status Data
8.6 Register Maps
8.6.1 Register State Transition
Figure 21. Register State Transition Chart
(1) TPIC2030 process as 0 even if set 1.
8.6.2 DAC Register (12-Bit Write Only)
Two difference forms are prepared in 12-bit DAC register, and the forms can be selected by setting VDAC_MAPSW (REG74h). Table 5. DAC Register (VDAC_MAPSW = 0)
(1) TPIC2030 process as 0 even if set 1. Table 6. DAC Register (VDAC_MAPSW = 1)
8.6.3 Control Register
Table 7. Control Register (8bit Read/Write) (1)
8.6.4 Detailed Description of Registers
8.6.4.1 REG01 12-bit DAC for Tilt (VDAC_MAPSW = 0)
Figure 22. Tilt (REG01) Table 8. Tilt (REG01) Field Descriptions 11-0 VTLT w 0 Digital input code for Tilt. be changed after writing VFCS.
8.6.4.2 REG02 12-bit DAC for Focus (VDAC_MAPSW = 0)
Figure 23. Focus (REG02) Table 9. Focus (REG02) Field Descriptions 11-0 VFCS w 0 Digital input code for Focus.
8.6.4.3 REG03 12-bit DAC for Track (VDAC_MAPSW = 0)
Figure 24. Track (REG03) Table 10. Track (REG03) Field Descriptions 11-0 VTRK w 0 Digital input code for Tracking.
8.6.4.4 REG04 10bit DAC for Sled1 (VDAC_MAPSW = 0)
Figure 25. Sled1 (REG04) Table 11. Sled1 (REG04) Field Descriptions 11-2 VSLD1 w 0 Digital input code for Sled1. Two bits on LSB, VSLD1[1:0], will be handled with zero.
8.6.4.5 REG05 10bit DAC for Sled2 (VDAC_MAPSW = 0)
Figure 26. Sled2 (REG05) Table 12. Sled2 (REG05) Field Descriptions 11-2 VSLD2 w 0 Digital input code for Sled2. Two bits on LSB, VSLD2[1:0], will be handled with zero.
8.6.4.6 REG08 12-bit DAC for Spindle (VDAC_MAPSW = 0)
Figure 27. Spindle (REG08) Table 13. Spindle (REG08) Field Descriptions 11-0 VSPM w 0 Digital input code for Spindle.
8.6.4.7 REG09 12-bit DAC for Load (VDAC_MAPSW = 0)
Figure 28. Load (REG09) Table 14. Load (REG09) Field Descriptions 11-0 VLOAD w 0 Digital input code for Load.
8.6.4.8 REG65 8bit Control Register for FBSVR
Figure 29. FBSVR (REG65) Table 15. FBSVR (REG65) Field Descriptions(1)
1 FBSVR_SBRK_OFF
0 TI reserved rw 0
8.6.4.9 REG6D 8bit Control Register for DCCfg
Figure 30. DCCfg (REG6D) Table 16. DCCfg (REG6D) Field Descriptions Prohibit setting in 3.3V output mode.
8.6.4.10 REG6E 8bit Control Register for UtilCfg
Figure 31. UtilCfg (REG6E) Table 17. UtilCfg (REG6E) Field Descriptions
7 GPOUT_HL rw 0 GPOUT (General Purpose Output) pin output selection
6 GPOUT_ENA rw 0 Enable monitor signal output to GPOUT pin
4 SWR_GPIO_CNTL rw 0 Set GPOUT output value (disable DCDC converter)
8.6.4.11 REG6F 8bit Control Register for MonitorSet (REG6F)
Figure 32. MonitorSet (REG6F) Table 18. MonitorSet (REG6F) Field Descriptions
7 ACTTIMER_FLT_MON rw 0 Assign signal to GPIO pin
6 ENDDET_MON rw 0 Assign signal to GPIO pin
5 SIF_TIMEOUTERR_MON rw 0 Assign signal to GPIO pin
4 PWRERR_MON rw 0 Assign signal to GPIO pin
3 TSDERR_MON rw 0 Assign signal to GPIO pin
2 OCPERR_MON rw 0 Assign signal to GPIO pin
1 TSDFAULT_MON rw 0 Assign signal to GPIO pin
8.6.4.12 REG70 8bit Control Register for DriverEna
Figure 33. DriverEna (REG70) Table 19. DriverEna (REG70) Field Descriptions
7 TLT_ENA rw 0 1 : Tilt enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
6 FCS_ENA rw 0 1: Focus enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
5 TRK_ENA rw 0 1: Track enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
4 SPM_ENA rw 0 1: Spindle enable (with XSLEEP=1)
It’s reset when XMUTE changes to L.
3 SLD_ENA rw 0 1: Sled enable (with XSLEEP=1)
It’s reset when XMUTE changes to L. 2 SWR_MD_BURST rw 0 1 : Enable DCDC converter discontinuous regulation mode. discontinuous mode. Holds a former value after XMUTE = L event.
1 LOAD_ENA rw 0 1 : LOAD enable (with XSLEEP=1)
sharing the DAC PWM module. Load priority is higher than TRK_ENA.
0 XSLEEP rw 0 1: Operation mode 0 : Power save mode
(regardless of setting xxx_ENA bit is 1) when setting XSLEEP to 0. Therefore set 1 to XSLEEP before setting each enable bits.
8.6.4.13 REG71 8bit Control Register for FuncEna
Figure 34. FuncEna (REG71) Table 20. FuncEna (REG71) Field Descriptions
7 SPM_LSMODE rw 0 0 : Spindle rotation mode
6 ENDDET_ENA rw 0 1 : use Sled end detection enable ( with SLD_ENA=1)
5 SWR_BSTAUTON rw 0 1 : Enable auto DCDC converter discontinuous regulation mode. automatically. Holds a former value after XMUTE = L event.
4 LED_ON rw 0 1 : LEDO enable ( with XSLEEP=1)
3 CSW_ON rw 0 1 : CSWO enable ( with XSLEEP=1)
2 TEMPMON_ENA rw 0 1: enable chip temperature monitoring ( with XSLEEP=1)
8.6.4.14 REG72 8bit Control Register for ACTCfg
Figure 35. ACTCfg (REG72) Table 21. ACTCfg (REG72) Field Descriptions
6 LOADPROT_OFF rw 0 1: Load Overcurrent Protection OFF
5 ACTPROT_OFF rw 0 0 : Actuator protection ON 1 : Actuator Fault monitor disable (No
By writing value 0x00, ACTTIMER_PROT flag is cleared.
8.6.4.15 REG73 8bit Control Register for Parm0
Figure 36. Parm0 (REG73) Table 22. Parm0 (REG73) Field Descriptions 5 SLEDEND_HZTIME rw 0 Time window for sled end detection. Caution) Need to recycle ENDDET_ENA=0→1 after writing this bit.
0 XMUTE_NORST rw 0 Reset driver enable bit (XXX_ENA and CSW_ON) register at XMUTE =
1: XMUTE status does not influence enable bit.
8.6.4.16 REG74 8bit Control Register for OptSet
Figure 37. OptSet (REG74) Table 23. OptSet (REG74) Field Descriptions
7 DIFF_TLT rw 0 1 : Differential Tilt mode enable (with TLT_ENA=FCS_ENA=1)
Use for Slot-in model or step down tray model.
5 RDSTAT_ON_VFCS rw 0 Set Read status data (REG7F) at VFCS write command (REG02)
4 VSLD2_POL rw 0 change direction of SLED rotation
3 LOAD_OCP_IUP rw 0 Select over current protection (OCP) threshold for Load channel current
2 TI reserved rw 0
1 SOMI_HIZ rw 0 0: SOMI line High-Z at bus idling time. 1: SOMI line Pull Down at bus idling time.
0 VDAC_MAPSW rw 0 Selection of DAC register channel assignments (REG01~09)
8.6.4.17 REG76 8bit Control Register for WriteEna
Figure 38. WriteEna (REG76) Table 24. WriteEna (REG76) Field Descriptions
7 WRITE_ENABLE 0 0: Register Write disable except REG76
8.6.4.18 REG77 8bit Control Register for ClrReg
Figure 39. ClrReg (REG77) Table 25. ClrReg (REG77) Field Descriptions
7 RST_INDAC w 0 1 : Reset all 12-bit input DAC register (REG01~0B)
6 RST_REGS w 0 1 : Reset all 8bit R/W Registers (REG70h~77h, 60h-6Fh)
5 RST_ERR_FLAG w 0 1 : Reset Fault Flag Latch (REG7F[5:1], REG79~REG7B)
8.6.4.19 REG78 8bit Control Register for ActTemp
Figure 40. ActTemp (REG78) Table 26. ActTemp (REG78) Field Descriptions
5 ACT_TIMER_PROT r 0 ACT timer protection flag
1: ACT Timer Protection has detected and latched. 4-0 ACTTEMP r 0 An integrated value of ACT_TIMER counters at present.
8.6.4.20 REG79 8bit Control Register for UVLOMon
Figure 41. UVLOMon (REG79) Table 27. UVLOMon (REG79) Field Descriptions
4 UVLO_P5V r 0 UVLO (Under Voltage Lock Out) flag for detection Low P5V supply(1)
2 UVLO_SIOV r 0 UVLO flag for detection Low SIOV(1)
1 UVLO_SWR r 0 UVLO flag for detection Low DCDC(1)
0 OVP_P5V r 0 Over voltage protection flag for P5Vsply(1)
8.6.4.21 REG7A 8bit Control Register for TsdMon
Figure 42. TsdMon (REG7A) Table 28. TsdMon (REG7A) Field Descriptions
7 TSD_FAULT_SWR r 0 Pre alert of thermal protection for DCDC converter block(1)
6 TSD_FAULT_SPM r 0 Pre alert of thermal protection of Spindle block(1)
5 TSD_FAULT_ACT r 0 Pre alert of thermal protection of Focus /Track /Tilt Sled1 /Sled2 /
4 TSD_FAULT_LEDCS
3 TSD_SWR r 0 Thermal protection flag for DCDC converter block(1)
2 TSD_SPM r 0 Thermal protection flag for Spindle(1)
1 TSD_ACT r 0 Thermal protection flag for Focus /Track /Tilt Sled1 /Sled2 /Load(1)
0 TSD_ LEDCSW r 0 Thermal protection flag for CSW/LED(1)
8.6.4.22 REG7B 8bit Control Register for ProtMon
Figure 43. ProtMon (REG7B) Table 29. ProtMon (REG7B) Field Descriptions
7 OCP_SWR r 0 Overcurrent protection flag bit for DCDC converter(1)
6 OCP_LOAD r 0 Overcurrent protection flag bit for Load channel(1)
5 OCP_LED r 0 Overcurrent protection flag bit for LED channel(1)
4 OCP_CSW r 0 Overcurrent protection flag bit for CSW channel(1)
3 SCP_SPM r 0 Short circuit protection flag bit for spindle channe(1)
2 SCP_SLED r 0 Short circuit protection flag bit for sled channe(1)
1 SCP_LOAD r 0 Short circuit protection flag bit for load channe(1)
0 SCP_ACT r 0 Short circuit protection flag bit for Fcs/Trk/Tilt channel(1)
8.6.4.23 REG7C 8bit Control Register for TempMon
Figure 44. TempMon (REG7C) Table 30. TempMon (REG7C) Field Descriptions
7 CHIPTEMP_STATUS r 0 1: New data CHIPTEMP[6:0] is updated
It will be cleared after reading.
8.6.4.24 REG7E 8bit Control Register for Version
Figure 45. Version (REG7E) Table 31. Version (REG7E) Field Descriptions
8.6.4.25 REG7F 8bit Control Register for Status
Figure 46. Status (REG7F) Table 32. Status (REG7F) Field Descriptions
7 ACTTIMER_FAULT r 0 Status flag of ACTTIMER protection
1: Pre alert of ACTTIMER protection. It is close to the threshold level. You can get current ACTTIMER value in REG78.
6 ENDDET r 0 status flag of END detection
5 SIF_TIMEOUTERR r 0 error flag of serial I/F watch dog timer
4 PWRERR r 0 error flag of Power
3 TSDERR r 0 error flag of any over thermal protections
2 OCPERR r 0 error flag of any over current protection
1 TSDFAULT r 0 warning of TSD of any thermal protection
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
- Operate every driver channel after 5-V power supplied and stable.
- Appropriate capacity of de-coupling capacitor is required enough value of over 10μF due to reduce influence of PWM switching noise. And the P5V pin needs to connect a filter of 1μF. It is effective to put bypass capacitor(about 0.1uF) near Power pin（P5V_1,P5V_2, P5V_SW,P5V_SPM）for PWM switching noise reduction on power and GND line.
- Much current flow to driver circuits, to consider as below matters. – Pattern-lay-out and line-impedance. And noise influence from supply line.
9.1 Application Information
9.1.1 DAC Type
Table 33. DAC Type
9.1.2 Example Sampling Rate of 12-Bit DAC for FCS/TRK/TLT
9 G D F
1.25 MHz
5 MHz
Figure 47. Example of 12-Bit DAC Conversion Time (FCS/TRK/TLT)
9.1.3 Digital Input Coding
- bit[11:0] is the digital input value, range 000000000000b to 111111111111b. (2)
Table 34. DAC Format
Figure 48. Output Voltage vs DAC Code
9.1.4 Example Timing of Target Control System
system parameter is listed in . It takes 0.51 µs for transmit a 16-bit data packet to TPIC2030 with 35 MHz SCLK. Table 35. Example Timing of Target Control System
Figure 49. Example DAC Control
9.1.5 Spindle Motor Driver Part
mode by detecting the rotor position by BEMF signal from the spindle motor coil. Figure 50. Spindle Operating Sequence
- It is recommended to use down-edge of FG signal for monitoring FG frequency. The FG terminal needs to be pull up to the appropriate supply voltage by external resistor.
- Short Brake mode is asserted after 300 ms of FG signal stays L-level in deceleration.
- The FG output is set to H-level in sleep mode in order to reduce sleep mode current.
- This value is the nominal number of using motor with 16-poles.
- First of all, power supply voltage of P5V must be supplied before any signals input.
9.1.5.1 Spindle PWM Control
in the width of plus or minus 0x52 focusing on zero. Figure 51. Spindle PWM Control
9.1.5.2 Auto Short Brake Function
TPIC2030 provides auto short brake function which is selecting brake mode automatically by motor speed. Auto Short Brake is the intelligent brake function that includes 2 modes, Short Brake and Active Brake. Table 36. Brake Mode Figure 52. Brake Mode Selections This value is the nominal number of using motor with 16-poles motor.
9.1.5.3 Spindle Low Speed Mode
mode is always SHORT BRAKE. shows the output duty of LS mode. Figure 53. Spindle PWM Control (Low Speed Mode)
9.1.5.4 Spindle Driver Current Limit Circuit
This IC builds in the SPM current sense resistor which can select resistor value. . current by reducing PWM duty when detecting over current conditions. shows resistor value. A limit current value can be calculated from following formulas. Table 37. SPM Current Sense Resistor
9.1.6 Sled Driver Part
9.1.6.1 Sled Channel Input vs Output PWM Duty
Figure 54. Sled Output Current
- Both outputs of SLED1/2 are L when input code is in dead band.
9.1.6.2 Sled End Detect Function
bit will be cleared at the BEMF voltage exceed threshold again. Figure 55. Timing of Sled End Detection
- In order to perform high-precision detection, the sled motor needs to generate higher BEMF voltage. BEMF level depends on the stepping motor characteristic and its speed.
- BEMF detection level is selectable 22, 46, 86 mV.
9.1.7 Load Driver Part
9.1.7.1 Load Channel Input vs Output PWM Duty
to other actuator channels. Load driver is shared with the TRK driver.
Figure 56. Load Output Duty
- Output voltage is controlled by PWM
- Both LOAD+ and LOAD- are connected to PGND through the internal clamp diode respectively.
9.1.8 Focus/Track/Tilt Driver Part
Figure 57. FCS/TRK/TLT Output Duty
9.1.8.1 Differential Tilt Mode
necessary to write VFCS data when set VTLT. In differential mode, the output value is calculated as follows.
9.1.9 Step-Down Synchronous DC-DC Converter
have fast transient response.
- • • •
- • • •
- • • •
- • • • TPIC2030 www.ti.com SLIS171 – DECEMBER 2015 Product Folder Links: TPIC2030 Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated (1) It is necessary to maintain REGFB > 3.7 V for 100 µs in DC-DC working. and bypass capacitor(s). The gate drivers and compensations are all internal to the chip. The required input supply is 5 V for P5V_SW. It has a soft start approximately about 0.8 ms to limit the in-rush current when the regulator comes alive. The soft-start circuit uses the internal clock to profile its ramp. It’s able to up 2%, 3.8% and 5.4% of the output voltage by setting SWR_VOUTUP (REG6D) for 1.2 V and 1.5 V,
Table 38. Output Voltage Setting
9.1.9.1 Discontinuous Regulation Mode
Figure 58. Discontinuous Regulation Mode
9.1.9.2 High Efficiency Mode (in Discontinuous Regulation Mode)
1.2 V, and 1.5 V. This mode is selected by SWR_BST_HEFF = 1 (REG6D) in discontinuous mode.
9.1.10 Monitor Signal on GPOUT
9.2 Typical Application
Figure 59. Example of Application Circuit Table 39. Pin Connection When Specific Function is
9.2.1 Design Requirements
- Motor configuration: The user can use all motor channels or some of them.
- Power up devices with a 5-V supply.
9.2.2 Detailed Design Procedure
After power up on 5-V supply, the following values may be written to the following registers to enable motors.
- Set WRITE_ENABLE = 1 on REG76 via SPI.
- Enable motor channel by ENA_XXX bits on REG70
- Change the DAC settings for each motor in REG01-0B. Then, output channels will start driving load.
Table 40. Recommended External Components Table 41. Specific for DCDC Converter Components
9.2.3 Application Curves
Figure 60. DAC Code vs Duty Cycle for LOAD Outputs Figure 61. DAC Code vs Duty Cycle for TRK Outputs
10 Power Supply Recommendations
All driver channels should be operated after the required power is supplied and stable. switching noise. The P5V1, P5V2, P5V_SW, and P5V_SPM pins must connect to 10-μF decoupling capacitors.
11 Layout
11.1 Layout Guidelines
- CV3P3V requires an external capacitor. Because these are reference voltage for device, locate the capacitor
as close to device as possible. Keep away from noise sources.
- TI recommends SCLK ground shielding.
- Place the inductor for the DC-DC converter as close to the chip as possible, and keep the feedback line to
the REGFB pin as short as possible.
11.2 Layout Example
Figure 62. Layout Recommendation
www.ti.com SLIS171 – DECEMBER 2015 Product Folder Links: TPIC2030 Submit Documentation FeedbackCopyright © 2015, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TPIC2030DBTRG4 Active Production TSSOP (DBT) | 44 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -20 to 75 TPIC2030 TPIC2030DBTRG4.A Active Production TSSOP (DBT) | 44 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -20 to 75 TPIC2030 TPIC2030DBTRG4.B Active Production TSSOP (DBT) | 44 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -20 to 75 TPIC2030 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com PACKAGE OUTLINE C 42X 0.5 10.5 44X 0.27 0.17 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 11.1 10.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightDBT0044A SMALL OUTLINE PACKAGE 4220223/A 02/2017
0.08 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 1.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
44X (1.5) 44X (0.3) 42X (0.5) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightDBT0044A SMALL OUTLINE PACKAGE 4220223/A 02/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM SYMM 22 23 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 44X (1.5) 44X (0.3) 42X (0.5) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightDBT0044A SMALL OUTLINE PACKAGE 4220223/A 02/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 8X SYMM SYMM 22 23
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